src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31
  32 extern "C" {
  33 #include "brw_vs.h"
  34 #include "brw_context.h"
  35 #include "brw_eu.h"
  36 };
  37
  38 #include "glsl/ir.h"
  39
  40 namespace brw {
  41
  42 class dst_reg;
  43
  44 /**
  45  * Common helper for constructing swizzles.  When only a subset of
  46  * channels of a vec4 are used, we don't want to reference the other
  47  * channels, as that will tell optimization passes that those other
  48  * channels are used.
  49  */
  50 static unsigned
  51 swizzle_for_size(int size)
  52 {
  53    static const unsigned size_swizzles[4] = {
  54       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
  55       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
  56       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),
  57       BRW_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W),
  58    };
  59
  60    assert((size >= 1) && (size <= 4));
  61    return size_swizzles[size - 1];
  62 }
  63
  64 enum register_file {
  65    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
  66    GRF = BRW_GENERAL_REGISTER_FILE,
  67    MRF = BRW_MESSAGE_REGISTER_FILE,
  68    IMM = BRW_IMMEDIATE_VALUE,
  69    HW_REG, /* a struct brw_reg */
  70    ATTR,
  71    UNIFORM, /* prog_data->params[hw_reg] */
  72    BAD_FILE
  73 };
  74
  75 class reg
  76 {
  77 public:
  78    /** Register file: ARF, GRF, MRF, IMM. */
  79    enum register_file file;
  80    /** virtual register number.  0 = fixed hw reg */
  81    int reg;
  82    /** Offset within the virtual register. */
  83    int reg_offset;
  84    /** Register type.  BRW_REGISTER_TYPE_* */
  85    int type;
  86    struct brw_reg fixed_hw_reg;
  87
  88    /** Value for file == BRW_IMMMEDIATE_FILE */
  89    union {
  90       int32_t i;
  91       uint32_t u;
  92       float f;
  93    } imm;
  94 };
  95
  96 class src_reg : public reg
  97 {
  98 public:
  99    /* Callers of this ralloc-based new need not call delete. It's
 100     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 101    static void* operator new(size_t size, void *ctx)
 102    {
 103       void *node;
 104
 105       node = ralloc_size(ctx, size);
 106       assert(node != NULL);
 107
 108       return node;
 109    }
 110
 111    void init()
 112    {
 113       memset(this, 0, sizeof(*this));
 114
 115       this->file = BAD_FILE;
 116    }
 117
 118    src_reg(register_file file, int reg, const glsl_type *type)
 119    {
 120       init();
 121
 122       this->file = file;
 123       this->reg = reg;
 124       if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
 125          this->swizzle = swizzle_for_size(type->vector_elements);
 126       else
 127          this->swizzle = SWIZZLE_XYZW;
 128    }
 129
 130    /** Generic unset register constructor. */
 131    src_reg()
 132    {
 133       init();
 134    }
 135
 136    src_reg(float f)
 137    {
 138       init();
 139
 140       this->file = IMM;
 141       this->type = BRW_REGISTER_TYPE_F;
 142       this->imm.f = f;
 143    }
 144
 145    src_reg(uint32_t u)
 146    {
 147       init();
 148
 149       this->file = IMM;
 150       this->type = BRW_REGISTER_TYPE_UD;
 151       this->imm.u = u;
 152    }
 153
 154    src_reg(int32_t i)
 155    {
 156       init();
 157
 158       this->file = IMM;
 159       this->type = BRW_REGISTER_TYPE_D;
 160       this->imm.i = i;
 161    }
 162
 163    bool equals(src_reg *r);
 164    bool is_zero() const;
 165    bool is_one() const;
 166
 167    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 168
 169    explicit src_reg(dst_reg reg);
 170
 171    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 172    bool negate;
 173    bool abs;
 174
 175    src_reg *reladdr;
 176 };
 177
 178 class dst_reg : public reg
 179 {
 180 public:
 181    /* Callers of this ralloc-based new need not call delete. It's
 182     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 183    static void* operator new(size_t size, void *ctx)
 184    {
 185       void *node;
 186
 187       node = ralloc_size(ctx, size);
 188       assert(node != NULL);
 189
 190       return node;
 191    }
 192
 193    void init()
 194    {
 195       memset(this, 0, sizeof(*this));
 196       this->file = BAD_FILE;
 197       this->writemask = WRITEMASK_XYZW;
 198    }
 199
 200    dst_reg()
 201    {
 202       init();
 203    }
 204
 205    dst_reg(register_file file, int reg)
 206    {
 207       init();
 208
 209       this->file = file;
 210       this->reg = reg;
 211    }
 212
 213    dst_reg(register_file file, int reg, const glsl_type *type, int writemask)
 214    {
 215       init();
 216
 217       this->file = file;
 218       this->reg = reg;
 219       this->type = brw_type_for_base_type(type);
 220       this->writemask = writemask;
 221    }
 222
 223    dst_reg(struct brw_reg reg)
 224    {
 225       init();
 226
 227       this->file = HW_REG;
 228       this->fixed_hw_reg = reg;
 229    }
 230
 231    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 232
 233    explicit dst_reg(src_reg reg);
 234
 235    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 236
 237    src_reg *reladdr;
 238 };
 239
 240 class vec4_instruction : public exec_node {
 241 public:
 242    /* Callers of this ralloc-based new need not call delete. It's
 243     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 244    static void* operator new(size_t size, void *ctx)
 245    {
 246       void *node;
 247
 248       node = rzalloc_size(ctx, size);
 249       assert(node != NULL);
 250
 251       return node;
 252    }
 253
 254    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 255                     dst_reg dst = dst_reg(),
 256                     src_reg src0 = src_reg(),
 257                     src_reg src1 = src_reg(),
 258                     src_reg src2 = src_reg());
 259
 260    struct brw_reg get_dst(void);
 261    struct brw_reg get_src(int i);
 262
 263    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 264    dst_reg dst;
 265    src_reg src[3];
 266
 267    bool saturate;
 268    bool predicate_inverse;
 269    uint32_t predicate;
 270
 271    int conditional_mod; /**< BRW_CONDITIONAL_* */
 272
 273    int sampler;
 274    int target; /**< MRT target. */
 275    bool shadow_compare;
 276
 277    bool eot;
 278    bool header_present;
 279    int mlen; /**< SEND message length */
 280    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 281
 282    uint32_t offset; /* spill/unspill offset */
 283    /** @{
 284     * Annotation for the generated IR.  One of the two can be set.
 285     */
 286    ir_instruction *ir;
 287    const char *annotation;
 288
 289    bool is_tex();
 290    bool is_math();
 291 };
 292
 293 class vec4_visitor : public ir_visitor
 294 {
 295 public:
 296    vec4_visitor(struct brw_vs_compile *c,
 297                 struct gl_shader_program *prog, struct brw_shader *shader);
 298    ~vec4_visitor();
 299
 300    dst_reg dst_null_f()
 301    {
 302       return dst_reg(brw_null_reg());
 303    }
 304
 305    dst_reg dst_null_d()
 306    {
 307       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 308    }
 309
 310    struct brw_context *brw;
 311    const struct gl_vertex_program *vp;
 312    struct intel_context *intel;
 313    struct gl_context *ctx;
 314    struct brw_vs_compile *c;
 315    struct brw_vs_prog_data *prog_data;
 316    struct brw_compile *p;
 317    struct brw_shader *shader;
 318    struct gl_shader_program *prog;
 319    void *mem_ctx;
 320    exec_list instructions;
 321
 322    char *fail_msg;
 323    bool failed;
 324
 325    /**
 326     * GLSL IR currently being processed, which is associated with our
 327     * driver IR instructions for debugging purposes.
 328     */
 329    ir_instruction *base_ir;
 330    const char *current_annotation;
 331
 332    int *virtual_grf_sizes;
 333    int virtual_grf_count;
 334    int virtual_grf_array_size;
 335    int first_non_payload_grf;
 336    int *virtual_grf_def;
 337    int *virtual_grf_use;
 338    dst_reg userplane[MAX_CLIP_PLANES];
 339
 340    /**
 341     * This is the size to be used for an array with an element per
 342     * reg_offset
 343     */
 344    int virtual_grf_reg_count;
 345    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 346    int *virtual_grf_reg_map;
 347
 348    bool live_intervals_valid;
 349
 350    dst_reg *variable_storage(ir_variable *var);
 351
 352    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 353
 354    src_reg src_reg_for_float(float val);
 355
 356    /**
 357     * \name Visit methods
 358     *
 359     * As typical for the visitor pattern, there must be one \c visit method for
 360     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 361     * the hierarchy should not have \c visit methods.
 362     */
 363    /*@{*/
 364    virtual void visit(ir_variable *);
 365    virtual void visit(ir_loop *);
 366    virtual void visit(ir_loop_jump *);
 367    virtual void visit(ir_function_signature *);
 368    virtual void visit(ir_function *);
 369    virtual void visit(ir_expression *);
 370    virtual void visit(ir_swizzle *);
 371    virtual void visit(ir_dereference_variable  *);
 372    virtual void visit(ir_dereference_array *);
 373    virtual void visit(ir_dereference_record *);
 374    virtual void visit(ir_assignment *);
 375    virtual void visit(ir_constant *);
 376    virtual void visit(ir_call *);
 377    virtual void visit(ir_return *);
 378    virtual void visit(ir_discard *);
 379    virtual void visit(ir_texture *);
 380    virtual void visit(ir_if *);
 381    /*@}*/
 382
 383    src_reg result;
 384
 385    /* Regs for vertex results.  Generated at ir_variable visiting time
 386     * for the ir->location's used.
 387     */
 388    dst_reg output_reg[BRW_VERT_RESULT_MAX];
 389    const char *output_reg_annotation[BRW_VERT_RESULT_MAX];
 390    int uniform_size[MAX_UNIFORMS];
 391    int uniform_vector_size[MAX_UNIFORMS];
 392    int uniforms;
 393
 394    struct hash_table *variable_ht;
 395
 396    bool run(void);
 397    void fail(const char *msg, ...);
 398
 399    int virtual_grf_alloc(int size);
 400    void setup_uniform_clipplane_values();
 401    int setup_uniform_values(int loc, const glsl_type *type);
 402    void setup_builtin_uniform_values(ir_variable *ir);
 403    int setup_attributes(int payload_reg);
 404    int setup_uniforms(int payload_reg);
 405    void setup_payload();
 406    void reg_allocate_trivial();
 407    void reg_allocate();
 408    void move_grf_array_access_to_scratch();
 409    void move_uniform_array_access_to_pull_constants();
 410    void move_push_constants_to_pull_constants();
 411    void split_uniform_registers();
 412    void pack_uniform_registers();
 413    void calculate_live_intervals();
 414    bool dead_code_eliminate();
 415    bool virtual_grf_interferes(int a, int b);
 416    bool opt_copy_propagation();
 417    bool opt_algebraic();
 418    bool opt_compute_to_mrf();
 419
 420    vec4_instruction *emit(vec4_instruction *inst);
 421
 422    vec4_instruction *emit(enum opcode opcode);
 423
 424    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 425
 426    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 427                           src_reg src0, src_reg src1);
 428
 429    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 430                           src_reg src0, src_reg src1, src_reg src2);
 431
 432    vec4_instruction *emit_before(vec4_instruction *inst,
 433                                  vec4_instruction *new_inst);
 434
 435    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 436    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 437    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 438    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 439    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 440    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 441    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 442    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 443    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 444    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 445    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 446    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 447    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 448    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 449    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 450    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 451                          uint32_t condition);
 452    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 453    vec4_instruction *IF(uint32_t predicate);
 454    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 455    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 456    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 457
 458    int implied_mrf_writes(vec4_instruction *inst);
 459
 460    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 461                                dst_reg dst,
 462                                src_reg src,
 463                                vec4_instruction *pre_rhs_inst,
 464                                vec4_instruction *last_rhs_inst);
 465
 466    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 467    void visit_instructions(const exec_list *list);
 468
 469    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 470    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 471    void emit_if_gen6(ir_if *ir);
 472
 473    void emit_block_move(dst_reg *dst, src_reg *src,
 474                         const struct glsl_type *type, uint32_t predicate);
 475
 476    void emit_constant_values(dst_reg *dst, ir_constant *value);
 477
 478    /**
 479     * Emit the correct dot-product instruction for the type of arguments
 480     */
 481    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 482
 483    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 484                     dst_reg dst, src_reg src0);
 485
 486    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 487                     dst_reg dst, src_reg src0, src_reg src1);
 488
 489    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 490                  dst_reg dst, const src_reg &src);
 491
 492    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 493    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 494    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 495    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 496    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 497    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 498
 499    void emit_ndc_computation();
 500    void emit_psiz_and_flags(struct brw_reg reg);
 501    void emit_clip_distances(struct brw_reg reg, int offset);
 502    void emit_generic_urb_slot(dst_reg reg, int vert_result);
 503    void emit_urb_slot(int mrf, int vert_result);
 504    void emit_urb_writes(void);
 505
 506    src_reg get_scratch_offset(vec4_instruction *inst,
 507                               src_reg *reladdr, int reg_offset);
 508    src_reg get_pull_constant_offset(vec4_instruction *inst,
 509                                     src_reg *reladdr, int reg_offset);
 510    void emit_scratch_read(vec4_instruction *inst,
 511                           dst_reg dst,
 512                           src_reg orig_src,
 513                           int base_offset);
 514    void emit_scratch_write(vec4_instruction *inst,
 515                            src_reg temp,
 516                            dst_reg orig_dst,
 517                            int base_offset);
 518    void emit_pull_constant_load(vec4_instruction *inst,
 519                                 dst_reg dst,
 520                                 src_reg orig_src,
 521                                 int base_offset);
 522
 523    bool try_emit_sat(ir_expression *ir);
 524    void resolve_ud_negate(src_reg *reg);
 525
 526    bool process_move_condition(ir_rvalue *ir);
 527
 528    void generate_code();
 529    void generate_vs_instruction(vec4_instruction *inst,
 530                                 struct brw_reg dst,
 531                                 struct brw_reg *src);
 532
 533    void generate_math1_gen4(vec4_instruction *inst,
 534                             struct brw_reg dst,
 535                             struct brw_reg src);
 536    void generate_math1_gen6(vec4_instruction *inst,
 537                             struct brw_reg dst,
 538                             struct brw_reg src);
 539    void generate_math2_gen4(vec4_instruction *inst,
 540                             struct brw_reg dst,
 541                             struct brw_reg src0,
 542                             struct brw_reg src1);
 543    void generate_math2_gen6(vec4_instruction *inst,
 544                             struct brw_reg dst,
 545                             struct brw_reg src0,
 546                             struct brw_reg src1);
 547    void generate_math2_gen7(vec4_instruction *inst,
 548                             struct brw_reg dst,
 549                             struct brw_reg src0,
 550                             struct brw_reg src1);
 551
 552    void generate_urb_write(vec4_instruction *inst);
 553    void generate_oword_dual_block_offsets(struct brw_reg m1,
 554                                           struct brw_reg index);
 555    void generate_scratch_write(vec4_instruction *inst,
 556                                struct brw_reg dst,
 557                                struct brw_reg src,
 558                                struct brw_reg index);
 559    void generate_scratch_read(vec4_instruction *inst,
 560                               struct brw_reg dst,
 561                               struct brw_reg index);
 562    void generate_pull_constant_load(vec4_instruction *inst,
 563                                     struct brw_reg dst,
 564                                     struct brw_reg index);
 565 };
 566
 567 } /* namespace brw */
 568
 569 #endif /* BRW_VEC4_H */