src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39 #include "intel_asm_annotation.h"
  40
  41 #ifdef __cplusplus
  42 }; /* extern "C" */
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52 #ifdef __cplusplus
  53 extern "C" {
  54 #endif
  55
  56 void
  57 brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
  58                                       struct brw_vue_prog_key *key,
  59                                       GLuint id, struct gl_program *prog);
  60
  61 #ifdef __cplusplus
  62 } /* extern "C" */
  63
  64 namespace brw {
  65
  66 class dst_reg;
  67
  68 class vec4_live_variables;
  69
  70 unsigned
  71 swizzle_for_size(int size);
  72
  73 class src_reg : public backend_reg
  74 {
  75 public:
  76    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  77
  78    void init();
  79
  80    src_reg(register_file file, int reg, const glsl_type *type);
  81    src_reg();
  82    src_reg(float f);
  83    src_reg(uint32_t u);
  84    src_reg(int32_t i);
  85    src_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  86    src_reg(struct brw_reg reg);
  87
  88    bool equals(const src_reg &r) const;
  89
  90    src_reg(class vec4_visitor *v, const struct glsl_type *type);
  91    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
  92
  93    explicit src_reg(dst_reg reg);
  94
  95    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
  96
  97    src_reg *reladdr;
  98 };
  99
 100 static inline src_reg
 101 retype(src_reg reg, enum brw_reg_type type)
 102 {
 103    reg.fixed_hw_reg.type = reg.type = type;
 104    return reg;
 105 }
 106
 107 static inline src_reg
 108 offset(src_reg reg, unsigned delta)
 109 {
 110    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 111    reg.reg_offset += delta;
 112    return reg;
 113 }
 114
 115 /**
 116  * Reswizzle a given source register.
 117  * \sa brw_swizzle().
 118  */
 119 static inline src_reg
 120 swizzle(src_reg reg, unsigned swizzle)
 121 {
 122    assert(reg.file != HW_REG);
 123    reg.swizzle = BRW_SWIZZLE4(
 124       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
 125       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
 126       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
 127       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
 128    return reg;
 129 }
 130
 131 static inline src_reg
 132 negate(src_reg reg)
 133 {
 134    assert(reg.file != HW_REG && reg.file != IMM);
 135    reg.negate = !reg.negate;
 136    return reg;
 137 }
 138
 139 class dst_reg : public backend_reg
 140 {
 141 public:
 142    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 143
 144    void init();
 145
 146    dst_reg();
 147    dst_reg(register_file file, int reg);
 148    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 149    dst_reg(struct brw_reg reg);
 150    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 151
 152    explicit dst_reg(src_reg reg);
 153
 154    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 155
 156    src_reg *reladdr;
 157 };
 158
 159 static inline dst_reg
 160 retype(dst_reg reg, enum brw_reg_type type)
 161 {
 162    reg.fixed_hw_reg.type = reg.type = type;
 163    return reg;
 164 }
 165
 166 static inline dst_reg
 167 offset(dst_reg reg, unsigned delta)
 168 {
 169    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 170    reg.reg_offset += delta;
 171    return reg;
 172 }
 173
 174 static inline dst_reg
 175 writemask(dst_reg reg, unsigned mask)
 176 {
 177    assert(reg.file != HW_REG && reg.file != IMM);
 178    assert((reg.writemask & mask) != 0);
 179    reg.writemask &= mask;
 180    return reg;
 181 }
 182
 183 class vec4_instruction : public backend_instruction {
 184 public:
 185    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 186
 187    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 188                     const dst_reg &dst = dst_reg(),
 189                     const src_reg &src0 = src_reg(),
 190                     const src_reg &src1 = src_reg(),
 191                     const src_reg &src2 = src_reg());
 192
 193    struct brw_reg get_dst(void);
 194    struct brw_reg get_src(const struct brw_vue_prog_data *prog_data, int i);
 195
 196    dst_reg dst;
 197    src_reg src[3];
 198
 199    enum brw_urb_write_flags urb_write_flags;
 200
 201    unsigned sol_binding; /**< gen6: SOL binding table index */
 202    bool sol_final_write; /**< gen6: send commit message */
 203    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 204
 205    bool is_send_from_grf();
 206    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
 207    void reswizzle(int dst_writemask, int swizzle);
 208    bool can_do_source_mods(struct brw_context *brw);
 209
 210    bool reads_flag()
 211    {
 212       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 213    }
 214
 215    bool writes_flag()
 216    {
 217       return (conditional_mod && (opcode != BRW_OPCODE_SEL &&
 218                                   opcode != BRW_OPCODE_IF &&
 219                                   opcode != BRW_OPCODE_WHILE));
 220    }
 221 };
 222
 223 /**
 224  * The vertex shader front-end.
 225  *
 226  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 227  * fixed-function) into VS IR.
 228  */
 229 class vec4_visitor : public backend_visitor
 230 {
 231 public:
 232    vec4_visitor(struct brw_context *brw,
 233                 struct brw_vec4_compile *c,
 234                 struct gl_program *prog,
 235                 const struct brw_vue_prog_key *key,
 236                 struct brw_vue_prog_data *prog_data,
 237                 struct gl_shader_program *shader_prog,
 238                 gl_shader_stage stage,
 239                 void *mem_ctx,
 240                 bool debug_flag,
 241                 bool no_spills,
 242                 shader_time_shader_type st_base,
 243                 shader_time_shader_type st_written,
 244                 shader_time_shader_type st_reset);
 245    ~vec4_visitor();
 246
 247    dst_reg dst_null_f()
 248    {
 249       return dst_reg(brw_null_reg());
 250    }
 251
 252    dst_reg dst_null_d()
 253    {
 254       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 255    }
 256
 257    dst_reg dst_null_ud()
 258    {
 259       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 260    }
 261
 262    struct brw_vec4_compile * const c;
 263    const struct brw_vue_prog_key * const key;
 264    struct brw_vue_prog_data * const prog_data;
 265    unsigned int sanity_param_count;
 266
 267    char *fail_msg;
 268    bool failed;
 269
 270    /**
 271     * GLSL IR currently being processed, which is associated with our
 272     * driver IR instructions for debugging purposes.
 273     */
 274    const void *base_ir;
 275    const char *current_annotation;
 276
 277    int *virtual_grf_sizes;
 278    int virtual_grf_count;
 279    int virtual_grf_array_size;
 280    int first_non_payload_grf;
 281    unsigned int max_grf;
 282    int *virtual_grf_start;
 283    int *virtual_grf_end;
 284    brw::vec4_live_variables *live_intervals;
 285    dst_reg userplane[MAX_CLIP_PLANES];
 286
 287    /**
 288     * This is the size to be used for an array with an element per
 289     * reg_offset
 290     */
 291    int virtual_grf_reg_count;
 292    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 293    int *virtual_grf_reg_map;
 294
 295    dst_reg *variable_storage(ir_variable *var);
 296
 297    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 298
 299    bool need_all_constants_in_pull_buffer;
 300
 301    /**
 302     * \name Visit methods
 303     *
 304     * As typical for the visitor pattern, there must be one \c visit method for
 305     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 306     * the hierarchy should not have \c visit methods.
 307     */
 308    /*@{*/
 309    virtual void visit(ir_variable *);
 310    virtual void visit(ir_loop *);
 311    virtual void visit(ir_loop_jump *);
 312    virtual void visit(ir_function_signature *);
 313    virtual void visit(ir_function *);
 314    virtual void visit(ir_expression *);
 315    virtual void visit(ir_swizzle *);
 316    virtual void visit(ir_dereference_variable  *);
 317    virtual void visit(ir_dereference_array *);
 318    virtual void visit(ir_dereference_record *);
 319    virtual void visit(ir_assignment *);
 320    virtual void visit(ir_constant *);
 321    virtual void visit(ir_call *);
 322    virtual void visit(ir_return *);
 323    virtual void visit(ir_discard *);
 324    virtual void visit(ir_texture *);
 325    virtual void visit(ir_if *);
 326    virtual void visit(ir_emit_vertex *);
 327    virtual void visit(ir_end_primitive *);
 328    /*@}*/
 329
 330    src_reg result;
 331
 332    /* Regs for vertex results.  Generated at ir_variable visiting time
 333     * for the ir->location's used.
 334     */
 335    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 336    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 337    int *uniform_size;
 338    int *uniform_vector_size;
 339    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 340    int uniforms;
 341
 342    src_reg shader_start_time;
 343
 344    struct hash_table *variable_ht;
 345
 346    bool run(void);
 347    void fail(const char *msg, ...);
 348
 349    int virtual_grf_alloc(int size);
 350    void setup_uniform_clipplane_values();
 351    void setup_uniform_values(ir_variable *ir);
 352    void setup_builtin_uniform_values(ir_variable *ir);
 353    int setup_uniforms(int payload_reg);
 354    bool reg_allocate_trivial();
 355    bool reg_allocate();
 356    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 357    int choose_spill_reg(struct ra_graph *g);
 358    void spill_reg(int spill_reg);
 359    void move_grf_array_access_to_scratch();
 360    void move_uniform_array_access_to_pull_constants();
 361    void move_push_constants_to_pull_constants();
 362    void split_uniform_registers();
 363    void pack_uniform_registers();
 364    void calculate_live_intervals();
 365    void invalidate_live_intervals();
 366    void split_virtual_grfs();
 367    bool opt_reduce_swizzle();
 368    bool dead_code_eliminate();
 369    bool virtual_grf_interferes(int a, int b);
 370    bool opt_copy_propagation();
 371    bool opt_cse_local(bblock_t *block);
 372    bool opt_cse();
 373    bool opt_algebraic();
 374    bool opt_register_coalesce();
 375    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 376    void opt_set_dependency_control();
 377    void opt_schedule_instructions();
 378
 379    vec4_instruction *emit(vec4_instruction *inst);
 380
 381    vec4_instruction *emit(enum opcode opcode);
 382    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 383    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 384                           const src_reg &src0);
 385    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 386                           const src_reg &src0, const src_reg &src1);
 387    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 388                           const src_reg &src0, const src_reg &src1,
 389                           const src_reg &src2);
 390
 391    vec4_instruction *emit_before(bblock_t *block,
 392                                  vec4_instruction *inst,
 393                                  vec4_instruction *new_inst);
 394
 395 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 396 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 397 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 398    EMIT1(MOV)
 399    EMIT1(NOT)
 400    EMIT1(RNDD)
 401    EMIT1(RNDE)
 402    EMIT1(RNDZ)
 403    EMIT1(FRC)
 404    EMIT1(F32TO16)
 405    EMIT1(F16TO32)
 406    EMIT2(ADD)
 407    EMIT2(MUL)
 408    EMIT2(MACH)
 409    EMIT2(MAC)
 410    EMIT2(AND)
 411    EMIT2(OR)
 412    EMIT2(XOR)
 413    EMIT2(DP3)
 414    EMIT2(DP4)
 415    EMIT2(DPH)
 416    EMIT2(SHL)
 417    EMIT2(SHR)
 418    EMIT2(ASR)
 419    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 420                          enum brw_conditional_mod condition);
 421    vec4_instruction *IF(src_reg src0, src_reg src1,
 422                         enum brw_conditional_mod condition);
 423    vec4_instruction *IF(enum brw_predicate predicate);
 424    EMIT1(PULL_CONSTANT_LOAD)
 425    EMIT1(SCRATCH_READ)
 426    EMIT2(SCRATCH_WRITE)
 427    EMIT3(LRP)
 428    EMIT1(BFREV)
 429    EMIT3(BFE)
 430    EMIT2(BFI1)
 431    EMIT3(BFI2)
 432    EMIT1(FBH)
 433    EMIT1(FBL)
 434    EMIT1(CBIT)
 435    EMIT3(MAD)
 436    EMIT2(ADDC)
 437    EMIT2(SUBB)
 438 #undef EMIT1
 439 #undef EMIT2
 440 #undef EMIT3
 441
 442    int implied_mrf_writes(vec4_instruction *inst);
 443
 444    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 445                                dst_reg dst,
 446                                src_reg src,
 447                                vec4_instruction *pre_rhs_inst,
 448                                vec4_instruction *last_rhs_inst);
 449
 450    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 451    void visit_instructions(const exec_list *list);
 452
 453    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 454                     src_reg src0, src_reg src1, src_reg one);
 455
 456    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 457    void emit_if_gen6(ir_if *ir);
 458
 459    void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 460                     src_reg src0, src_reg src1);
 461
 462    void emit_lrp(const dst_reg &dst,
 463                  const src_reg &x, const src_reg &y, const src_reg &a);
 464
 465    void emit_block_move(dst_reg *dst, src_reg *src,
 466                         const struct glsl_type *type, brw_predicate predicate);
 467
 468    void emit_constant_values(dst_reg *dst, ir_constant *value);
 469
 470    /**
 471     * Emit the correct dot-product instruction for the type of arguments
 472     */
 473    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 474
 475    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 476                     dst_reg dst, src_reg src0);
 477
 478    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 479                     dst_reg dst, src_reg src0, src_reg src1);
 480
 481    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 482                  dst_reg dst, const src_reg &src);
 483
 484    src_reg fix_3src_operand(src_reg src);
 485
 486    void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 487                   const src_reg &src1 = src_reg());
 488    src_reg fix_math_operand(src_reg src);
 489
 490    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 491    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 492    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 493    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 494    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 495    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 496
 497    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 498    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
 499    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 500    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 501
 502    void emit_ndc_computation();
 503    void emit_psiz_and_flags(dst_reg reg);
 504    void emit_clip_distances(dst_reg reg, int offset);
 505    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
 506    void emit_urb_slot(dst_reg reg, int varying);
 507
 508    void emit_shader_time_begin();
 509    void emit_shader_time_end();
 510    void emit_shader_time_write(enum shader_time_shader_type type,
 511                                src_reg value);
 512
 513    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 514                             dst_reg dst, src_reg offset, src_reg src0,
 515                             src_reg src1);
 516
 517    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 518                                   src_reg offset);
 519
 520    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 521                               src_reg *reladdr, int reg_offset);
 522    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 523                                     src_reg *reladdr, int reg_offset);
 524    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 525                           dst_reg dst,
 526                           src_reg orig_src,
 527                           int base_offset);
 528    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 529                            int base_offset);
 530    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 531                                 dst_reg dst,
 532                                 src_reg orig_src,
 533                                 int base_offset);
 534
 535    bool try_emit_mad(ir_expression *ir);
 536    bool try_emit_b2f_of_compare(ir_expression *ir);
 537    void resolve_ud_negate(src_reg *reg);
 538    void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
 539
 540    src_reg get_timestamp();
 541
 542    bool process_move_condition(ir_rvalue *ir);
 543
 544    void dump_instruction(backend_instruction *inst);
 545    void dump_instruction(backend_instruction *inst, FILE *file);
 546
 547    void visit_atomic_counter_intrinsic(ir_call *ir);
 548
 549 protected:
 550    void emit_vertex();
 551    void lower_attributes_to_hw_regs(const int *attribute_map,
 552                                     bool interleaved);
 553    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 554                                    int reg_node_count);
 555    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 556    virtual void assign_binding_table_offsets();
 557    virtual void setup_payload() = 0;
 558    virtual void emit_prolog() = 0;
 559    virtual void emit_program_code() = 0;
 560    virtual void emit_thread_end() = 0;
 561    virtual void emit_urb_write_header(int mrf) = 0;
 562    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 563    virtual int compute_array_stride(ir_dereference_array *ir);
 564
 565    const bool debug_flag;
 566
 567 private:
 568    /**
 569     * If true, then register allocation should fail instead of spilling.
 570     */
 571    const bool no_spills;
 572
 573    const shader_time_shader_type st_base;
 574    const shader_time_shader_type st_written;
 575    const shader_time_shader_type st_reset;
 576 };
 577
 578
 579 /**
 580  * The vertex shader code generator.
 581  *
 582  * Translates VS IR to actual i965 assembly code.
 583  */
 584 class vec4_generator
 585 {
 586 public:
 587    vec4_generator(struct brw_context *brw,
 588                   struct gl_shader_program *shader_prog,
 589                   struct gl_program *prog,
 590                   struct brw_vue_prog_data *prog_data,
 591                   void *mem_ctx,
 592                   bool debug_flag);
 593    ~vec4_generator();
 594
 595    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 596
 597 private:
 598    void generate_code(const cfg_t *cfg);
 599
 600    void generate_math1_gen4(vec4_instruction *inst,
 601                             struct brw_reg dst,
 602                             struct brw_reg src);
 603    void generate_math2_gen4(vec4_instruction *inst,
 604                             struct brw_reg dst,
 605                             struct brw_reg src0,
 606                             struct brw_reg src1);
 607    void generate_math_gen6(vec4_instruction *inst,
 608                            struct brw_reg dst,
 609                            struct brw_reg src0,
 610                            struct brw_reg src1);
 611
 612    void generate_tex(vec4_instruction *inst,
 613                      struct brw_reg dst,
 614                      struct brw_reg src,
 615                      struct brw_reg sampler_index);
 616
 617    void generate_vs_urb_write(vec4_instruction *inst);
 618    void generate_gs_urb_write(vec4_instruction *inst);
 619    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 620    void generate_gs_thread_end(vec4_instruction *inst);
 621    void generate_gs_set_write_offset(struct brw_reg dst,
 622                                      struct brw_reg src0,
 623                                      struct brw_reg src1);
 624    void generate_gs_set_vertex_count(struct brw_reg dst,
 625                                      struct brw_reg src);
 626    void generate_gs_svb_write(vec4_instruction *inst,
 627                               struct brw_reg dst,
 628                               struct brw_reg src0,
 629                               struct brw_reg src1);
 630    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 631                                               struct brw_reg dst,
 632                                               struct brw_reg src);
 633    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 634    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 635    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 636    void generate_gs_get_instance_id(struct brw_reg dst);
 637    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 638                                            struct brw_reg src0,
 639                                            struct brw_reg src1,
 640                                            struct brw_reg src2);
 641    void generate_gs_ff_sync(vec4_instruction *inst,
 642                             struct brw_reg dst,
 643                             struct brw_reg src0,
 644                             struct brw_reg src1);
 645    void generate_gs_set_primitive_id(struct brw_reg dst);
 646    void generate_oword_dual_block_offsets(struct brw_reg m1,
 647                                           struct brw_reg index);
 648    void generate_scratch_write(vec4_instruction *inst,
 649                                struct brw_reg dst,
 650                                struct brw_reg src,
 651                                struct brw_reg index);
 652    void generate_scratch_read(vec4_instruction *inst,
 653                               struct brw_reg dst,
 654                               struct brw_reg index);
 655    void generate_pull_constant_load(vec4_instruction *inst,
 656                                     struct brw_reg dst,
 657                                     struct brw_reg index,
 658                                     struct brw_reg offset);
 659    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 660                                          struct brw_reg dst,
 661                                          struct brw_reg surf_index,
 662                                          struct brw_reg offset);
 663    void generate_unpack_flags(vec4_instruction *inst,
 664                               struct brw_reg dst);
 665
 666    void generate_untyped_atomic(vec4_instruction *inst,
 667                                 struct brw_reg dst,
 668                                 struct brw_reg atomic_op,
 669                                 struct brw_reg surf_index);
 670
 671    void generate_untyped_surface_read(vec4_instruction *inst,
 672                                       struct brw_reg dst,
 673                                       struct brw_reg surf_index);
 674
 675    struct brw_context *brw;
 676
 677    struct brw_compile *p;
 678
 679    struct gl_shader_program *shader_prog;
 680    const struct gl_program *prog;
 681
 682    struct brw_vue_prog_data *prog_data;
 683
 684    void *mem_ctx;
 685    const bool debug_flag;
 686 };
 687
 688 } /* namespace brw */
 689 #endif /* __cplusplus */
 690
 691 #endif /* BRW_VEC4_H */