src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39
  40 #ifdef __cplusplus
  41 }; /* extern "C" */
  42 #endif
  43
  44 #include "glsl/ir.h"
  45
  46 struct brw_vs_compile;
  47
  48
  49 struct brw_vec4_compile {
  50    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  51 };
  52
  53
  54 struct brw_vec4_prog_key {
  55    GLuint program_string_id;
  56
  57    /**
  58     * True if at least one clip flag is enabled, regardless of whether the
  59     * shader uses clip planes or gl_ClipDistance.
  60     */
  61    GLuint userclip_active:1;
  62
  63    /**
  64     * How many user clipping planes are being uploaded to the vertex shader as
  65     * push constants.
  66     */
  67    GLuint nr_userclip_plane_consts:4;
  68
  69    /**
  70     * True if the shader uses gl_ClipDistance, regardless of whether any clip
  71     * flags are enabled.
  72     */
  73    GLuint uses_clip_distance:1;
  74
  75    GLuint clamp_vertex_color:1;
  76
  77    struct brw_sampler_prog_key_data tex;
  78 };
  79
  80
  81 #ifdef __cplusplus
  82 extern "C" {
  83 #endif
  84
  85 bool brw_vec4_prog_data_compare(const struct brw_vec4_prog_data *a,
  86                                 const struct brw_vec4_prog_data *b);
  87 void brw_vec4_prog_data_free(const struct brw_vec4_prog_data *prog_data);
  88
  89 #ifdef __cplusplus
  90 } /* extern "C" */
  91
  92 namespace brw {
  93
  94 class dst_reg;
  95
  96 unsigned
  97 swizzle_for_size(int size);
  98
  99 class reg
 100 {
 101 public:
 102    /** Register file: ARF, GRF, MRF, IMM. */
 103    enum register_file file;
 104    /** virtual register number.  0 = fixed hw reg */
 105    int reg;
 106    /** Offset within the virtual register. */
 107    int reg_offset;
 108    /** Register type.  BRW_REGISTER_TYPE_* */
 109    int type;
 110    struct brw_reg fixed_hw_reg;
 111
 112    /** Value for file == BRW_IMMMEDIATE_FILE */
 113    union {
 114       int32_t i;
 115       uint32_t u;
 116       float f;
 117    } imm;
 118 };
 119
 120 class src_reg : public reg
 121 {
 122 public:
 123    /* Callers of this ralloc-based new need not call delete. It's
 124     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 125    static void* operator new(size_t size, void *ctx)
 126    {
 127       void *node;
 128
 129       node = ralloc_size(ctx, size);
 130       assert(node != NULL);
 131
 132       return node;
 133    }
 134
 135    void init();
 136
 137    src_reg(register_file file, int reg, const glsl_type *type);
 138    src_reg();
 139    src_reg(float f);
 140    src_reg(uint32_t u);
 141    src_reg(int32_t i);
 142
 143    bool equals(src_reg *r);
 144    bool is_zero() const;
 145    bool is_one() const;
 146
 147    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 148
 149    explicit src_reg(dst_reg reg);
 150
 151    GLuint swizzle; /**< SWIZZLE_XYZW swizzles from Mesa. */
 152    bool negate;
 153    bool abs;
 154
 155    src_reg *reladdr;
 156 };
 157
 158 class dst_reg : public reg
 159 {
 160 public:
 161    /* Callers of this ralloc-based new need not call delete. It's
 162     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 163    static void* operator new(size_t size, void *ctx)
 164    {
 165       void *node;
 166
 167       node = ralloc_size(ctx, size);
 168       assert(node != NULL);
 169
 170       return node;
 171    }
 172
 173    void init();
 174
 175    dst_reg();
 176    dst_reg(register_file file, int reg);
 177    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 178    dst_reg(struct brw_reg reg);
 179    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 180
 181    explicit dst_reg(src_reg reg);
 182
 183    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 184
 185    src_reg *reladdr;
 186 };
 187
 188 class vec4_instruction : public backend_instruction {
 189 public:
 190    /* Callers of this ralloc-based new need not call delete. It's
 191     * easier to just ralloc_free 'ctx' (or any of its ancestors). */
 192    static void* operator new(size_t size, void *ctx)
 193    {
 194       void *node;
 195
 196       node = rzalloc_size(ctx, size);
 197       assert(node != NULL);
 198
 199       return node;
 200    }
 201
 202    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 203                     dst_reg dst = dst_reg(),
 204                     src_reg src0 = src_reg(),
 205                     src_reg src1 = src_reg(),
 206                     src_reg src2 = src_reg());
 207
 208    struct brw_reg get_dst(void);
 209    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 210
 211    dst_reg dst;
 212    src_reg src[3];
 213
 214    bool saturate;
 215    bool force_writemask_all;
 216    bool no_dd_clear, no_dd_check;
 217
 218    int conditional_mod; /**< BRW_CONDITIONAL_* */
 219
 220    int sampler;
 221    uint32_t texture_offset; /**< Texture Offset bitfield */
 222    int target; /**< MRT target. */
 223    bool shadow_compare;
 224
 225    enum brw_urb_write_flags urb_write_flags;
 226    bool header_present;
 227    int mlen; /**< SEND message length */
 228    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 229
 230    uint32_t offset; /* spill/unspill offset */
 231    /** @{
 232     * Annotation for the generated IR.  One of the two can be set.
 233     */
 234    const void *ir;
 235    const char *annotation;
 236
 237    bool is_send_from_grf();
 238    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 239    void reswizzle_dst(int dst_writemask, int swizzle);
 240
 241    bool depends_on_flags()
 242    {
 243       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 244    }
 245 };
 246
 247 /**
 248  * The vertex shader front-end.
 249  *
 250  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 251  * fixed-function) into VS IR.
 252  */
 253 class vec4_visitor : public backend_visitor
 254 {
 255 public:
 256    vec4_visitor(struct brw_context *brw,
 257                 struct brw_vec4_compile *c,
 258                 struct gl_program *prog,
 259                 const struct brw_vec4_prog_key *key,
 260                 struct brw_vec4_prog_data *prog_data,
 261                 struct gl_shader_program *shader_prog,
 262                 struct brw_shader *shader,
 263                 void *mem_ctx,
 264                 bool debug_flag);
 265    ~vec4_visitor();
 266
 267    dst_reg dst_null_f()
 268    {
 269       return dst_reg(brw_null_reg());
 270    }
 271
 272    dst_reg dst_null_d()
 273    {
 274       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 275    }
 276
 277    struct gl_program *prog;
 278    struct brw_vec4_compile *c;
 279    const struct brw_vec4_prog_key *key;
 280    struct brw_vec4_prog_data *prog_data;
 281    unsigned int sanity_param_count;
 282
 283    char *fail_msg;
 284    bool failed;
 285
 286    /**
 287     * GLSL IR currently being processed, which is associated with our
 288     * driver IR instructions for debugging purposes.
 289     */
 290    const void *base_ir;
 291    const char *current_annotation;
 292
 293    int *virtual_grf_sizes;
 294    int virtual_grf_count;
 295    int virtual_grf_array_size;
 296    int first_non_payload_grf;
 297    unsigned int max_grf;
 298    int *virtual_grf_start;
 299    int *virtual_grf_end;
 300    dst_reg userplane[MAX_CLIP_PLANES];
 301
 302    /**
 303     * This is the size to be used for an array with an element per
 304     * reg_offset
 305     */
 306    int virtual_grf_reg_count;
 307    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 308    int *virtual_grf_reg_map;
 309
 310    bool live_intervals_valid;
 311
 312    dst_reg *variable_storage(ir_variable *var);
 313
 314    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 315
 316    bool need_all_constants_in_pull_buffer;
 317
 318    /**
 319     * \name Visit methods
 320     *
 321     * As typical for the visitor pattern, there must be one \c visit method for
 322     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 323     * the hierarchy should not have \c visit methods.
 324     */
 325    /*@{*/
 326    virtual void visit(ir_variable *);
 327    virtual void visit(ir_loop *);
 328    virtual void visit(ir_loop_jump *);
 329    virtual void visit(ir_function_signature *);
 330    virtual void visit(ir_function *);
 331    virtual void visit(ir_expression *);
 332    virtual void visit(ir_swizzle *);
 333    virtual void visit(ir_dereference_variable  *);
 334    virtual void visit(ir_dereference_array *);
 335    virtual void visit(ir_dereference_record *);
 336    virtual void visit(ir_assignment *);
 337    virtual void visit(ir_constant *);
 338    virtual void visit(ir_call *);
 339    virtual void visit(ir_return *);
 340    virtual void visit(ir_discard *);
 341    virtual void visit(ir_texture *);
 342    virtual void visit(ir_if *);
 343    virtual void visit(ir_emit_vertex *);
 344    virtual void visit(ir_end_primitive *);
 345    /*@}*/
 346
 347    src_reg result;
 348
 349    /* Regs for vertex results.  Generated at ir_variable visiting time
 350     * for the ir->location's used.
 351     */
 352    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 353    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 354    int uniform_size[MAX_UNIFORMS];
 355    int uniform_vector_size[MAX_UNIFORMS];
 356    int uniforms;
 357
 358    src_reg shader_start_time;
 359
 360    struct hash_table *variable_ht;
 361
 362    bool run(void);
 363    void fail(const char *msg, ...);
 364
 365    int virtual_grf_alloc(int size);
 366    void setup_uniform_clipplane_values();
 367    void setup_uniform_values(ir_variable *ir);
 368    void setup_builtin_uniform_values(ir_variable *ir);
 369    int setup_uniforms(int payload_reg);
 370    bool reg_allocate_trivial();
 371    bool reg_allocate();
 372    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 373    int choose_spill_reg(struct ra_graph *g);
 374    void spill_reg(int spill_reg);
 375    void move_grf_array_access_to_scratch();
 376    void move_uniform_array_access_to_pull_constants();
 377    void move_push_constants_to_pull_constants();
 378    void split_uniform_registers();
 379    void pack_uniform_registers();
 380    void calculate_live_intervals();
 381    void split_virtual_grfs();
 382    bool dead_code_eliminate();
 383    bool virtual_grf_interferes(int a, int b);
 384    bool opt_copy_propagation();
 385    bool opt_algebraic();
 386    bool opt_register_coalesce();
 387    void opt_set_dependency_control();
 388    void opt_schedule_instructions();
 389
 390    bool can_do_source_mods(vec4_instruction *inst);
 391
 392    vec4_instruction *emit(vec4_instruction *inst);
 393
 394    vec4_instruction *emit(enum opcode opcode);
 395
 396    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 397
 398    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 399                           src_reg src0, src_reg src1);
 400
 401    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 402                           src_reg src0, src_reg src1, src_reg src2);
 403
 404    vec4_instruction *emit_before(vec4_instruction *inst,
 405                                  vec4_instruction *new_inst);
 406
 407    vec4_instruction *MOV(dst_reg dst, src_reg src0);
 408    vec4_instruction *NOT(dst_reg dst, src_reg src0);
 409    vec4_instruction *RNDD(dst_reg dst, src_reg src0);
 410    vec4_instruction *RNDE(dst_reg dst, src_reg src0);
 411    vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
 412    vec4_instruction *FRC(dst_reg dst, src_reg src0);
 413    vec4_instruction *F32TO16(dst_reg dst, src_reg src0);
 414    vec4_instruction *F16TO32(dst_reg dst, src_reg src0);
 415    vec4_instruction *ADD(dst_reg dst, src_reg src0, src_reg src1);
 416    vec4_instruction *MUL(dst_reg dst, src_reg src0, src_reg src1);
 417    vec4_instruction *MACH(dst_reg dst, src_reg src0, src_reg src1);
 418    vec4_instruction *MAC(dst_reg dst, src_reg src0, src_reg src1);
 419    vec4_instruction *AND(dst_reg dst, src_reg src0, src_reg src1);
 420    vec4_instruction *OR(dst_reg dst, src_reg src0, src_reg src1);
 421    vec4_instruction *XOR(dst_reg dst, src_reg src0, src_reg src1);
 422    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
 423    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
 424    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
 425    vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
 426    vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
 427    vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
 428    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 429                          uint32_t condition);
 430    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 431    vec4_instruction *IF(uint32_t predicate);
 432    vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
 433    vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
 434    vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
 435    vec4_instruction *LRP(dst_reg dst, src_reg a, src_reg y, src_reg x);
 436    vec4_instruction *BFREV(dst_reg dst, src_reg value);
 437    vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg value);
 438    vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
 439    vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert, src_reg base);
 440    vec4_instruction *FBH(dst_reg dst, src_reg value);
 441    vec4_instruction *FBL(dst_reg dst, src_reg value);
 442    vec4_instruction *CBIT(dst_reg dst, src_reg value);
 443
 444    int implied_mrf_writes(vec4_instruction *inst);
 445
 446    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 447                                dst_reg dst,
 448                                src_reg src,
 449                                vec4_instruction *pre_rhs_inst,
 450                                vec4_instruction *last_rhs_inst);
 451
 452    bool try_copy_propagation(vec4_instruction *inst, int arg,
 453                              src_reg *values[4]);
 454
 455    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 456    void visit_instructions(const exec_list *list);
 457
 458    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 459                     src_reg src0, src_reg src1, src_reg one);
 460
 461    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 462    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 463    void emit_if_gen6(ir_if *ir);
 464
 465    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 466
 467    void emit_block_move(dst_reg *dst, src_reg *src,
 468                         const struct glsl_type *type, uint32_t predicate);
 469
 470    void emit_constant_values(dst_reg *dst, ir_constant *value);
 471
 472    /**
 473     * Emit the correct dot-product instruction for the type of arguments
 474     */
 475    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 476
 477    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 478                     dst_reg dst, src_reg src0);
 479
 480    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 481                     dst_reg dst, src_reg src0, src_reg src1);
 482
 483    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 484                  dst_reg dst, const src_reg &src);
 485
 486    src_reg fix_3src_operand(src_reg src);
 487
 488    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 489    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 490    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 491    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 492    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 493    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 494    src_reg fix_math_operand(src_reg src);
 495
 496    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 497    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 498
 499    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 500
 501    void emit_ndc_computation();
 502    void emit_psiz_and_flags(struct brw_reg reg);
 503    void emit_clip_distances(dst_reg reg, int offset);
 504    void emit_generic_urb_slot(dst_reg reg, int varying);
 505    void emit_urb_slot(int mrf, int varying);
 506
 507    void emit_shader_time_begin();
 508    void emit_shader_time_end();
 509    void emit_shader_time_write(enum shader_time_shader_type type,
 510                                src_reg value);
 511
 512    src_reg get_scratch_offset(vec4_instruction *inst,
 513                               src_reg *reladdr, int reg_offset);
 514    src_reg get_pull_constant_offset(vec4_instruction *inst,
 515                                     src_reg *reladdr, int reg_offset);
 516    void emit_scratch_read(vec4_instruction *inst,
 517                           dst_reg dst,
 518                           src_reg orig_src,
 519                           int base_offset);
 520    void emit_scratch_write(vec4_instruction *inst,
 521                            int base_offset);
 522    void emit_pull_constant_load(vec4_instruction *inst,
 523                                 dst_reg dst,
 524                                 src_reg orig_src,
 525                                 int base_offset);
 526
 527    bool try_emit_sat(ir_expression *ir);
 528    bool try_emit_mad(ir_expression *ir, int mul_arg);
 529    void resolve_ud_negate(src_reg *reg);
 530
 531    src_reg get_timestamp();
 532
 533    bool process_move_condition(ir_rvalue *ir);
 534
 535    void dump_instruction(backend_instruction *inst);
 536
 537 protected:
 538    void emit_vertex();
 539    void lower_attributes_to_hw_regs(const int *attribute_map);
 540    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 541    virtual void setup_payload() = 0;
 542    virtual void emit_prolog() = 0;
 543    virtual void emit_program_code() = 0;
 544    virtual void emit_thread_end() = 0;
 545    virtual void emit_urb_write_header(int mrf) = 0;
 546    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 547    virtual int compute_array_stride(ir_dereference_array *ir);
 548
 549    const bool debug_flag;
 550 };
 551
 552 class vec4_vs_visitor : public vec4_visitor
 553 {
 554 public:
 555    vec4_vs_visitor(struct brw_context *brw,
 556                    struct brw_vs_compile *vs_compile,
 557                    struct brw_vs_prog_data *vs_prog_data,
 558                    struct gl_shader_program *prog,
 559                    struct brw_shader *shader,
 560                    void *mem_ctx);
 561
 562 protected:
 563    virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
 564    virtual void setup_payload();
 565    virtual void emit_prolog();
 566    virtual void emit_program_code();
 567    virtual void emit_thread_end();
 568    virtual void emit_urb_write_header(int mrf);
 569    virtual vec4_instruction *emit_urb_write_opcode(bool complete);
 570
 571 private:
 572    int setup_attributes(int payload_reg);
 573    void setup_vp_regs();
 574    dst_reg get_vp_dst_reg(const prog_dst_register &dst);
 575    src_reg get_vp_src_reg(const prog_src_register &src);
 576
 577    struct brw_vs_compile * const vs_compile;
 578    struct brw_vs_prog_data * const vs_prog_data;
 579    src_reg *vp_temp_regs;
 580    src_reg vp_addr_reg;
 581 };
 582
 583 /**
 584  * The vertex shader code generator.
 585  *
 586  * Translates VS IR to actual i965 assembly code.
 587  */
 588 class vec4_generator
 589 {
 590 public:
 591    vec4_generator(struct brw_context *brw,
 592                   struct gl_shader_program *shader_prog,
 593                   struct gl_program *prog,
 594                   struct brw_vec4_prog_data *prog_data,
 595                   void *mem_ctx,
 596                   bool debug_flag);
 597    ~vec4_generator();
 598
 599    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 600
 601 private:
 602    void generate_code(exec_list *instructions);
 603    void generate_vec4_instruction(vec4_instruction *inst,
 604                                   struct brw_reg dst,
 605                                   struct brw_reg *src);
 606
 607    void generate_math1_gen4(vec4_instruction *inst,
 608                             struct brw_reg dst,
 609                             struct brw_reg src);
 610    void generate_math1_gen6(vec4_instruction *inst,
 611                             struct brw_reg dst,
 612                             struct brw_reg src);
 613    void generate_math2_gen4(vec4_instruction *inst,
 614                             struct brw_reg dst,
 615                             struct brw_reg src0,
 616                             struct brw_reg src1);
 617    void generate_math2_gen6(vec4_instruction *inst,
 618                             struct brw_reg dst,
 619                             struct brw_reg src0,
 620                             struct brw_reg src1);
 621    void generate_math2_gen7(vec4_instruction *inst,
 622                             struct brw_reg dst,
 623                             struct brw_reg src0,
 624                             struct brw_reg src1);
 625
 626    void generate_tex(vec4_instruction *inst,
 627                      struct brw_reg dst,
 628                      struct brw_reg src);
 629
 630    void generate_vs_urb_write(vec4_instruction *inst);
 631    void generate_gs_urb_write(vec4_instruction *inst);
 632    void generate_gs_thread_end(vec4_instruction *inst);
 633    void generate_gs_set_write_offset(struct brw_reg dst,
 634                                      struct brw_reg src0,
 635                                      struct brw_reg src1);
 636    void generate_gs_set_vertex_count(struct brw_reg dst,
 637                                      struct brw_reg src);
 638    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 639    void generate_oword_dual_block_offsets(struct brw_reg m1,
 640                                           struct brw_reg index);
 641    void generate_scratch_write(vec4_instruction *inst,
 642                                struct brw_reg dst,
 643                                struct brw_reg src,
 644                                struct brw_reg index);
 645    void generate_scratch_read(vec4_instruction *inst,
 646                               struct brw_reg dst,
 647                               struct brw_reg index);
 648    void generate_pull_constant_load(vec4_instruction *inst,
 649                                     struct brw_reg dst,
 650                                     struct brw_reg index,
 651                                     struct brw_reg offset);
 652    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 653                                          struct brw_reg dst,
 654                                          struct brw_reg surf_index,
 655                                          struct brw_reg offset);
 656    void generate_unpack_flags(vec4_instruction *inst,
 657                               struct brw_reg dst);
 658
 659    void mark_surface_used(unsigned surf_index);
 660
 661    struct brw_context *brw;
 662
 663    struct brw_compile *p;
 664
 665    struct gl_shader_program *shader_prog;
 666    struct gl_shader *shader;
 667    const struct gl_program *prog;
 668
 669    struct brw_vec4_prog_data *prog_data;
 670
 671    void *mem_ctx;
 672    const bool debug_flag;
 673 };
 674
 675 } /* namespace brw */
 676 #endif /* __cplusplus */
 677
 678 #endif /* BRW_VEC4_H */