2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "brw_shader.h"
29 #include "main/compiler.h"
30 #include "program/hash_table.h"
31 #include "brw_program.h"
37 #include "brw_context.h"
39 #include "intel_asm_annotation.h"
48 struct brw_vec4_compile
{
49 GLuint last_scratch
; /**< measured in 32-byte (register size) units */
53 struct brw_vec4_prog_key
{
54 GLuint program_string_id
;
57 * True if at least one clip flag is enabled, regardless of whether the
58 * shader uses clip planes or gl_ClipDistance.
60 GLuint userclip_active
:1;
63 * How many user clipping planes are being uploaded to the vertex shader as
66 GLuint nr_userclip_plane_consts
:4;
68 GLuint clamp_vertex_color
:1;
70 struct brw_sampler_prog_key_data tex
;
79 brw_vec4_setup_prog_key_for_precompile(struct gl_context
*ctx
,
80 struct brw_vec4_prog_key
*key
,
81 GLuint id
, struct gl_program
*prog
);
91 swizzle_for_size(int size
);
93 class src_reg
: public backend_reg
96 DECLARE_RALLOC_CXX_OPERATORS(src_reg
)
100 src_reg(register_file file
, int reg
, const glsl_type
*type
);
105 src_reg(struct brw_reg reg
);
107 bool equals(const src_reg
&r
) const;
109 src_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
111 explicit src_reg(dst_reg reg
);
113 GLuint swizzle
; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
118 static inline src_reg
119 retype(src_reg reg
, enum brw_reg_type type
)
121 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
125 static inline src_reg
126 offset(src_reg reg
, unsigned delta
)
128 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
129 reg
.reg_offset
+= delta
;
134 * Reswizzle a given source register.
137 static inline src_reg
138 swizzle(src_reg reg
, unsigned swizzle
)
140 assert(reg
.file
!= HW_REG
);
141 reg
.swizzle
= BRW_SWIZZLE4(
142 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 0)),
143 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 1)),
144 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 2)),
145 BRW_GET_SWZ(reg
.swizzle
, BRW_GET_SWZ(swizzle
, 3)));
149 static inline src_reg
152 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
153 reg
.negate
= !reg
.negate
;
157 class dst_reg
: public backend_reg
160 DECLARE_RALLOC_CXX_OPERATORS(dst_reg
)
165 dst_reg(register_file file
, int reg
);
166 dst_reg(register_file file
, int reg
, const glsl_type
*type
, int writemask
);
167 dst_reg(struct brw_reg reg
);
168 dst_reg(class vec4_visitor
*v
, const struct glsl_type
*type
);
170 explicit dst_reg(src_reg reg
);
172 int writemask
; /**< Bitfield of WRITEMASK_[XYZW] */
177 static inline dst_reg
178 retype(dst_reg reg
, enum brw_reg_type type
)
180 reg
.fixed_hw_reg
.type
= reg
.type
= type
;
184 static inline dst_reg
185 offset(dst_reg reg
, unsigned delta
)
187 assert(delta
== 0 || (reg
.file
!= HW_REG
&& reg
.file
!= IMM
));
188 reg
.reg_offset
+= delta
;
192 static inline dst_reg
193 writemask(dst_reg reg
, unsigned mask
)
195 assert(reg
.file
!= HW_REG
&& reg
.file
!= IMM
);
196 assert((reg
.writemask
& mask
) != 0);
197 reg
.writemask
&= mask
;
201 class vec4_instruction
: public backend_instruction
{
203 DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction
)
205 vec4_instruction(vec4_visitor
*v
, enum opcode opcode
,
206 const dst_reg
&dst
= dst_reg(),
207 const src_reg
&src0
= src_reg(),
208 const src_reg
&src1
= src_reg(),
209 const src_reg
&src2
= src_reg());
211 struct brw_reg
get_dst(void);
212 struct brw_reg
get_src(const struct brw_vec4_prog_data
*prog_data
, int i
);
219 enum brw_urb_write_flags urb_write_flags
;
222 bool is_send_from_grf();
223 bool can_reswizzle(int dst_writemask
, int swizzle
, int swizzle_mask
);
224 void reswizzle(int dst_writemask
, int swizzle
);
225 bool can_do_source_mods(struct brw_context
*brw
);
229 return predicate
|| opcode
== VS_OPCODE_UNPACK_FLAGS_SIMD4X2
;
234 return conditional_mod
&& opcode
!= BRW_OPCODE_SEL
;
239 * The vertex shader front-end.
241 * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
242 * fixed-function) into VS IR.
244 class vec4_visitor
: public backend_visitor
247 vec4_visitor(struct brw_context
*brw
,
248 struct brw_vec4_compile
*c
,
249 struct gl_program
*prog
,
250 const struct brw_vec4_prog_key
*key
,
251 struct brw_vec4_prog_data
*prog_data
,
252 struct gl_shader_program
*shader_prog
,
253 gl_shader_stage stage
,
257 shader_time_shader_type st_base
,
258 shader_time_shader_type st_written
,
259 shader_time_shader_type st_reset
);
264 return dst_reg(brw_null_reg());
269 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D
));
272 dst_reg
dst_null_ud()
274 return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
277 struct brw_vec4_compile
* const c
;
278 const struct brw_vec4_prog_key
* const key
;
279 struct brw_vec4_prog_data
* const prog_data
;
280 unsigned int sanity_param_count
;
286 * GLSL IR currently being processed, which is associated with our
287 * driver IR instructions for debugging purposes.
290 const char *current_annotation
;
292 int *virtual_grf_sizes
;
293 int virtual_grf_count
;
294 int virtual_grf_array_size
;
295 int first_non_payload_grf
;
296 unsigned int max_grf
;
297 int *virtual_grf_start
;
298 int *virtual_grf_end
;
299 dst_reg userplane
[MAX_CLIP_PLANES
];
302 * This is the size to be used for an array with an element per
305 int virtual_grf_reg_count
;
306 /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
307 int *virtual_grf_reg_map
;
309 bool live_intervals_valid
;
311 dst_reg
*variable_storage(ir_variable
*var
);
313 void reladdr_to_temp(ir_instruction
*ir
, src_reg
*reg
, int *num_reladdr
);
315 bool need_all_constants_in_pull_buffer
;
318 * \name Visit methods
320 * As typical for the visitor pattern, there must be one \c visit method for
321 * each concrete subclass of \c ir_instruction. Virtual base classes within
322 * the hierarchy should not have \c visit methods.
325 virtual void visit(ir_variable
*);
326 virtual void visit(ir_loop
*);
327 virtual void visit(ir_loop_jump
*);
328 virtual void visit(ir_function_signature
*);
329 virtual void visit(ir_function
*);
330 virtual void visit(ir_expression
*);
331 virtual void visit(ir_swizzle
*);
332 virtual void visit(ir_dereference_variable
*);
333 virtual void visit(ir_dereference_array
*);
334 virtual void visit(ir_dereference_record
*);
335 virtual void visit(ir_assignment
*);
336 virtual void visit(ir_constant
*);
337 virtual void visit(ir_call
*);
338 virtual void visit(ir_return
*);
339 virtual void visit(ir_discard
*);
340 virtual void visit(ir_texture
*);
341 virtual void visit(ir_if
*);
342 virtual void visit(ir_emit_vertex
*);
343 virtual void visit(ir_end_primitive
*);
348 /* Regs for vertex results. Generated at ir_variable visiting time
349 * for the ir->location's used.
351 dst_reg output_reg
[BRW_VARYING_SLOT_COUNT
];
352 const char *output_reg_annotation
[BRW_VARYING_SLOT_COUNT
];
354 int *uniform_vector_size
;
355 int uniform_array_size
; /*< Size of uniform_[vector_]size arrays */
358 src_reg shader_start_time
;
360 struct hash_table
*variable_ht
;
363 void fail(const char *msg
, ...);
365 int virtual_grf_alloc(int size
);
366 void setup_uniform_clipplane_values();
367 void setup_uniform_values(ir_variable
*ir
);
368 void setup_builtin_uniform_values(ir_variable
*ir
);
369 int setup_uniforms(int payload_reg
);
370 bool reg_allocate_trivial();
372 void evaluate_spill_costs(float *spill_costs
, bool *no_spill
);
373 int choose_spill_reg(struct ra_graph
*g
);
374 void spill_reg(int spill_reg
);
375 void move_grf_array_access_to_scratch();
376 void move_uniform_array_access_to_pull_constants();
377 void move_push_constants_to_pull_constants();
378 void split_uniform_registers();
379 void pack_uniform_registers();
380 void calculate_live_intervals();
381 void invalidate_live_intervals(bool invalidate_cfg
= true);
382 void split_virtual_grfs();
383 bool opt_reduce_swizzle();
384 bool dead_code_eliminate();
385 bool virtual_grf_interferes(int a
, int b
);
386 bool opt_copy_propagation();
387 bool opt_cse_local(bblock_t
*block
);
389 bool opt_algebraic();
390 bool opt_register_coalesce();
391 void opt_set_dependency_control();
392 void opt_schedule_instructions();
394 vec4_instruction
*emit(vec4_instruction
*inst
);
396 vec4_instruction
*emit(enum opcode opcode
);
398 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
);
400 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
, src_reg src0
);
402 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
403 src_reg src0
, src_reg src1
);
405 vec4_instruction
*emit(enum opcode opcode
, dst_reg dst
,
406 src_reg src0
, src_reg src1
, src_reg src2
);
408 vec4_instruction
*emit_before(vec4_instruction
*inst
,
409 vec4_instruction
*new_inst
);
411 vec4_instruction
*MOV(const dst_reg
&dst
, const src_reg
&src0
);
412 vec4_instruction
*NOT(const dst_reg
&dst
, const src_reg
&src0
);
413 vec4_instruction
*RNDD(const dst_reg
&dst
, const src_reg
&src0
);
414 vec4_instruction
*RNDE(const dst_reg
&dst
, const src_reg
&src0
);
415 vec4_instruction
*RNDZ(const dst_reg
&dst
, const src_reg
&src0
);
416 vec4_instruction
*FRC(const dst_reg
&dst
, const src_reg
&src0
);
417 vec4_instruction
*F32TO16(const dst_reg
&dst
, const src_reg
&src0
);
418 vec4_instruction
*F16TO32(const dst_reg
&dst
, const src_reg
&src0
);
419 vec4_instruction
*ADD(const dst_reg
&dst
, const src_reg
&src0
,
420 const src_reg
&src1
);
421 vec4_instruction
*MUL(const dst_reg
&dst
, const src_reg
&src0
,
422 const src_reg
&src1
);
423 vec4_instruction
*MACH(const dst_reg
&dst
, const src_reg
&src0
,
424 const src_reg
&src1
);
425 vec4_instruction
*MAC(const dst_reg
&dst
, const src_reg
&src0
,
426 const src_reg
&src1
);
427 vec4_instruction
*AND(const dst_reg
&dst
, const src_reg
&src0
,
428 const src_reg
&src1
);
429 vec4_instruction
*OR(const dst_reg
&dst
, const src_reg
&src0
,
430 const src_reg
&src1
);
431 vec4_instruction
*XOR(const dst_reg
&dst
, const src_reg
&src0
,
432 const src_reg
&src1
);
433 vec4_instruction
*DP3(const dst_reg
&dst
, const src_reg
&src0
,
434 const src_reg
&src1
);
435 vec4_instruction
*DP4(const dst_reg
&dst
, const src_reg
&src0
,
436 const src_reg
&src1
);
437 vec4_instruction
*DPH(const dst_reg
&dst
, const src_reg
&src0
,
438 const src_reg
&src1
);
439 vec4_instruction
*SHL(const dst_reg
&dst
, const src_reg
&src0
,
440 const src_reg
&src1
);
441 vec4_instruction
*SHR(const dst_reg
&dst
, const src_reg
&src0
,
442 const src_reg
&src1
);
443 vec4_instruction
*ASR(const dst_reg
&dst
, const src_reg
&src0
,
444 const src_reg
&src1
);
445 vec4_instruction
*CMP(dst_reg dst
, src_reg src0
, src_reg src1
,
446 enum brw_conditional_mod condition
);
447 vec4_instruction
*IF(src_reg src0
, src_reg src1
,
448 enum brw_conditional_mod condition
);
449 vec4_instruction
*IF(enum brw_predicate predicate
);
450 vec4_instruction
*PULL_CONSTANT_LOAD(const dst_reg
&dst
,
451 const src_reg
&index
);
452 vec4_instruction
*SCRATCH_READ(const dst_reg
&dst
, const src_reg
&index
);
453 vec4_instruction
*SCRATCH_WRITE(const dst_reg
&dst
, const src_reg
&src
,
454 const src_reg
&index
);
455 vec4_instruction
*LRP(const dst_reg
&dst
, const src_reg
&a
,
456 const src_reg
&y
, const src_reg
&x
);
457 vec4_instruction
*BFREV(const dst_reg
&dst
, const src_reg
&value
);
458 vec4_instruction
*BFE(const dst_reg
&dst
, const src_reg
&bits
,
459 const src_reg
&offset
, const src_reg
&value
);
460 vec4_instruction
*BFI1(const dst_reg
&dst
, const src_reg
&bits
,
461 const src_reg
&offset
);
462 vec4_instruction
*BFI2(const dst_reg
&dst
, const src_reg
&bfi1_dst
,
463 const src_reg
&insert
, const src_reg
&base
);
464 vec4_instruction
*FBH(const dst_reg
&dst
, const src_reg
&value
);
465 vec4_instruction
*FBL(const dst_reg
&dst
, const src_reg
&value
);
466 vec4_instruction
*CBIT(const dst_reg
&dst
, const src_reg
&value
);
467 vec4_instruction
*MAD(const dst_reg
&dst
, const src_reg
&c
,
468 const src_reg
&b
, const src_reg
&a
);
469 vec4_instruction
*ADDC(const dst_reg
&dst
, const src_reg
&src0
,
470 const src_reg
&src1
);
471 vec4_instruction
*SUBB(const dst_reg
&dst
, const src_reg
&src0
,
472 const src_reg
&src1
);
474 int implied_mrf_writes(vec4_instruction
*inst
);
476 bool try_rewrite_rhs_to_dst(ir_assignment
*ir
,
479 vec4_instruction
*pre_rhs_inst
,
480 vec4_instruction
*last_rhs_inst
);
482 /** Walks an exec_list of ir_instruction and sends it through this visitor. */
483 void visit_instructions(const exec_list
*list
);
485 void emit_vp_sop(enum brw_conditional_mod condmod
, dst_reg dst
,
486 src_reg src0
, src_reg src1
, src_reg one
);
488 void emit_bool_to_cond_code(ir_rvalue
*ir
, enum brw_predicate
*predicate
);
489 void emit_if_gen6(ir_if
*ir
);
491 void emit_minmax(enum brw_conditional_mod conditionalmod
, dst_reg dst
,
492 src_reg src0
, src_reg src1
);
494 void emit_lrp(const dst_reg
&dst
,
495 const src_reg
&x
, const src_reg
&y
, const src_reg
&a
);
497 void emit_block_move(dst_reg
*dst
, src_reg
*src
,
498 const struct glsl_type
*type
, brw_predicate predicate
);
500 void emit_constant_values(dst_reg
*dst
, ir_constant
*value
);
503 * Emit the correct dot-product instruction for the type of arguments
505 void emit_dp(dst_reg dst
, src_reg src0
, src_reg src1
, unsigned elements
);
507 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
508 dst_reg dst
, src_reg src0
);
510 void emit_scalar(ir_instruction
*ir
, enum prog_opcode op
,
511 dst_reg dst
, src_reg src0
, src_reg src1
);
513 void emit_scs(ir_instruction
*ir
, enum prog_opcode op
,
514 dst_reg dst
, const src_reg
&src
);
516 src_reg
fix_3src_operand(src_reg src
);
518 void emit_math1_gen6(enum opcode opcode
, dst_reg dst
, src_reg src
);
519 void emit_math1_gen4(enum opcode opcode
, dst_reg dst
, src_reg src
);
520 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src
);
521 void emit_math2_gen6(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
522 void emit_math2_gen4(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
523 void emit_math(enum opcode opcode
, dst_reg dst
, src_reg src0
, src_reg src1
);
524 src_reg
fix_math_operand(src_reg src
);
526 void emit_pack_half_2x16(dst_reg dst
, src_reg src0
);
527 void emit_unpack_half_2x16(dst_reg dst
, src_reg src0
);
529 uint32_t gather_channel(ir_texture
*ir
, uint32_t sampler
);
530 src_reg
emit_mcs_fetch(ir_texture
*ir
, src_reg coordinate
, src_reg sampler
);
531 void emit_gen6_gather_wa(uint8_t wa
, dst_reg dst
);
532 void swizzle_result(ir_texture
*ir
, src_reg orig_val
, uint32_t sampler
);
534 void emit_ndc_computation();
535 void emit_psiz_and_flags(struct brw_reg reg
);
536 void emit_clip_distances(dst_reg reg
, int offset
);
537 void emit_generic_urb_slot(dst_reg reg
, int varying
);
538 void emit_urb_slot(int mrf
, int varying
);
540 void emit_shader_time_begin();
541 void emit_shader_time_end();
542 void emit_shader_time_write(enum shader_time_shader_type type
,
545 void emit_untyped_atomic(unsigned atomic_op
, unsigned surf_index
,
546 dst_reg dst
, src_reg offset
, src_reg src0
,
549 void emit_untyped_surface_read(unsigned surf_index
, dst_reg dst
,
552 src_reg
get_scratch_offset(vec4_instruction
*inst
,
553 src_reg
*reladdr
, int reg_offset
);
554 src_reg
get_pull_constant_offset(vec4_instruction
*inst
,
555 src_reg
*reladdr
, int reg_offset
);
556 void emit_scratch_read(vec4_instruction
*inst
,
560 void emit_scratch_write(vec4_instruction
*inst
,
562 void emit_pull_constant_load(vec4_instruction
*inst
,
567 bool try_emit_mad(ir_expression
*ir
);
568 bool try_emit_b2f_of_compare(ir_expression
*ir
);
569 void resolve_ud_negate(src_reg
*reg
);
571 src_reg
get_timestamp();
573 bool process_move_condition(ir_rvalue
*ir
);
575 void dump_instruction(backend_instruction
*inst
);
576 void dump_instruction(backend_instruction
*inst
, FILE *file
);
578 void visit_atomic_counter_intrinsic(ir_call
*ir
);
582 void lower_attributes_to_hw_regs(const int *attribute_map
,
584 void setup_payload_interference(struct ra_graph
*g
, int first_payload_node
,
586 virtual dst_reg
*make_reg_for_system_value(ir_variable
*ir
) = 0;
587 virtual void setup_payload() = 0;
588 virtual void emit_prolog() = 0;
589 virtual void emit_program_code() = 0;
590 virtual void emit_thread_end() = 0;
591 virtual void emit_urb_write_header(int mrf
) = 0;
592 virtual vec4_instruction
*emit_urb_write_opcode(bool complete
) = 0;
593 virtual int compute_array_stride(ir_dereference_array
*ir
);
595 const bool debug_flag
;
599 * If true, then register allocation should fail instead of spilling.
601 const bool no_spills
;
603 const shader_time_shader_type st_base
;
604 const shader_time_shader_type st_written
;
605 const shader_time_shader_type st_reset
;
610 * The vertex shader code generator.
612 * Translates VS IR to actual i965 assembly code.
617 vec4_generator(struct brw_context
*brw
,
618 struct gl_shader_program
*shader_prog
,
619 struct gl_program
*prog
,
620 struct brw_vec4_prog_data
*prog_data
,
625 const unsigned *generate_assembly(const cfg_t
*cfg
, unsigned *asm_size
);
628 void generate_code(const cfg_t
*cfg
);
630 void generate_math1_gen4(vec4_instruction
*inst
,
633 void generate_math2_gen4(vec4_instruction
*inst
,
636 struct brw_reg src1
);
637 void generate_math_gen6(vec4_instruction
*inst
,
640 struct brw_reg src1
);
642 void generate_tex(vec4_instruction
*inst
,
645 struct brw_reg sampler_index
);
647 void generate_vs_urb_write(vec4_instruction
*inst
);
648 void generate_gs_urb_write(vec4_instruction
*inst
);
649 void generate_gs_thread_end(vec4_instruction
*inst
);
650 void generate_gs_set_write_offset(struct brw_reg dst
,
652 struct brw_reg src1
);
653 void generate_gs_set_vertex_count(struct brw_reg dst
,
655 void generate_gs_set_dword_2_immed(struct brw_reg dst
, struct brw_reg src
);
656 void generate_gs_prepare_channel_masks(struct brw_reg dst
);
657 void generate_gs_set_channel_masks(struct brw_reg dst
, struct brw_reg src
);
658 void generate_gs_get_instance_id(struct brw_reg dst
);
659 void generate_gs_ff_sync(vec4_instruction
*inst
,
661 struct brw_reg src0
);
662 void generate_oword_dual_block_offsets(struct brw_reg m1
,
663 struct brw_reg index
);
664 void generate_scratch_write(vec4_instruction
*inst
,
667 struct brw_reg index
);
668 void generate_scratch_read(vec4_instruction
*inst
,
670 struct brw_reg index
);
671 void generate_pull_constant_load(vec4_instruction
*inst
,
673 struct brw_reg index
,
674 struct brw_reg offset
);
675 void generate_pull_constant_load_gen7(vec4_instruction
*inst
,
677 struct brw_reg surf_index
,
678 struct brw_reg offset
);
679 void generate_unpack_flags(vec4_instruction
*inst
,
682 void generate_untyped_atomic(vec4_instruction
*inst
,
684 struct brw_reg atomic_op
,
685 struct brw_reg surf_index
);
687 void generate_untyped_surface_read(vec4_instruction
*inst
,
689 struct brw_reg surf_index
);
691 struct brw_context
*brw
;
693 struct brw_compile
*p
;
695 struct gl_shader_program
*shader_prog
;
696 const struct gl_program
*prog
;
698 struct brw_vec4_prog_data
*prog_data
;
701 const bool debug_flag
;
704 } /* namespace brw */
705 #endif /* __cplusplus */
707 #endif /* BRW_VEC4_H */