src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39 #include "intel_asm_annotation.h"
  40
  41 #ifdef __cplusplus
  42 }; /* extern "C" */
  43 #endif
  44
  45 #include "glsl/ir.h"
  46
  47
  48 struct brw_vec4_compile {
  49    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  50 };
  51
  52
  53 struct brw_vec4_prog_key {
  54    GLuint program_string_id;
  55
  56    /**
  57     * True if at least one clip flag is enabled, regardless of whether the
  58     * shader uses clip planes or gl_ClipDistance.
  59     */
  60    GLuint userclip_active:1;
  61
  62    /**
  63     * How many user clipping planes are being uploaded to the vertex shader as
  64     * push constants.
  65     */
  66    GLuint nr_userclip_plane_consts:4;
  67
  68    GLuint clamp_vertex_color:1;
  69
  70    struct brw_sampler_prog_key_data tex;
  71 };
  72
  73
  74 #ifdef __cplusplus
  75 extern "C" {
  76 #endif
  77
  78 void
  79 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  80                                        struct brw_vec4_prog_key *key,
  81                                        GLuint id, struct gl_program *prog);
  82
  83 #ifdef __cplusplus
  84 } /* extern "C" */
  85
  86 namespace brw {
  87
  88 class dst_reg;
  89
  90 unsigned
  91 swizzle_for_size(int size);
  92
  93 class src_reg : public backend_reg
  94 {
  95 public:
  96    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  97
  98    void init();
  99
 100    src_reg(register_file file, int reg, const glsl_type *type);
 101    src_reg();
 102    src_reg(float f);
 103    src_reg(uint32_t u);
 104    src_reg(int32_t i);
 105    src_reg(struct brw_reg reg);
 106
 107    bool equals(const src_reg &r) const;
 108
 109    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 110    src_reg(class vec4_visitor *v, const struct glsl_type *type, int size);
 111
 112    explicit src_reg(dst_reg reg);
 113
 114    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 115
 116    src_reg *reladdr;
 117 };
 118
 119 static inline src_reg
 120 retype(src_reg reg, enum brw_reg_type type)
 121 {
 122    reg.fixed_hw_reg.type = reg.type = type;
 123    return reg;
 124 }
 125
 126 static inline src_reg
 127 offset(src_reg reg, unsigned delta)
 128 {
 129    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 130    reg.reg_offset += delta;
 131    return reg;
 132 }
 133
 134 /**
 135  * Reswizzle a given source register.
 136  * \sa brw_swizzle().
 137  */
 138 static inline src_reg
 139 swizzle(src_reg reg, unsigned swizzle)
 140 {
 141    assert(reg.file != HW_REG);
 142    reg.swizzle = BRW_SWIZZLE4(
 143       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
 144       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
 145       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
 146       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
 147    return reg;
 148 }
 149
 150 static inline src_reg
 151 negate(src_reg reg)
 152 {
 153    assert(reg.file != HW_REG && reg.file != IMM);
 154    reg.negate = !reg.negate;
 155    return reg;
 156 }
 157
 158 class dst_reg : public backend_reg
 159 {
 160 public:
 161    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 162
 163    void init();
 164
 165    dst_reg();
 166    dst_reg(register_file file, int reg);
 167    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 168    dst_reg(struct brw_reg reg);
 169    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 170
 171    explicit dst_reg(src_reg reg);
 172
 173    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 174
 175    src_reg *reladdr;
 176 };
 177
 178 static inline dst_reg
 179 retype(dst_reg reg, enum brw_reg_type type)
 180 {
 181    reg.fixed_hw_reg.type = reg.type = type;
 182    return reg;
 183 }
 184
 185 static inline dst_reg
 186 offset(dst_reg reg, unsigned delta)
 187 {
 188    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 189    reg.reg_offset += delta;
 190    return reg;
 191 }
 192
 193 static inline dst_reg
 194 writemask(dst_reg reg, unsigned mask)
 195 {
 196    assert(reg.file != HW_REG && reg.file != IMM);
 197    assert((reg.writemask & mask) != 0);
 198    reg.writemask &= mask;
 199    return reg;
 200 }
 201
 202 class vec4_instruction : public backend_instruction {
 203 public:
 204    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 205
 206    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 207                     const dst_reg &dst = dst_reg(),
 208                     const src_reg &src0 = src_reg(),
 209                     const src_reg &src1 = src_reg(),
 210                     const src_reg &src2 = src_reg());
 211
 212    struct brw_reg get_dst(void);
 213    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 214
 215    dst_reg dst;
 216    src_reg src[3];
 217
 218    enum brw_urb_write_flags urb_write_flags;
 219
 220    unsigned sol_binding; /**< gen6: SOL binding table index */
 221    bool sol_final_write; /**< gen6: send commit message */
 222    unsigned sol_vertex; /**< gen6: used for setting dst index in SVB header */
 223
 224    bool is_send_from_grf();
 225    bool can_reswizzle(int dst_writemask, int swizzle, int swizzle_mask);
 226    void reswizzle(int dst_writemask, int swizzle);
 227    bool can_do_source_mods(struct brw_context *brw);
 228
 229    bool reads_flag()
 230    {
 231       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 232    }
 233
 234    bool writes_flag()
 235    {
 236       return conditional_mod && opcode != BRW_OPCODE_SEL;
 237    }
 238 };
 239
 240 /**
 241  * The vertex shader front-end.
 242  *
 243  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 244  * fixed-function) into VS IR.
 245  */
 246 class vec4_visitor : public backend_visitor
 247 {
 248 public:
 249    vec4_visitor(struct brw_context *brw,
 250                 struct brw_vec4_compile *c,
 251                 struct gl_program *prog,
 252                 const struct brw_vec4_prog_key *key,
 253                 struct brw_vec4_prog_data *prog_data,
 254                 struct gl_shader_program *shader_prog,
 255                 gl_shader_stage stage,
 256                 void *mem_ctx,
 257                 bool debug_flag,
 258                 bool no_spills,
 259                 shader_time_shader_type st_base,
 260                 shader_time_shader_type st_written,
 261                 shader_time_shader_type st_reset);
 262    ~vec4_visitor();
 263
 264    dst_reg dst_null_f()
 265    {
 266       return dst_reg(brw_null_reg());
 267    }
 268
 269    dst_reg dst_null_d()
 270    {
 271       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 272    }
 273
 274    dst_reg dst_null_ud()
 275    {
 276       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 277    }
 278
 279    struct brw_vec4_compile * const c;
 280    const struct brw_vec4_prog_key * const key;
 281    struct brw_vec4_prog_data * const prog_data;
 282    unsigned int sanity_param_count;
 283
 284    char *fail_msg;
 285    bool failed;
 286
 287    /**
 288     * GLSL IR currently being processed, which is associated with our
 289     * driver IR instructions for debugging purposes.
 290     */
 291    const void *base_ir;
 292    const char *current_annotation;
 293
 294    int *virtual_grf_sizes;
 295    int virtual_grf_count;
 296    int virtual_grf_array_size;
 297    int first_non_payload_grf;
 298    unsigned int max_grf;
 299    int *virtual_grf_start;
 300    int *virtual_grf_end;
 301    dst_reg userplane[MAX_CLIP_PLANES];
 302
 303    /**
 304     * This is the size to be used for an array with an element per
 305     * reg_offset
 306     */
 307    int virtual_grf_reg_count;
 308    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 309    int *virtual_grf_reg_map;
 310
 311    bool live_intervals_valid;
 312
 313    dst_reg *variable_storage(ir_variable *var);
 314
 315    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 316
 317    bool need_all_constants_in_pull_buffer;
 318
 319    /**
 320     * \name Visit methods
 321     *
 322     * As typical for the visitor pattern, there must be one \c visit method for
 323     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 324     * the hierarchy should not have \c visit methods.
 325     */
 326    /*@{*/
 327    virtual void visit(ir_variable *);
 328    virtual void visit(ir_loop *);
 329    virtual void visit(ir_loop_jump *);
 330    virtual void visit(ir_function_signature *);
 331    virtual void visit(ir_function *);
 332    virtual void visit(ir_expression *);
 333    virtual void visit(ir_swizzle *);
 334    virtual void visit(ir_dereference_variable  *);
 335    virtual void visit(ir_dereference_array *);
 336    virtual void visit(ir_dereference_record *);
 337    virtual void visit(ir_assignment *);
 338    virtual void visit(ir_constant *);
 339    virtual void visit(ir_call *);
 340    virtual void visit(ir_return *);
 341    virtual void visit(ir_discard *);
 342    virtual void visit(ir_texture *);
 343    virtual void visit(ir_if *);
 344    virtual void visit(ir_emit_vertex *);
 345    virtual void visit(ir_end_primitive *);
 346    /*@}*/
 347
 348    src_reg result;
 349
 350    /* Regs for vertex results.  Generated at ir_variable visiting time
 351     * for the ir->location's used.
 352     */
 353    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 354    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 355    int *uniform_size;
 356    int *uniform_vector_size;
 357    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 358    int uniforms;
 359
 360    src_reg shader_start_time;
 361
 362    struct hash_table *variable_ht;
 363
 364    bool run(void);
 365    void fail(const char *msg, ...);
 366
 367    int virtual_grf_alloc(int size);
 368    void setup_uniform_clipplane_values();
 369    void setup_uniform_values(ir_variable *ir);
 370    void setup_builtin_uniform_values(ir_variable *ir);
 371    int setup_uniforms(int payload_reg);
 372    bool reg_allocate_trivial();
 373    bool reg_allocate();
 374    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 375    int choose_spill_reg(struct ra_graph *g);
 376    void spill_reg(int spill_reg);
 377    void move_grf_array_access_to_scratch();
 378    void move_uniform_array_access_to_pull_constants();
 379    void move_push_constants_to_pull_constants();
 380    void split_uniform_registers();
 381    void pack_uniform_registers();
 382    void calculate_live_intervals();
 383    void invalidate_live_intervals();
 384    void split_virtual_grfs();
 385    bool opt_reduce_swizzle();
 386    bool dead_code_eliminate();
 387    bool virtual_grf_interferes(int a, int b);
 388    bool opt_copy_propagation();
 389    bool opt_cse_local(bblock_t *block);
 390    bool opt_cse();
 391    bool opt_algebraic();
 392    bool opt_register_coalesce();
 393    void opt_set_dependency_control();
 394    void opt_schedule_instructions();
 395
 396    vec4_instruction *emit(vec4_instruction *inst);
 397
 398    vec4_instruction *emit(enum opcode opcode);
 399    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 400    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 401                           const src_reg &src0);
 402    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 403                           const src_reg &src0, const src_reg &src1);
 404    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 405                           const src_reg &src0, const src_reg &src1,
 406                           const src_reg &src2);
 407
 408    vec4_instruction *emit_before(bblock_t *block,
 409                                  vec4_instruction *inst,
 410                                  vec4_instruction *new_inst);
 411
 412 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 413 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 414 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 415    EMIT1(MOV)
 416    EMIT1(NOT)
 417    EMIT1(RNDD)
 418    EMIT1(RNDE)
 419    EMIT1(RNDZ)
 420    EMIT1(FRC)
 421    EMIT1(F32TO16)
 422    EMIT1(F16TO32)
 423    EMIT2(ADD)
 424    EMIT2(MUL)
 425    EMIT2(MACH)
 426    EMIT2(MAC)
 427    EMIT2(AND)
 428    EMIT2(OR)
 429    EMIT2(XOR)
 430    EMIT2(DP3)
 431    EMIT2(DP4)
 432    EMIT2(DPH)
 433    EMIT2(SHL)
 434    EMIT2(SHR)
 435    EMIT2(ASR)
 436    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 437                          enum brw_conditional_mod condition);
 438    vec4_instruction *IF(src_reg src0, src_reg src1,
 439                         enum brw_conditional_mod condition);
 440    vec4_instruction *IF(enum brw_predicate predicate);
 441    EMIT1(PULL_CONSTANT_LOAD)
 442    EMIT1(SCRATCH_READ)
 443    EMIT2(SCRATCH_WRITE)
 444    EMIT3(LRP)
 445    EMIT1(BFREV)
 446    EMIT3(BFE)
 447    EMIT2(BFI1)
 448    EMIT3(BFI2)
 449    EMIT1(FBH)
 450    EMIT1(FBL)
 451    EMIT1(CBIT)
 452    EMIT3(MAD)
 453    EMIT2(ADDC)
 454    EMIT2(SUBB)
 455 #undef EMIT1
 456 #undef EMIT2
 457 #undef EMIT3
 458
 459    int implied_mrf_writes(vec4_instruction *inst);
 460
 461    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 462                                dst_reg dst,
 463                                src_reg src,
 464                                vec4_instruction *pre_rhs_inst,
 465                                vec4_instruction *last_rhs_inst);
 466
 467    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 468    void visit_instructions(const exec_list *list);
 469
 470    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 471                     src_reg src0, src_reg src1, src_reg one);
 472
 473    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 474    void emit_if_gen6(ir_if *ir);
 475
 476    void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 477                     src_reg src0, src_reg src1);
 478
 479    void emit_lrp(const dst_reg &dst,
 480                  const src_reg &x, const src_reg &y, const src_reg &a);
 481
 482    void emit_block_move(dst_reg *dst, src_reg *src,
 483                         const struct glsl_type *type, brw_predicate predicate);
 484
 485    void emit_constant_values(dst_reg *dst, ir_constant *value);
 486
 487    /**
 488     * Emit the correct dot-product instruction for the type of arguments
 489     */
 490    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 491
 492    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 493                     dst_reg dst, src_reg src0);
 494
 495    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 496                     dst_reg dst, src_reg src0, src_reg src1);
 497
 498    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 499                  dst_reg dst, const src_reg &src);
 500
 501    src_reg fix_3src_operand(src_reg src);
 502
 503    void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 504                   const src_reg &src1 = src_reg());
 505    src_reg fix_math_operand(src_reg src);
 506
 507    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 508    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 509
 510    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 511    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
 512    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 513    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 514
 515    void emit_ndc_computation();
 516    void emit_psiz_and_flags(dst_reg reg);
 517    void emit_clip_distances(dst_reg reg, int offset);
 518    void emit_generic_urb_slot(dst_reg reg, int varying);
 519    void emit_urb_slot(dst_reg reg, int varying);
 520
 521    void emit_shader_time_begin();
 522    void emit_shader_time_end();
 523    void emit_shader_time_write(enum shader_time_shader_type type,
 524                                src_reg value);
 525
 526    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 527                             dst_reg dst, src_reg offset, src_reg src0,
 528                             src_reg src1);
 529
 530    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 531                                   src_reg offset);
 532
 533    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 534                               src_reg *reladdr, int reg_offset);
 535    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 536                                     src_reg *reladdr, int reg_offset);
 537    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 538                           dst_reg dst,
 539                           src_reg orig_src,
 540                           int base_offset);
 541    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 542                            int base_offset);
 543    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 544                                 dst_reg dst,
 545                                 src_reg orig_src,
 546                                 int base_offset);
 547
 548    bool try_emit_mad(ir_expression *ir);
 549    bool try_emit_b2f_of_compare(ir_expression *ir);
 550    void resolve_ud_negate(src_reg *reg);
 551
 552    src_reg get_timestamp();
 553
 554    bool process_move_condition(ir_rvalue *ir);
 555
 556    void dump_instruction(backend_instruction *inst);
 557    void dump_instruction(backend_instruction *inst, FILE *file);
 558
 559    void visit_atomic_counter_intrinsic(ir_call *ir);
 560
 561 protected:
 562    void emit_vertex();
 563    void lower_attributes_to_hw_regs(const int *attribute_map,
 564                                     bool interleaved);
 565    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 566                                    int reg_node_count);
 567    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 568    virtual void assign_binding_table_offsets();
 569    virtual void setup_payload() = 0;
 570    virtual void emit_prolog() = 0;
 571    virtual void emit_program_code() = 0;
 572    virtual void emit_thread_end() = 0;
 573    virtual void emit_urb_write_header(int mrf) = 0;
 574    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 575    virtual int compute_array_stride(ir_dereference_array *ir);
 576
 577    const bool debug_flag;
 578
 579 private:
 580    /**
 581     * If true, then register allocation should fail instead of spilling.
 582     */
 583    const bool no_spills;
 584
 585    const shader_time_shader_type st_base;
 586    const shader_time_shader_type st_written;
 587    const shader_time_shader_type st_reset;
 588 };
 589
 590
 591 /**
 592  * The vertex shader code generator.
 593  *
 594  * Translates VS IR to actual i965 assembly code.
 595  */
 596 class vec4_generator
 597 {
 598 public:
 599    vec4_generator(struct brw_context *brw,
 600                   struct gl_shader_program *shader_prog,
 601                   struct gl_program *prog,
 602                   struct brw_vec4_prog_data *prog_data,
 603                   void *mem_ctx,
 604                   bool debug_flag);
 605    ~vec4_generator();
 606
 607    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 608
 609 private:
 610    void generate_code(const cfg_t *cfg);
 611
 612    void generate_math1_gen4(vec4_instruction *inst,
 613                             struct brw_reg dst,
 614                             struct brw_reg src);
 615    void generate_math2_gen4(vec4_instruction *inst,
 616                             struct brw_reg dst,
 617                             struct brw_reg src0,
 618                             struct brw_reg src1);
 619    void generate_math_gen6(vec4_instruction *inst,
 620                            struct brw_reg dst,
 621                            struct brw_reg src0,
 622                            struct brw_reg src1);
 623
 624    void generate_tex(vec4_instruction *inst,
 625                      struct brw_reg dst,
 626                      struct brw_reg src,
 627                      struct brw_reg sampler_index);
 628
 629    void generate_vs_urb_write(vec4_instruction *inst);
 630    void generate_gs_urb_write(vec4_instruction *inst);
 631    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 632    void generate_gs_thread_end(vec4_instruction *inst);
 633    void generate_gs_set_write_offset(struct brw_reg dst,
 634                                      struct brw_reg src0,
 635                                      struct brw_reg src1);
 636    void generate_gs_set_vertex_count(struct brw_reg dst,
 637                                      struct brw_reg src);
 638    void generate_gs_svb_write(vec4_instruction *inst,
 639                               struct brw_reg dst,
 640                               struct brw_reg src0,
 641                               struct brw_reg src1);
 642    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 643                                               struct brw_reg dst,
 644                                               struct brw_reg src);
 645    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 646    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 647    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 648    void generate_gs_get_instance_id(struct brw_reg dst);
 649    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 650                                            struct brw_reg src0,
 651                                            struct brw_reg src1,
 652                                            struct brw_reg src2);
 653    void generate_gs_ff_sync(vec4_instruction *inst,
 654                             struct brw_reg dst,
 655                             struct brw_reg src0,
 656                             struct brw_reg src1);
 657    void generate_gs_set_primitive_id(struct brw_reg dst);
 658    void generate_oword_dual_block_offsets(struct brw_reg m1,
 659                                           struct brw_reg index);
 660    void generate_scratch_write(vec4_instruction *inst,
 661                                struct brw_reg dst,
 662                                struct brw_reg src,
 663                                struct brw_reg index);
 664    void generate_scratch_read(vec4_instruction *inst,
 665                               struct brw_reg dst,
 666                               struct brw_reg index);
 667    void generate_pull_constant_load(vec4_instruction *inst,
 668                                     struct brw_reg dst,
 669                                     struct brw_reg index,
 670                                     struct brw_reg offset);
 671    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 672                                          struct brw_reg dst,
 673                                          struct brw_reg surf_index,
 674                                          struct brw_reg offset);
 675    void generate_unpack_flags(vec4_instruction *inst,
 676                               struct brw_reg dst);
 677
 678    void generate_untyped_atomic(vec4_instruction *inst,
 679                                 struct brw_reg dst,
 680                                 struct brw_reg atomic_op,
 681                                 struct brw_reg surf_index);
 682
 683    void generate_untyped_surface_read(vec4_instruction *inst,
 684                                       struct brw_reg dst,
 685                                       struct brw_reg surf_index);
 686
 687    struct brw_context *brw;
 688
 689    struct brw_compile *p;
 690
 691    struct gl_shader_program *shader_prog;
 692    const struct gl_program *prog;
 693
 694    struct brw_vec4_prog_data *prog_data;
 695
 696    void *mem_ctx;
 697    const bool debug_flag;
 698 };
 699
 700 } /* namespace brw */
 701 #endif /* __cplusplus */
 702
 703 #endif /* BRW_VEC4_H */