src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 #include "brw_ir_vec4.h"
  35
  36 extern "C" {
  37 #endif
  38
  39 #include "brw_context.h"
  40 #include "brw_eu.h"
  41 #include "intel_asm_annotation.h"
  42
  43 #ifdef __cplusplus
  44 }; /* extern "C" */
  45 #endif
  46
  47 #include "glsl/ir.h"
  48
  49
  50 struct brw_vec4_compile {
  51    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  52 };
  53
  54 #ifdef __cplusplus
  55 extern "C" {
  56 #endif
  57
  58 void
  59 brw_vue_setup_prog_key_for_precompile(struct gl_context *ctx,
  60                                       struct brw_vue_prog_key *key,
  61                                       GLuint id, struct gl_program *prog);
  62
  63 #ifdef __cplusplus
  64 } /* extern "C" */
  65
  66 namespace brw {
  67
  68 class vec4_live_variables;
  69
  70 /**
  71  * The vertex shader front-end.
  72  *
  73  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
  74  * fixed-function) into VS IR.
  75  */
  76 class vec4_visitor : public backend_shader, public ir_visitor
  77 {
  78 public:
  79    vec4_visitor(struct brw_context *brw,
  80                 struct brw_vec4_compile *c,
  81                 struct gl_program *prog,
  82                 const struct brw_vue_prog_key *key,
  83                 struct brw_vue_prog_data *prog_data,
  84                 struct gl_shader_program *shader_prog,
  85                 gl_shader_stage stage,
  86                 void *mem_ctx,
  87                 bool no_spills,
  88                 shader_time_shader_type st_base,
  89                 shader_time_shader_type st_written,
  90                 shader_time_shader_type st_reset);
  91    ~vec4_visitor();
  92
  93    dst_reg dst_null_f()
  94    {
  95       return dst_reg(brw_null_reg());
  96    }
  97
  98    dst_reg dst_null_d()
  99    {
 100       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 101    }
 102
 103    dst_reg dst_null_ud()
 104    {
 105       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 106    }
 107
 108    struct brw_vec4_compile * const c;
 109    const struct brw_vue_prog_key * const key;
 110    struct brw_vue_prog_data * const prog_data;
 111    unsigned int sanity_param_count;
 112
 113    char *fail_msg;
 114    bool failed;
 115
 116    /**
 117     * GLSL IR currently being processed, which is associated with our
 118     * driver IR instructions for debugging purposes.
 119     */
 120    const void *base_ir;
 121    const char *current_annotation;
 122
 123    int first_non_payload_grf;
 124    unsigned int max_grf;
 125    int *virtual_grf_start;
 126    int *virtual_grf_end;
 127    brw::vec4_live_variables *live_intervals;
 128    dst_reg userplane[MAX_CLIP_PLANES];
 129
 130    dst_reg *variable_storage(ir_variable *var);
 131
 132    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 133
 134    bool need_all_constants_in_pull_buffer;
 135
 136    /**
 137     * \name Visit methods
 138     *
 139     * As typical for the visitor pattern, there must be one \c visit method for
 140     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 141     * the hierarchy should not have \c visit methods.
 142     */
 143    /*@{*/
 144    virtual void visit(ir_variable *);
 145    virtual void visit(ir_loop *);
 146    virtual void visit(ir_loop_jump *);
 147    virtual void visit(ir_function_signature *);
 148    virtual void visit(ir_function *);
 149    virtual void visit(ir_expression *);
 150    virtual void visit(ir_swizzle *);
 151    virtual void visit(ir_dereference_variable  *);
 152    virtual void visit(ir_dereference_array *);
 153    virtual void visit(ir_dereference_record *);
 154    virtual void visit(ir_assignment *);
 155    virtual void visit(ir_constant *);
 156    virtual void visit(ir_call *);
 157    virtual void visit(ir_return *);
 158    virtual void visit(ir_discard *);
 159    virtual void visit(ir_texture *);
 160    virtual void visit(ir_if *);
 161    virtual void visit(ir_emit_vertex *);
 162    virtual void visit(ir_end_primitive *);
 163    virtual void visit(ir_barrier *);
 164    /*@}*/
 165
 166    src_reg result;
 167
 168    /* Regs for vertex results.  Generated at ir_variable visiting time
 169     * for the ir->location's used.
 170     */
 171    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 172    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 173    int *uniform_size;
 174    int *uniform_vector_size;
 175    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 176    int uniforms;
 177
 178    src_reg shader_start_time;
 179
 180    struct hash_table *variable_ht;
 181
 182    bool run(void);
 183    void fail(const char *msg, ...);
 184
 185    void setup_uniform_clipplane_values();
 186    void setup_uniform_values(ir_variable *ir);
 187    void setup_builtin_uniform_values(ir_variable *ir);
 188    int setup_uniforms(int payload_reg);
 189    bool reg_allocate_trivial();
 190    bool reg_allocate();
 191    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 192    int choose_spill_reg(struct ra_graph *g);
 193    void spill_reg(int spill_reg);
 194    void move_grf_array_access_to_scratch();
 195    void move_uniform_array_access_to_pull_constants();
 196    void move_push_constants_to_pull_constants();
 197    void split_uniform_registers();
 198    void pack_uniform_registers();
 199    void calculate_live_intervals();
 200    void invalidate_live_intervals();
 201    void split_virtual_grfs();
 202    bool opt_vector_float();
 203    bool opt_reduce_swizzle();
 204    bool dead_code_eliminate();
 205    int var_range_start(unsigned v, unsigned n) const;
 206    int var_range_end(unsigned v, unsigned n) const;
 207    bool virtual_grf_interferes(int a, int b);
 208    bool opt_copy_propagation(bool do_constant_prop = true);
 209    bool opt_cse_local(bblock_t *block);
 210    bool opt_cse();
 211    bool opt_algebraic();
 212    bool opt_register_coalesce();
 213    bool eliminate_find_live_channel();
 214    bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
 215    void opt_set_dependency_control();
 216    void opt_schedule_instructions();
 217
 218    vec4_instruction *emit(vec4_instruction *inst);
 219
 220    vec4_instruction *emit(enum opcode opcode);
 221    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst);
 222    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 223                           const src_reg &src0);
 224    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 225                           const src_reg &src0, const src_reg &src1);
 226    vec4_instruction *emit(enum opcode opcode, const dst_reg &dst,
 227                           const src_reg &src0, const src_reg &src1,
 228                           const src_reg &src2);
 229
 230    vec4_instruction *emit_before(bblock_t *block,
 231                                  vec4_instruction *inst,
 232                                  vec4_instruction *new_inst);
 233
 234 #define EMIT1(op) vec4_instruction *op(const dst_reg &, const src_reg &);
 235 #define EMIT2(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &);
 236 #define EMIT3(op) vec4_instruction *op(const dst_reg &, const src_reg &, const src_reg &, const src_reg &);
 237    EMIT1(MOV)
 238    EMIT1(NOT)
 239    EMIT1(RNDD)
 240    EMIT1(RNDE)
 241    EMIT1(RNDZ)
 242    EMIT1(FRC)
 243    EMIT1(F32TO16)
 244    EMIT1(F16TO32)
 245    EMIT2(ADD)
 246    EMIT2(MUL)
 247    EMIT2(MACH)
 248    EMIT2(MAC)
 249    EMIT2(AND)
 250    EMIT2(OR)
 251    EMIT2(XOR)
 252    EMIT2(DP3)
 253    EMIT2(DP4)
 254    EMIT2(DPH)
 255    EMIT2(SHL)
 256    EMIT2(SHR)
 257    EMIT2(ASR)
 258    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 259                          enum brw_conditional_mod condition);
 260    vec4_instruction *IF(src_reg src0, src_reg src1,
 261                         enum brw_conditional_mod condition);
 262    vec4_instruction *IF(enum brw_predicate predicate);
 263    EMIT1(SCRATCH_READ)
 264    EMIT2(SCRATCH_WRITE)
 265    EMIT3(LRP)
 266    EMIT1(BFREV)
 267    EMIT3(BFE)
 268    EMIT2(BFI1)
 269    EMIT3(BFI2)
 270    EMIT1(FBH)
 271    EMIT1(FBL)
 272    EMIT1(CBIT)
 273    EMIT3(MAD)
 274    EMIT2(ADDC)
 275    EMIT2(SUBB)
 276 #undef EMIT1
 277 #undef EMIT2
 278 #undef EMIT3
 279
 280    int implied_mrf_writes(vec4_instruction *inst);
 281
 282    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 283                                dst_reg dst,
 284                                src_reg src,
 285                                vec4_instruction *pre_rhs_inst,
 286                                vec4_instruction *last_rhs_inst);
 287
 288    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 289    void visit_instructions(const exec_list *list);
 290
 291    void emit_vp_sop(enum brw_conditional_mod condmod, dst_reg dst,
 292                     src_reg src0, src_reg src1, src_reg one);
 293
 294    void emit_bool_to_cond_code(ir_rvalue *ir, enum brw_predicate *predicate);
 295    void emit_if_gen6(ir_if *ir);
 296
 297    void emit_minmax(enum brw_conditional_mod conditionalmod, dst_reg dst,
 298                     src_reg src0, src_reg src1);
 299
 300    void emit_lrp(const dst_reg &dst,
 301                  const src_reg &x, const src_reg &y, const src_reg &a);
 302
 303    /** Copy any live channel from \p src to the first channel of \p dst. */
 304    void emit_uniformize(const dst_reg &dst, const src_reg &src);
 305
 306    void emit_block_move(dst_reg *dst, src_reg *src,
 307                         const struct glsl_type *type, brw_predicate predicate);
 308
 309    void emit_constant_values(dst_reg *dst, ir_constant *value);
 310
 311    /**
 312     * Emit the correct dot-product instruction for the type of arguments
 313     */
 314    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 315
 316    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 317                     dst_reg dst, src_reg src0);
 318
 319    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 320                     dst_reg dst, src_reg src0, src_reg src1);
 321
 322    src_reg fix_3src_operand(src_reg src);
 323
 324    void emit_math(enum opcode opcode, const dst_reg &dst, const src_reg &src0,
 325                   const src_reg &src1 = src_reg());
 326    src_reg fix_math_operand(src_reg src);
 327
 328    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 329    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 330    void emit_unpack_unorm_4x8(const dst_reg &dst, src_reg src0);
 331    void emit_unpack_snorm_4x8(const dst_reg &dst, src_reg src0);
 332    void emit_pack_unorm_4x8(const dst_reg &dst, const src_reg &src0);
 333    void emit_pack_snorm_4x8(const dst_reg &dst, const src_reg &src0);
 334
 335    uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
 336    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
 337    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 338    void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 339
 340    void emit_ndc_computation();
 341    void emit_psiz_and_flags(dst_reg reg);
 342    void emit_clip_distances(dst_reg reg, int offset);
 343    vec4_instruction *emit_generic_urb_slot(dst_reg reg, int varying);
 344    void emit_urb_slot(dst_reg reg, int varying);
 345
 346    void emit_shader_time_begin();
 347    void emit_shader_time_end();
 348    void emit_shader_time_write(enum shader_time_shader_type type,
 349                                src_reg value);
 350
 351    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 352                             dst_reg dst, src_reg offset, src_reg src0,
 353                             src_reg src1);
 354
 355    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 356                                   src_reg offset);
 357
 358    src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
 359                               src_reg *reladdr, int reg_offset);
 360    src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
 361                                     src_reg *reladdr, int reg_offset);
 362    void emit_scratch_read(bblock_t *block, vec4_instruction *inst,
 363                           dst_reg dst,
 364                           src_reg orig_src,
 365                           int base_offset);
 366    void emit_scratch_write(bblock_t *block, vec4_instruction *inst,
 367                            int base_offset);
 368    void emit_pull_constant_load(bblock_t *block, vec4_instruction *inst,
 369                                 dst_reg dst,
 370                                 src_reg orig_src,
 371                                 int base_offset);
 372    void emit_pull_constant_load_reg(dst_reg dst,
 373                                     src_reg surf_index,
 374                                     src_reg offset,
 375                                     bblock_t *before_block,
 376                                     vec4_instruction *before_inst);
 377    src_reg emit_resolve_reladdr(int scratch_loc[], bblock_t *block,
 378                                 vec4_instruction *inst, src_reg src);
 379
 380    bool try_emit_mad(ir_expression *ir);
 381    bool try_emit_b2f_of_compare(ir_expression *ir);
 382    void resolve_ud_negate(src_reg *reg);
 383    void resolve_bool_comparison(ir_rvalue *rvalue, src_reg *reg);
 384
 385    src_reg get_timestamp();
 386
 387    bool process_move_condition(ir_rvalue *ir);
 388
 389    void dump_instruction(backend_instruction *inst);
 390    void dump_instruction(backend_instruction *inst, FILE *file);
 391
 392    void visit_atomic_counter_intrinsic(ir_call *ir);
 393
 394 protected:
 395    void emit_vertex();
 396    void lower_attributes_to_hw_regs(const int *attribute_map,
 397                                     bool interleaved);
 398    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 399                                    int reg_node_count);
 400    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 401    virtual void assign_binding_table_offsets();
 402    virtual void setup_payload() = 0;
 403    virtual void emit_prolog() = 0;
 404    virtual void emit_program_code() = 0;
 405    virtual void emit_thread_end() = 0;
 406    virtual void emit_urb_write_header(int mrf) = 0;
 407    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 408    virtual int compute_array_stride(ir_dereference_array *ir);
 409
 410 private:
 411    /**
 412     * If true, then register allocation should fail instead of spilling.
 413     */
 414    const bool no_spills;
 415
 416    const shader_time_shader_type st_base;
 417    const shader_time_shader_type st_written;
 418    const shader_time_shader_type st_reset;
 419 };
 420
 421
 422 /**
 423  * The vertex shader code generator.
 424  *
 425  * Translates VS IR to actual i965 assembly code.
 426  */
 427 class vec4_generator
 428 {
 429 public:
 430    vec4_generator(const struct brw_compiler *compiler,
 431                   struct gl_shader_program *shader_prog,
 432                   struct gl_program *prog,
 433                   struct brw_vue_prog_data *prog_data,
 434                   void *mem_ctx,
 435                   bool debug_flag,
 436                   const char *stage_name,
 437                   const char *stage_abbrev);
 438    ~vec4_generator();
 439
 440    const unsigned *generate_assembly(const cfg_t *cfg, unsigned *asm_size);
 441
 442 private:
 443    void generate_code(const cfg_t *cfg);
 444
 445    void generate_math1_gen4(vec4_instruction *inst,
 446                             struct brw_reg dst,
 447                             struct brw_reg src);
 448    void generate_math2_gen4(vec4_instruction *inst,
 449                             struct brw_reg dst,
 450                             struct brw_reg src0,
 451                             struct brw_reg src1);
 452    void generate_math_gen6(vec4_instruction *inst,
 453                            struct brw_reg dst,
 454                            struct brw_reg src0,
 455                            struct brw_reg src1);
 456
 457    void generate_tex(vec4_instruction *inst,
 458                      struct brw_reg dst,
 459                      struct brw_reg src,
 460                      struct brw_reg sampler_index);
 461
 462    void generate_vs_urb_write(vec4_instruction *inst);
 463    void generate_gs_urb_write(vec4_instruction *inst);
 464    void generate_gs_urb_write_allocate(vec4_instruction *inst);
 465    void generate_gs_thread_end(vec4_instruction *inst);
 466    void generate_gs_set_write_offset(struct brw_reg dst,
 467                                      struct brw_reg src0,
 468                                      struct brw_reg src1);
 469    void generate_gs_set_vertex_count(struct brw_reg dst,
 470                                      struct brw_reg src);
 471    void generate_gs_svb_write(vec4_instruction *inst,
 472                               struct brw_reg dst,
 473                               struct brw_reg src0,
 474                               struct brw_reg src1);
 475    void generate_gs_svb_set_destination_index(vec4_instruction *inst,
 476                                               struct brw_reg dst,
 477                                               struct brw_reg src);
 478    void generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src);
 479    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 480    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 481    void generate_gs_get_instance_id(struct brw_reg dst);
 482    void generate_gs_ff_sync_set_primitives(struct brw_reg dst,
 483                                            struct brw_reg src0,
 484                                            struct brw_reg src1,
 485                                            struct brw_reg src2);
 486    void generate_gs_ff_sync(vec4_instruction *inst,
 487                             struct brw_reg dst,
 488                             struct brw_reg src0,
 489                             struct brw_reg src1);
 490    void generate_gs_set_primitive_id(struct brw_reg dst);
 491    void generate_oword_dual_block_offsets(struct brw_reg m1,
 492                                           struct brw_reg index);
 493    void generate_scratch_write(vec4_instruction *inst,
 494                                struct brw_reg dst,
 495                                struct brw_reg src,
 496                                struct brw_reg index);
 497    void generate_scratch_read(vec4_instruction *inst,
 498                               struct brw_reg dst,
 499                               struct brw_reg index);
 500    void generate_pull_constant_load(vec4_instruction *inst,
 501                                     struct brw_reg dst,
 502                                     struct brw_reg index,
 503                                     struct brw_reg offset);
 504    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 505                                          struct brw_reg dst,
 506                                          struct brw_reg surf_index,
 507                                          struct brw_reg offset);
 508    void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
 509                                          struct brw_reg dst);
 510    void generate_unpack_flags(struct brw_reg dst);
 511
 512    const struct brw_compiler *compiler;
 513    const struct brw_device_info *devinfo;
 514
 515    struct brw_codegen *p;
 516
 517    struct gl_shader_program *shader_prog;
 518    const struct gl_program *prog;
 519
 520    struct brw_vue_prog_data *prog_data;
 521
 522    void *mem_ctx;
 523    const char *stage_name;
 524    const char *stage_abbrev;
 525    const bool debug_flag;
 526 };
 527
 528 } /* namespace brw */
 529 #endif /* __cplusplus */
 530
 531 #endif /* BRW_VEC4_H */