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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
34 #include "main/macros.h"
40 is_direct_copy(vec4_instruction
*inst
)
42 return (inst
->opcode
== BRW_OPCODE_MOV
&&
44 inst
->dst
.file
== GRF
&&
47 !inst
->src
[0].reladdr
&&
48 inst
->dst
.type
== inst
->src
[0].type
);
52 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
54 return (inst
->opcode
!= BRW_OPCODE_DO
&&
55 inst
->opcode
!= BRW_OPCODE_WHILE
&&
56 inst
->opcode
!= BRW_OPCODE_ELSE
&&
57 inst
->opcode
!= BRW_OPCODE_ENDIF
);
61 try_constant_propagation(vec4_instruction
*inst
, int arg
, src_reg
*values
[4])
63 /* For constant propagation, we only handle the same constant
64 * across all 4 channels. Some day, we should handle the 8-bit
65 * float vector format, which would let us constant propagate
68 src_reg value
= *values
[0];
69 for (int i
= 1; i
< 4; i
++) {
70 if (!value
.equals(values
[i
]))
74 if (value
.file
!= IMM
)
77 if (inst
->src
[arg
].abs
) {
78 if (value
.type
== BRW_REGISTER_TYPE_F
) {
79 value
.imm
.f
= fabs(value
.imm
.f
);
80 } else if (value
.type
== BRW_REGISTER_TYPE_D
) {
82 value
.imm
.i
= -value
.imm
.i
;
86 if (inst
->src
[arg
].negate
) {
87 if (value
.type
== BRW_REGISTER_TYPE_F
)
88 value
.imm
.f
= -value
.imm
.f
;
90 value
.imm
.u
= -value
.imm
.u
;
93 switch (inst
->opcode
) {
95 inst
->src
[arg
] = value
;
101 inst
->src
[arg
] = value
;
103 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
104 /* Fit this constant in by commuting the operands. Exception: we
105 * can't do this for 32-bit integer MUL because it's asymmetric.
107 if (inst
->opcode
== BRW_OPCODE_MUL
&&
108 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
109 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
111 inst
->src
[0] = inst
->src
[1];
112 inst
->src
[1] = value
;
119 inst
->src
[arg
] = value
;
121 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
124 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
125 if (new_cmod
!= ~0u) {
126 /* Fit this constant in by swapping the operands and
129 inst
->src
[0] = inst
->src
[1];
130 inst
->src
[1] = value
;
131 inst
->conditional_mod
= new_cmod
;
139 inst
->src
[arg
] = value
;
141 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
142 inst
->src
[0] = inst
->src
[1];
143 inst
->src
[1] = value
;
145 /* If this was predicated, flipping operands means
146 * we also need to flip the predicate.
148 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
149 inst
->predicate_inverse
= !inst
->predicate_inverse
;
163 try_copy_propagation(struct intel_context
*intel
,
164 vec4_instruction
*inst
, int arg
, src_reg
*values
[4])
166 /* For constant propagation, we only handle the same constant
167 * across all 4 channels. Some day, we should handle the 8-bit
168 * float vector format, which would let us constant propagate
171 src_reg value
= *values
[0];
172 for (int i
= 1; i
< 4; i
++) {
173 /* This is equals() except we don't care about the swizzle. */
174 if (value
.file
!= values
[i
]->file
||
175 value
.reg
!= values
[i
]->reg
||
176 value
.reg_offset
!= values
[i
]->reg_offset
||
177 value
.type
!= values
[i
]->type
||
178 value
.negate
!= values
[i
]->negate
||
179 value
.abs
!= values
[i
]->abs
) {
184 /* Compute the swizzle of the original register by swizzling the
185 * component loaded from each value according to the swizzle of
186 * operand we're going to change.
189 for (int i
= 0; i
< 4; i
++) {
190 s
[i
] = BRW_GET_SWZ(values
[i
]->swizzle
,
191 BRW_GET_SWZ(inst
->src
[arg
].swizzle
, i
));
193 value
.swizzle
= BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]);
195 if (value
.file
!= UNIFORM
&&
200 if (inst
->src
[arg
].abs
) {
201 value
.negate
= false;
204 if (inst
->src
[arg
].negate
)
205 value
.negate
= !value
.negate
;
207 /* FINISHME: We can't copy-propagate things that aren't normal
208 * vec8s into gen6 math instructions, because of the weird src
209 * handling for those instructions. Just ignore them for now.
211 if (intel
->gen
>= 6 && inst
->is_math())
214 /* We can't copy-propagate a UD negation into a condmod
215 * instruction, because the condmod ends up looking at the 33-bit
216 * signed accumulator value instead of the 32-bit value we wanted
218 if (inst
->conditional_mod
&&
220 value
.type
== BRW_REGISTER_TYPE_UD
)
223 /* Don't report progress if this is a noop. */
224 if (value
.equals(&inst
->src
[arg
]))
227 inst
->src
[arg
] = value
;
232 vec4_visitor::opt_copy_propagation()
234 bool progress
= false;
235 src_reg
*cur_value
[virtual_grf_reg_count
][4];
237 memset(&cur_value
, 0, sizeof(cur_value
));
239 foreach_list(node
, &this->instructions
) {
240 vec4_instruction
*inst
= (vec4_instruction
*)node
;
242 /* This pass only works on basic blocks. If there's flow
243 * control, throw out all our information and start from
246 * This should really be fixed by using a structure like in
247 * src/glsl/opt_copy_propagation.cpp to track available copies.
249 if (!is_dominated_by_previous_instruction(inst
)) {
250 memset(cur_value
, 0, sizeof(cur_value
));
254 /* For each source arg, see if each component comes from a copy
255 * from the same type file (IMM, GRF, UNIFORM), and try
256 * optimizing out access to the copy result
258 for (int i
= 2; i
>= 0; i
--) {
259 /* Copied values end up in GRFs, and we don't track reladdr
262 if (inst
->src
[i
].file
!= GRF
||
263 inst
->src
[i
].reladdr
)
266 int reg
= (virtual_grf_reg_map
[inst
->src
[i
].reg
] +
267 inst
->src
[i
].reg_offset
);
269 /* Find the regs that each swizzle component came from.
273 for (c
= 0; c
< 4; c
++) {
274 values
[c
] = cur_value
[reg
][BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)];
276 /* If there's no available copy for this channel, bail.
277 * We could be more aggressive here -- some channels might
278 * not get used based on the destination writemask.
283 /* We'll only be able to copy propagate if the sources are
284 * all from the same file -- there's no ability to swizzle
285 * 0 or 1 constants in with source registers like in i915.
287 if (c
> 0 && values
[c
- 1]->file
!= values
[c
]->file
)
294 if (try_constant_propagation(inst
, i
, values
) ||
295 try_copy_propagation(intel
, inst
, i
, values
))
299 /* Track available source registers. */
300 const int reg
= virtual_grf_reg_map
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
302 /* Update our destination's current channel values. For a direct copy,
303 * the value is the newly propagated source. Otherwise, we don't know
304 * the new value, so clear it.
306 bool direct_copy
= is_direct_copy(inst
);
307 for (int i
= 0; i
< 4; i
++) {
308 if (inst
->dst
.writemask
& (1 << i
)) {
309 cur_value
[reg
][i
] = direct_copy
? &inst
->src
[0] : NULL
;
313 /* Clear the records for any registers whose current value came from
314 * our destination's updated channels, as the two are no longer equal.
316 if (inst
->dst
.file
== GRF
) {
317 if (inst
->dst
.reladdr
)
318 memset(cur_value
, 0, sizeof(cur_value
));
320 for (int i
= 0; i
< virtual_grf_reg_count
; i
++) {
321 for (int j
= 0; j
< 4; j
++) {
322 if (inst
->dst
.writemask
& (1 << j
) &&
324 cur_value
[i
][j
]->file
== GRF
&&
325 cur_value
[i
][j
]->reg
== inst
->dst
.reg
&&
326 cur_value
[i
][j
]->reg_offset
== inst
->dst
.reg_offset
) {
327 cur_value
[i
][j
] = NULL
;
336 live_intervals_valid
= false;
341 } /* namespace brw */