src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  62 {
  63    const src_reg *src = values[ch];
  64
  65    /* consider GRF only */
  66    assert(inst->dst.file == GRF);
  67    if (!src || src->file != GRF)
  68       return false;
  69
  70    return (src->reg == inst->dst.reg &&
  71            src->reg_offset == inst->dst.reg_offset &&
  72            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  73 }
  74
  75 static bool
  76 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
  77 {
  78    /* For constant propagation, we only handle the same constant
  79     * across all 4 channels.  Some day, we should handle the 8-bit
  80     * float vector format, which would let us constant propagate
  81     * vectors better.
  82     */
  83    src_reg value = *values[0];
  84    for (int i = 1; i < 4; i++) {
  85       if (!value.equals(*values[i]))
  86          return false;
  87    }
  88
  89    if (value.file != IMM)
  90       return false;
  91
  92    if (inst->src[arg].abs) {
  93       if (value.type == BRW_REGISTER_TYPE_F) {
  94          value.imm.f = fabs(value.imm.f);
  95       } else if (value.type == BRW_REGISTER_TYPE_D) {
  96          if (value.imm.i < 0)
  97             value.imm.i = -value.imm.i;
  98       }
  99    }
 100
 101    if (inst->src[arg].negate) {
 102       if (value.type == BRW_REGISTER_TYPE_F)
 103          value.imm.f = -value.imm.f;
 104       else
 105          value.imm.u = -value.imm.u;
 106    }
 107
 108    switch (inst->opcode) {
 109    case BRW_OPCODE_MOV:
 110       inst->src[arg] = value;
 111       return true;
 112
 113    case BRW_OPCODE_DP2:
 114    case BRW_OPCODE_DP3:
 115    case BRW_OPCODE_DP4:
 116    case BRW_OPCODE_DPH:
 117    case BRW_OPCODE_BFI1:
 118    case BRW_OPCODE_ASR:
 119    case BRW_OPCODE_SHL:
 120    case BRW_OPCODE_SHR:
 121    case BRW_OPCODE_SUBB:
 122       if (arg == 1) {
 123          inst->src[arg] = value;
 124          return true;
 125       }
 126       break;
 127
 128    case BRW_OPCODE_MACH:
 129    case BRW_OPCODE_MUL:
 130    case BRW_OPCODE_ADD:
 131    case BRW_OPCODE_OR:
 132    case BRW_OPCODE_AND:
 133    case BRW_OPCODE_XOR:
 134    case BRW_OPCODE_ADDC:
 135       if (arg == 1) {
 136          inst->src[arg] = value;
 137          return true;
 138       } else if (arg == 0 && inst->src[1].file != IMM) {
 139          /* Fit this constant in by commuting the operands.  Exception: we
 140           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 141           */
 142          if ((inst->opcode == BRW_OPCODE_MUL ||
 143               inst->opcode == BRW_OPCODE_MACH) &&
 144              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 145               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 146             break;
 147          inst->src[0] = inst->src[1];
 148          inst->src[1] = value;
 149          return true;
 150       }
 151       break;
 152
 153    case BRW_OPCODE_CMP:
 154       if (arg == 1) {
 155          inst->src[arg] = value;
 156          return true;
 157       } else if (arg == 0 && inst->src[1].file != IMM) {
 158          uint32_t new_cmod;
 159
 160          new_cmod = brw_swap_cmod(inst->conditional_mod);
 161          if (new_cmod != ~0u) {
 162             /* Fit this constant in by swapping the operands and
 163              * flipping the test.
 164              */
 165             inst->src[0] = inst->src[1];
 166             inst->src[1] = value;
 167             inst->conditional_mod = new_cmod;
 168             return true;
 169          }
 170       }
 171       break;
 172
 173    case BRW_OPCODE_SEL:
 174       if (arg == 1) {
 175          inst->src[arg] = value;
 176          return true;
 177       } else if (arg == 0 && inst->src[1].file != IMM) {
 178          inst->src[0] = inst->src[1];
 179          inst->src[1] = value;
 180
 181          /* If this was predicated, flipping operands means
 182           * we also need to flip the predicate.
 183           */
 184          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 185             inst->predicate_inverse = !inst->predicate_inverse;
 186          }
 187          return true;
 188       }
 189       break;
 190
 191    default:
 192       break;
 193    }
 194
 195    return false;
 196 }
 197
 198 static bool
 199 is_logic_op(enum opcode opcode)
 200 {
 201    return (opcode == BRW_OPCODE_AND ||
 202            opcode == BRW_OPCODE_OR  ||
 203            opcode == BRW_OPCODE_XOR ||
 204            opcode == BRW_OPCODE_NOT);
 205 }
 206
 207 bool
 208 vec4_visitor::try_copy_propagation(vec4_instruction *inst, int arg,
 209                                    src_reg *values[4])
 210 {
 211    /* For constant propagation, we only handle the same constant
 212     * across all 4 channels.  Some day, we should handle the 8-bit
 213     * float vector format, which would let us constant propagate
 214     * vectors better.
 215     */
 216    src_reg value = *values[0];
 217    for (int i = 1; i < 4; i++) {
 218       /* This is equals() except we don't care about the swizzle. */
 219       if (value.file != values[i]->file ||
 220           value.reg != values[i]->reg ||
 221           value.reg_offset != values[i]->reg_offset ||
 222           value.type != values[i]->type ||
 223           value.negate != values[i]->negate ||
 224           value.abs != values[i]->abs) {
 225          return false;
 226       }
 227    }
 228
 229    /* Compute the swizzle of the original register by swizzling the
 230     * component loaded from each value according to the swizzle of
 231     * operand we're going to change.
 232     */
 233    int s[4];
 234    for (int i = 0; i < 4; i++) {
 235       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 236                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 237    }
 238    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 239
 240    if (value.file != UNIFORM &&
 241        value.file != GRF &&
 242        value.file != ATTR)
 243       return false;
 244
 245    if (brw->gen >= 8) {
 246       if (value.negate) {
 247          if (is_logic_op(inst->opcode)) {
 248             return false;
 249          }
 250       }
 251    }
 252
 253    if (inst->src[arg].abs) {
 254       value.negate = false;
 255       value.abs = true;
 256    }
 257    if (inst->src[arg].negate)
 258       value.negate = !value.negate;
 259
 260    bool has_source_modifiers = value.negate || value.abs;
 261
 262    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 263     * instructions.
 264     */
 265    if ((has_source_modifiers || value.file == UNIFORM ||
 266         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
 267       return false;
 268
 269    if (has_source_modifiers && value.type != inst->src[arg].type)
 270       return false;
 271
 272    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 273                         inst->opcode == BRW_OPCODE_MAD ||
 274                         inst->opcode == BRW_OPCODE_BFE ||
 275                         inst->opcode == BRW_OPCODE_BFI2);
 276    if (is_3src_inst && value.file == UNIFORM)
 277       return false;
 278
 279    if (inst->is_send_from_grf())
 280       return false;
 281
 282    /* We can't copy-propagate a UD negation into a condmod
 283     * instruction, because the condmod ends up looking at the 33-bit
 284     * signed accumulator value instead of the 32-bit value we wanted
 285     */
 286    if (inst->conditional_mod &&
 287        value.negate &&
 288        value.type == BRW_REGISTER_TYPE_UD)
 289       return false;
 290
 291    /* Don't report progress if this is a noop. */
 292    if (value.equals(inst->src[arg]))
 293       return false;
 294
 295    value.type = inst->src[arg].type;
 296    inst->src[arg] = value;
 297    return true;
 298 }
 299
 300 bool
 301 vec4_visitor::opt_copy_propagation()
 302 {
 303    bool progress = false;
 304    src_reg *cur_value[virtual_grf_reg_count][4];
 305
 306    memset(&cur_value, 0, sizeof(cur_value));
 307
 308    foreach_list(node, &this->instructions) {
 309       vec4_instruction *inst = (vec4_instruction *)node;
 310
 311       /* This pass only works on basic blocks.  If there's flow
 312        * control, throw out all our information and start from
 313        * scratch.
 314        *
 315        * This should really be fixed by using a structure like in
 316        * src/glsl/opt_copy_propagation.cpp to track available copies.
 317        */
 318       if (!is_dominated_by_previous_instruction(inst)) {
 319          memset(cur_value, 0, sizeof(cur_value));
 320          continue;
 321       }
 322
 323       /* For each source arg, see if each component comes from a copy
 324        * from the same type file (IMM, GRF, UNIFORM), and try
 325        * optimizing out access to the copy result
 326        */
 327       for (int i = 2; i >= 0; i--) {
 328          /* Copied values end up in GRFs, and we don't track reladdr
 329           * accesses.
 330           */
 331          if (inst->src[i].file != GRF ||
 332              inst->src[i].reladdr)
 333             continue;
 334
 335          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 336                     inst->src[i].reg_offset);
 337
 338          /* Find the regs that each swizzle component came from.
 339           */
 340          src_reg *values[4];
 341          int c;
 342          for (c = 0; c < 4; c++) {
 343             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 344
 345             /* If there's no available copy for this channel, bail.
 346              * We could be more aggressive here -- some channels might
 347              * not get used based on the destination writemask.
 348              */
 349             if (!values[c])
 350                break;
 351
 352             /* We'll only be able to copy propagate if the sources are
 353              * all from the same file -- there's no ability to swizzle
 354              * 0 or 1 constants in with source registers like in i915.
 355              */
 356             if (c > 0 && values[c - 1]->file != values[c]->file)
 357                break;
 358          }
 359
 360          if (c != 4)
 361             continue;
 362
 363          if (try_constant_propagation(inst, i, values) ||
 364              try_copy_propagation(inst, i, values))
 365             progress = true;
 366       }
 367
 368       /* Track available source registers. */
 369       if (inst->dst.file == GRF) {
 370          const int reg =
 371             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 372
 373          /* Update our destination's current channel values.  For a direct copy,
 374           * the value is the newly propagated source.  Otherwise, we don't know
 375           * the new value, so clear it.
 376           */
 377          bool direct_copy = is_direct_copy(inst);
 378          for (int i = 0; i < 4; i++) {
 379             if (inst->dst.writemask & (1 << i)) {
 380                cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
 381             }
 382          }
 383
 384          /* Clear the records for any registers whose current value came from
 385           * our destination's updated channels, as the two are no longer equal.
 386           */
 387          if (inst->dst.reladdr)
 388             memset(cur_value, 0, sizeof(cur_value));
 389          else {
 390             for (int i = 0; i < virtual_grf_reg_count; i++) {
 391                for (int j = 0; j < 4; j++) {
 392                   if (is_channel_updated(inst, cur_value[i], j)){
 393                      cur_value[i][j] = NULL;
 394                   }
 395                }
 396             }
 397          }
 398       }
 399    }
 400
 401    if (progress)
 402       invalidate_live_intervals();
 403
 404    return progress;
 405 }
 406
 407 } /* namespace brw */