src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  62 {
  63    const src_reg *src = values[ch];
  64
  65    /* consider GRF only */
  66    assert(inst->dst.file == GRF);
  67    if (!src || src->file != GRF)
  68       return false;
  69
  70    return (src->reg == inst->dst.reg &&
  71            src->reg_offset == inst->dst.reg_offset &&
  72            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  73 }
  74
  75 static bool
  76 try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
  77                        int arg, src_reg *values[4])
  78 {
  79    /* For constant propagation, we only handle the same constant
  80     * across all 4 channels.  Some day, we should handle the 8-bit
  81     * float vector format, which would let us constant propagate
  82     * vectors better.
  83     */
  84    src_reg value = *values[0];
  85    for (int i = 1; i < 4; i++) {
  86       if (!value.equals(*values[i]))
  87          return false;
  88    }
  89
  90    if (value.file != IMM)
  91       return false;
  92
  93    if (inst->src[arg].abs) {
  94       if (value.type == BRW_REGISTER_TYPE_F) {
  95          value.fixed_hw_reg.dw1.f = fabs(value.fixed_hw_reg.dw1.f);
  96       } else if (value.type == BRW_REGISTER_TYPE_D) {
  97          if (value.fixed_hw_reg.dw1.d < 0)
  98             value.fixed_hw_reg.dw1.d = -value.fixed_hw_reg.dw1.d;
  99       }
 100    }
 101
 102    if (inst->src[arg].negate) {
 103       if (value.type == BRW_REGISTER_TYPE_F)
 104          value.fixed_hw_reg.dw1.f = -value.fixed_hw_reg.dw1.f;
 105       else
 106          value.fixed_hw_reg.dw1.ud = -value.fixed_hw_reg.dw1.ud;
 107    }
 108
 109    switch (inst->opcode) {
 110    case BRW_OPCODE_MOV:
 111       inst->src[arg] = value;
 112       return true;
 113
 114    case SHADER_OPCODE_POW:
 115    case SHADER_OPCODE_INT_QUOTIENT:
 116    case SHADER_OPCODE_INT_REMAINDER:
 117       if (brw->gen < 8)
 118          break;
 119       /* fallthrough */
 120    case BRW_OPCODE_DP2:
 121    case BRW_OPCODE_DP3:
 122    case BRW_OPCODE_DP4:
 123    case BRW_OPCODE_DPH:
 124    case BRW_OPCODE_BFI1:
 125    case BRW_OPCODE_ASR:
 126    case BRW_OPCODE_SHL:
 127    case BRW_OPCODE_SHR:
 128    case BRW_OPCODE_SUBB:
 129       if (arg == 1) {
 130          inst->src[arg] = value;
 131          return true;
 132       }
 133       break;
 134
 135    case BRW_OPCODE_MACH:
 136    case BRW_OPCODE_MUL:
 137    case BRW_OPCODE_ADD:
 138    case BRW_OPCODE_OR:
 139    case BRW_OPCODE_AND:
 140    case BRW_OPCODE_XOR:
 141    case BRW_OPCODE_ADDC:
 142       if (arg == 1) {
 143          inst->src[arg] = value;
 144          return true;
 145       } else if (arg == 0 && inst->src[1].file != IMM) {
 146          /* Fit this constant in by commuting the operands.  Exception: we
 147           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 148           */
 149          if ((inst->opcode == BRW_OPCODE_MUL ||
 150               inst->opcode == BRW_OPCODE_MACH) &&
 151              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 152               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 153             break;
 154          inst->src[0] = inst->src[1];
 155          inst->src[1] = value;
 156          return true;
 157       }
 158       break;
 159
 160    case BRW_OPCODE_CMP:
 161       if (arg == 1) {
 162          inst->src[arg] = value;
 163          return true;
 164       } else if (arg == 0 && inst->src[1].file != IMM) {
 165          enum brw_conditional_mod new_cmod;
 166
 167          new_cmod = brw_swap_cmod(inst->conditional_mod);
 168          if (new_cmod != BRW_CONDITIONAL_NONE) {
 169             /* Fit this constant in by swapping the operands and
 170              * flipping the test.
 171              */
 172             inst->src[0] = inst->src[1];
 173             inst->src[1] = value;
 174             inst->conditional_mod = new_cmod;
 175             return true;
 176          }
 177       }
 178       break;
 179
 180    case BRW_OPCODE_SEL:
 181       if (arg == 1) {
 182          inst->src[arg] = value;
 183          return true;
 184       } else if (arg == 0 && inst->src[1].file != IMM) {
 185          inst->src[0] = inst->src[1];
 186          inst->src[1] = value;
 187
 188          /* If this was predicated, flipping operands means
 189           * we also need to flip the predicate.
 190           */
 191          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 192             inst->predicate_inverse = !inst->predicate_inverse;
 193          }
 194          return true;
 195       }
 196       break;
 197
 198    default:
 199       break;
 200    }
 201
 202    return false;
 203 }
 204
 205 static bool
 206 is_logic_op(enum opcode opcode)
 207 {
 208    return (opcode == BRW_OPCODE_AND ||
 209            opcode == BRW_OPCODE_OR  ||
 210            opcode == BRW_OPCODE_XOR ||
 211            opcode == BRW_OPCODE_NOT);
 212 }
 213
 214 static bool
 215 try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
 216                    int arg, src_reg *values[4])
 217 {
 218    /* For constant propagation, we only handle the same constant
 219     * across all 4 channels.  Some day, we should handle the 8-bit
 220     * float vector format, which would let us constant propagate
 221     * vectors better.
 222     */
 223    src_reg value = *values[0];
 224    for (int i = 1; i < 4; i++) {
 225       /* This is equals() except we don't care about the swizzle. */
 226       if (value.file != values[i]->file ||
 227           value.reg != values[i]->reg ||
 228           value.reg_offset != values[i]->reg_offset ||
 229           value.type != values[i]->type ||
 230           value.negate != values[i]->negate ||
 231           value.abs != values[i]->abs) {
 232          return false;
 233       }
 234    }
 235
 236    /* Compute the swizzle of the original register by swizzling the
 237     * component loaded from each value according to the swizzle of
 238     * operand we're going to change.
 239     */
 240    int s[4];
 241    for (int i = 0; i < 4; i++) {
 242       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 243                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 244    }
 245    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 246
 247    if (value.file != UNIFORM &&
 248        value.file != GRF &&
 249        value.file != ATTR)
 250       return false;
 251
 252    if (brw->gen >= 8 && (value.negate || value.abs) &&
 253        is_logic_op(inst->opcode)) {
 254       return false;
 255    }
 256
 257    if (inst->src[arg].abs) {
 258       value.negate = false;
 259       value.abs = true;
 260    }
 261    if (inst->src[arg].negate)
 262       value.negate = !value.negate;
 263
 264    bool has_source_modifiers = value.negate || value.abs;
 265
 266    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 267     * instructions.
 268     */
 269    if ((has_source_modifiers || value.file == UNIFORM ||
 270         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
 271       return false;
 272
 273    if (has_source_modifiers && value.type != inst->src[arg].type)
 274       return false;
 275
 276    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 277                         inst->opcode == BRW_OPCODE_MAD ||
 278                         inst->opcode == BRW_OPCODE_BFE ||
 279                         inst->opcode == BRW_OPCODE_BFI2);
 280    if (is_3src_inst && value.file == UNIFORM)
 281       return false;
 282
 283    if (inst->is_send_from_grf())
 284       return false;
 285
 286    /* We can't copy-propagate a UD negation into a condmod
 287     * instruction, because the condmod ends up looking at the 33-bit
 288     * signed accumulator value instead of the 32-bit value we wanted
 289     */
 290    if (inst->conditional_mod &&
 291        value.negate &&
 292        value.type == BRW_REGISTER_TYPE_UD)
 293       return false;
 294
 295    /* Don't report progress if this is a noop. */
 296    if (value.equals(inst->src[arg]))
 297       return false;
 298
 299    value.type = inst->src[arg].type;
 300    inst->src[arg] = value;
 301    return true;
 302 }
 303
 304 bool
 305 vec4_visitor::opt_copy_propagation()
 306 {
 307    bool progress = false;
 308    src_reg *cur_value[virtual_grf_reg_count][4];
 309
 310    memset(&cur_value, 0, sizeof(cur_value));
 311
 312    foreach_in_list(vec4_instruction, inst, &instructions) {
 313       /* This pass only works on basic blocks.  If there's flow
 314        * control, throw out all our information and start from
 315        * scratch.
 316        *
 317        * This should really be fixed by using a structure like in
 318        * src/glsl/opt_copy_propagation.cpp to track available copies.
 319        */
 320       if (!is_dominated_by_previous_instruction(inst)) {
 321          memset(cur_value, 0, sizeof(cur_value));
 322          continue;
 323       }
 324
 325       /* For each source arg, see if each component comes from a copy
 326        * from the same type file (IMM, GRF, UNIFORM), and try
 327        * optimizing out access to the copy result
 328        */
 329       for (int i = 2; i >= 0; i--) {
 330          /* Copied values end up in GRFs, and we don't track reladdr
 331           * accesses.
 332           */
 333          if (inst->src[i].file != GRF ||
 334              inst->src[i].reladdr)
 335             continue;
 336
 337          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 338                     inst->src[i].reg_offset);
 339
 340          /* Find the regs that each swizzle component came from.
 341           */
 342          src_reg *values[4];
 343          int c;
 344          for (c = 0; c < 4; c++) {
 345             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 346
 347             /* If there's no available copy for this channel, bail.
 348              * We could be more aggressive here -- some channels might
 349              * not get used based on the destination writemask.
 350              */
 351             if (!values[c])
 352                break;
 353
 354             /* We'll only be able to copy propagate if the sources are
 355              * all from the same file -- there's no ability to swizzle
 356              * 0 or 1 constants in with source registers like in i915.
 357              */
 358             if (c > 0 && values[c - 1]->file != values[c]->file)
 359                break;
 360          }
 361
 362          if (c != 4)
 363             continue;
 364
 365          if (try_constant_propagate(brw, inst, i, values))
 366             progress = true;
 367
 368          if (try_copy_propagate(brw, inst, i, values))
 369             progress = true;
 370       }
 371
 372       /* Track available source registers. */
 373       if (inst->dst.file == GRF) {
 374          const int reg =
 375             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 376
 377          /* Update our destination's current channel values.  For a direct copy,
 378           * the value is the newly propagated source.  Otherwise, we don't know
 379           * the new value, so clear it.
 380           */
 381          bool direct_copy = is_direct_copy(inst);
 382          for (int i = 0; i < 4; i++) {
 383             if (inst->dst.writemask & (1 << i)) {
 384                cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
 385             }
 386          }
 387
 388          /* Clear the records for any registers whose current value came from
 389           * our destination's updated channels, as the two are no longer equal.
 390           */
 391          if (inst->dst.reladdr)
 392             memset(cur_value, 0, sizeof(cur_value));
 393          else {
 394             for (int i = 0; i < virtual_grf_reg_count; i++) {
 395                for (int j = 0; j < 4; j++) {
 396                   if (is_channel_updated(inst, cur_value[i], j)){
 397                      cur_value[i][j] = NULL;
 398                   }
 399                }
 400             }
 401          }
 402       }
 403    }
 404
 405    if (progress)
 406       invalidate_live_intervals();
 407
 408    return progress;
 409 }
 410
 411 } /* namespace brw */