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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
35 #include "main/macros.h"
46 is_direct_copy(vec4_instruction
*inst
)
48 return (inst
->opcode
== BRW_OPCODE_MOV
&&
50 inst
->dst
.file
== GRF
&&
52 !inst
->src
[0].reladdr
&&
53 (inst
->dst
.type
== inst
->src
[0].type
||
54 (inst
->dst
.type
== BRW_REGISTER_TYPE_F
&&
55 inst
->src
[0].type
== BRW_REGISTER_TYPE_VF
)));
59 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
61 return (inst
->opcode
!= BRW_OPCODE_DO
&&
62 inst
->opcode
!= BRW_OPCODE_WHILE
&&
63 inst
->opcode
!= BRW_OPCODE_ELSE
&&
64 inst
->opcode
!= BRW_OPCODE_ENDIF
);
68 is_channel_updated(vec4_instruction
*inst
, src_reg
*values
[4], int ch
)
70 const src_reg
*src
= values
[ch
];
72 /* consider GRF only */
73 assert(inst
->dst
.file
== GRF
);
74 if (!src
|| src
->file
!= GRF
)
77 return (src
->in_range(inst
->dst
, inst
->regs_written
) &&
78 inst
->dst
.writemask
& (1 << BRW_GET_SWZ(src
->swizzle
, ch
)));
82 swizzle_vf_imm(unsigned vf4
, unsigned swizzle
)
89 ret
.vf
[0] = v
.vf
[BRW_GET_SWZ(swizzle
, 0)];
90 ret
.vf
[1] = v
.vf
[BRW_GET_SWZ(swizzle
, 1)];
91 ret
.vf
[2] = v
.vf
[BRW_GET_SWZ(swizzle
, 2)];
92 ret
.vf
[3] = v
.vf
[BRW_GET_SWZ(swizzle
, 3)];
98 is_logic_op(enum opcode opcode
)
100 return (opcode
== BRW_OPCODE_AND
||
101 opcode
== BRW_OPCODE_OR
||
102 opcode
== BRW_OPCODE_XOR
||
103 opcode
== BRW_OPCODE_NOT
);
107 try_constant_propagate(const struct brw_device_info
*devinfo
,
108 vec4_instruction
*inst
,
109 int arg
, struct copy_entry
*entry
)
111 /* For constant propagation, we only handle the same constant
112 * across all 4 channels. Some day, we should handle the 8-bit
113 * float vector format, which would let us constant propagate
116 src_reg value
= *entry
->value
[0];
117 for (int i
= 1; i
< 4; i
++) {
118 if (!value
.equals(*entry
->value
[i
]))
122 if (value
.file
!= IMM
)
125 if (value
.type
== BRW_REGISTER_TYPE_VF
) {
126 /* The result of bit-casting the component values of a vector float
127 * cannot in general be represented as an immediate.
129 if (inst
->src
[arg
].type
!= BRW_REGISTER_TYPE_F
)
132 value
.type
= inst
->src
[arg
].type
;
135 if (inst
->src
[arg
].abs
) {
136 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
137 !brw_abs_immediate(value
.type
, &value
.fixed_hw_reg
)) {
142 if (inst
->src
[arg
].negate
) {
143 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
144 !brw_negate_immediate(value
.type
, &value
.fixed_hw_reg
)) {
149 if (value
.type
== BRW_REGISTER_TYPE_VF
)
150 value
.fixed_hw_reg
.dw1
.ud
= swizzle_vf_imm(value
.fixed_hw_reg
.dw1
.ud
,
151 inst
->src
[arg
].swizzle
);
153 switch (inst
->opcode
) {
155 case SHADER_OPCODE_BROADCAST
:
156 inst
->src
[arg
] = value
;
159 case SHADER_OPCODE_POW
:
160 case SHADER_OPCODE_INT_QUOTIENT
:
161 case SHADER_OPCODE_INT_REMAINDER
:
162 if (devinfo
->gen
< 8)
169 case BRW_OPCODE_BFI1
:
173 case BRW_OPCODE_SUBB
:
175 inst
->src
[arg
] = value
;
180 case BRW_OPCODE_MACH
:
186 case BRW_OPCODE_ADDC
:
188 inst
->src
[arg
] = value
;
190 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
191 /* Fit this constant in by commuting the operands. Exception: we
192 * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
194 if ((inst
->opcode
== BRW_OPCODE_MUL
||
195 inst
->opcode
== BRW_OPCODE_MACH
) &&
196 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
197 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
199 inst
->src
[0] = inst
->src
[1];
200 inst
->src
[1] = value
;
207 inst
->src
[arg
] = value
;
209 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
210 enum brw_conditional_mod new_cmod
;
212 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
213 if (new_cmod
!= BRW_CONDITIONAL_NONE
) {
214 /* Fit this constant in by swapping the operands and
217 inst
->src
[0] = inst
->src
[1];
218 inst
->src
[1] = value
;
219 inst
->conditional_mod
= new_cmod
;
227 inst
->src
[arg
] = value
;
229 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
230 inst
->src
[0] = inst
->src
[1];
231 inst
->src
[1] = value
;
233 /* If this was predicated, flipping operands means
234 * we also need to flip the predicate.
236 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
237 inst
->predicate_inverse
= !inst
->predicate_inverse
;
251 try_copy_propagate(const struct brw_device_info
*devinfo
,
252 vec4_instruction
*inst
,
253 int arg
, struct copy_entry
*entry
)
255 /* For constant propagation, we only handle the same constant
256 * across all 4 channels. Some day, we should handle the 8-bit
257 * float vector format, which would let us constant propagate
260 src_reg value
= *entry
->value
[0];
261 for (int i
= 1; i
< 4; i
++) {
262 /* This is equals() except we don't care about the swizzle. */
263 if (value
.file
!= entry
->value
[i
]->file
||
264 value
.reg
!= entry
->value
[i
]->reg
||
265 value
.reg_offset
!= entry
->value
[i
]->reg_offset
||
266 value
.type
!= entry
->value
[i
]->type
||
267 value
.negate
!= entry
->value
[i
]->negate
||
268 value
.abs
!= entry
->value
[i
]->abs
) {
273 /* Compute the swizzle of the original register by swizzling the
274 * component loaded from each value according to the swizzle of
275 * operand we're going to change.
278 for (int i
= 0; i
< 4; i
++) {
279 s
[i
] = BRW_GET_SWZ(entry
->value
[i
]->swizzle
, i
);
281 value
.swizzle
= brw_compose_swizzle(inst
->src
[arg
].swizzle
,
282 BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]));
284 if (value
.file
!= UNIFORM
&&
289 if (devinfo
->gen
>= 8 && (value
.negate
|| value
.abs
) &&
290 is_logic_op(inst
->opcode
)) {
294 if (inst
->src
[arg
].abs
) {
295 value
.negate
= false;
298 if (inst
->src
[arg
].negate
)
299 value
.negate
= !value
.negate
;
301 bool has_source_modifiers
= value
.negate
|| value
.abs
;
303 /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
306 if ((has_source_modifiers
|| value
.file
== UNIFORM
||
307 value
.swizzle
!= BRW_SWIZZLE_XYZW
) && !inst
->can_do_source_mods(devinfo
))
310 if (has_source_modifiers
&& value
.type
!= inst
->src
[arg
].type
)
313 if (has_source_modifiers
&&
314 inst
->opcode
== SHADER_OPCODE_GEN4_SCRATCH_WRITE
)
317 if (inst
->is_3src() && value
.file
== UNIFORM
)
320 if (inst
->is_send_from_grf())
323 /* we can't generally copy-propagate UD negations becuse we
324 * end up accessing the resulting values as signed integers
325 * instead. See also resolve_ud_negate().
328 value
.type
== BRW_REGISTER_TYPE_UD
)
331 /* Don't report progress if this is a noop. */
332 if (value
.equals(inst
->src
[arg
]))
335 const unsigned dst_saturate_mask
= inst
->dst
.writemask
&
336 brw_apply_swizzle_to_mask(inst
->src
[arg
].swizzle
, entry
->saturatemask
);
338 if (dst_saturate_mask
) {
339 /* We either saturate all or nothing. */
340 if (dst_saturate_mask
!= inst
->dst
.writemask
)
343 /* Limit saturate propagation only to SEL with src1 bounded within 0.0
344 * and 1.0, otherwise skip copy propagate altogether.
346 switch(inst
->opcode
) {
349 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
350 inst
->src
[1].file
!= IMM
||
351 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
352 inst
->src
[1].fixed_hw_reg
.dw1
.f
< 0.0 ||
353 inst
->src
[1].fixed_hw_reg
.dw1
.f
> 1.0) {
357 inst
->saturate
= true;
364 value
.type
= inst
->src
[arg
].type
;
365 inst
->src
[arg
] = value
;
370 vec4_visitor::opt_copy_propagation(bool do_constant_prop
)
372 bool progress
= false;
373 struct copy_entry entries
[alloc
.total_size
];
375 memset(&entries
, 0, sizeof(entries
));
377 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
378 /* This pass only works on basic blocks. If there's flow
379 * control, throw out all our information and start from
382 * This should really be fixed by using a structure like in
383 * src/glsl/opt_copy_propagation.cpp to track available copies.
385 if (!is_dominated_by_previous_instruction(inst
)) {
386 memset(&entries
, 0, sizeof(entries
));
390 /* For each source arg, see if each component comes from a copy
391 * from the same type file (IMM, GRF, UNIFORM), and try
392 * optimizing out access to the copy result
394 for (int i
= 2; i
>= 0; i
--) {
395 /* Copied values end up in GRFs, and we don't track reladdr
398 if (inst
->src
[i
].file
!= GRF
||
399 inst
->src
[i
].reladdr
)
402 /* We only handle single-register copies. */
403 if (inst
->regs_read(i
) != 1)
406 int reg
= (alloc
.offsets
[inst
->src
[i
].reg
] +
407 inst
->src
[i
].reg_offset
);
409 /* Find the regs that each swizzle component came from.
411 struct copy_entry entry
;
412 memset(&entry
, 0, sizeof(copy_entry
));
414 for (c
= 0; c
< 4; c
++) {
415 int channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
);
416 entry
.value
[c
] = entries
[reg
].value
[channel
];
418 /* If there's no available copy for this channel, bail.
419 * We could be more aggressive here -- some channels might
420 * not get used based on the destination writemask.
425 entry
.saturatemask
|=
426 (entries
[reg
].saturatemask
& (1 << channel
) ? 1 : 0) << c
;
428 /* We'll only be able to copy propagate if the sources are
429 * all from the same file -- there's no ability to swizzle
430 * 0 or 1 constants in with source registers like in i915.
432 if (c
> 0 && entry
.value
[c
- 1]->file
!= entry
.value
[c
]->file
)
439 if (do_constant_prop
&& try_constant_propagate(devinfo
, inst
, i
, &entry
))
442 if (try_copy_propagate(devinfo
, inst
, i
, &entry
))
446 /* Track available source registers. */
447 if (inst
->dst
.file
== GRF
) {
449 alloc
.offsets
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
451 /* Update our destination's current channel values. For a direct copy,
452 * the value is the newly propagated source. Otherwise, we don't know
453 * the new value, so clear it.
455 bool direct_copy
= is_direct_copy(inst
);
456 entries
[reg
].saturatemask
&= ~inst
->dst
.writemask
;
457 for (int i
= 0; i
< 4; i
++) {
458 if (inst
->dst
.writemask
& (1 << i
)) {
459 entries
[reg
].value
[i
] = direct_copy
? &inst
->src
[0] : NULL
;
460 entries
[reg
].saturatemask
|=
461 inst
->saturate
&& direct_copy
? 1 << i
: 0;
465 /* Clear the records for any registers whose current value came from
466 * our destination's updated channels, as the two are no longer equal.
468 if (inst
->dst
.reladdr
)
469 memset(&entries
, 0, sizeof(entries
));
471 for (unsigned i
= 0; i
< alloc
.total_size
; i
++) {
472 for (int j
= 0; j
< 4; j
++) {
473 if (is_channel_updated(inst
, entries
[i
].value
, j
)) {
474 entries
[i
].value
[j
] = NULL
;
475 entries
[i
].saturatemask
&= ~(1 << j
);
484 invalidate_live_intervals();
489 } /* namespace brw */