src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 #include "brw_cfg.h"
  34 extern "C" {
  35 #include "main/macros.h"
  36 }
  37
  38 namespace brw {
  39
  40 struct copy_entry {
  41    src_reg *value[4];
  42    int saturatemask;
  43 };
  44
  45 static bool
  46 is_direct_copy(vec4_instruction *inst)
  47 {
  48    return (inst->opcode == BRW_OPCODE_MOV &&
  49            !inst->predicate &&
  50            inst->dst.file == GRF &&
  51            !inst->dst.reladdr &&
  52            !inst->src[0].reladdr &&
  53            (inst->dst.type == inst->src[0].type ||
  54             (inst->dst.type == BRW_REGISTER_TYPE_F &&
  55              inst->src[0].type == BRW_REGISTER_TYPE_VF)));
  56 }
  57
  58 static bool
  59 is_dominated_by_previous_instruction(vec4_instruction *inst)
  60 {
  61    return (inst->opcode != BRW_OPCODE_DO &&
  62            inst->opcode != BRW_OPCODE_WHILE &&
  63            inst->opcode != BRW_OPCODE_ELSE &&
  64            inst->opcode != BRW_OPCODE_ENDIF);
  65 }
  66
  67 static bool
  68 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  69 {
  70    const src_reg *src = values[ch];
  71
  72    /* consider GRF only */
  73    assert(inst->dst.file == GRF);
  74    if (!src || src->file != GRF)
  75       return false;
  76
  77    return (src->in_range(inst->dst, inst->regs_written) &&
  78            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  79 }
  80
  81 static unsigned
  82 swizzle_vf_imm(unsigned vf4, unsigned swizzle)
  83 {
  84    union {
  85       unsigned vf4;
  86       uint8_t vf[4];
  87    } v = { vf4 }, ret;
  88
  89    ret.vf[0] = v.vf[BRW_GET_SWZ(swizzle, 0)];
  90    ret.vf[1] = v.vf[BRW_GET_SWZ(swizzle, 1)];
  91    ret.vf[2] = v.vf[BRW_GET_SWZ(swizzle, 2)];
  92    ret.vf[3] = v.vf[BRW_GET_SWZ(swizzle, 3)];
  93
  94    return ret.vf4;
  95 }
  96
  97 static bool
  98 is_logic_op(enum opcode opcode)
  99 {
 100    return (opcode == BRW_OPCODE_AND ||
 101            opcode == BRW_OPCODE_OR  ||
 102            opcode == BRW_OPCODE_XOR ||
 103            opcode == BRW_OPCODE_NOT);
 104 }
 105
 106 static bool
 107 try_constant_propagate(const struct brw_device_info *devinfo,
 108                        vec4_instruction *inst,
 109                        int arg, struct copy_entry *entry)
 110 {
 111    /* For constant propagation, we only handle the same constant
 112     * across all 4 channels.  Some day, we should handle the 8-bit
 113     * float vector format, which would let us constant propagate
 114     * vectors better.
 115     */
 116    src_reg value = *entry->value[0];
 117    for (int i = 1; i < 4; i++) {
 118       if (!value.equals(*entry->value[i]))
 119          return false;
 120    }
 121
 122    if (value.file != IMM)
 123       return false;
 124
 125    if (value.type == BRW_REGISTER_TYPE_VF) {
 126       /* The result of bit-casting the component values of a vector float
 127        * cannot in general be represented as an immediate.
 128        */
 129       if (inst->src[arg].type != BRW_REGISTER_TYPE_F)
 130          return false;
 131    } else {
 132       value.type = inst->src[arg].type;
 133    }
 134
 135    if (inst->src[arg].abs) {
 136       if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
 137           !brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
 138          return false;
 139       }
 140    }
 141
 142    if (inst->src[arg].negate) {
 143       if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
 144           !brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
 145          return false;
 146       }
 147    }
 148
 149    if (value.type == BRW_REGISTER_TYPE_VF)
 150       value.fixed_hw_reg.dw1.ud = swizzle_vf_imm(value.fixed_hw_reg.dw1.ud,
 151                                                  inst->src[arg].swizzle);
 152
 153    switch (inst->opcode) {
 154    case BRW_OPCODE_MOV:
 155    case SHADER_OPCODE_BROADCAST:
 156       inst->src[arg] = value;
 157       return true;
 158
 159    case SHADER_OPCODE_POW:
 160    case SHADER_OPCODE_INT_QUOTIENT:
 161    case SHADER_OPCODE_INT_REMAINDER:
 162       if (devinfo->gen < 8)
 163          break;
 164       /* fallthrough */
 165    case BRW_OPCODE_DP2:
 166    case BRW_OPCODE_DP3:
 167    case BRW_OPCODE_DP4:
 168    case BRW_OPCODE_DPH:
 169    case BRW_OPCODE_BFI1:
 170    case BRW_OPCODE_ASR:
 171    case BRW_OPCODE_SHL:
 172    case BRW_OPCODE_SHR:
 173    case BRW_OPCODE_SUBB:
 174       if (arg == 1) {
 175          inst->src[arg] = value;
 176          return true;
 177       }
 178       break;
 179
 180    case BRW_OPCODE_MACH:
 181    case BRW_OPCODE_MUL:
 182    case SHADER_OPCODE_MULH:
 183    case BRW_OPCODE_ADD:
 184    case BRW_OPCODE_OR:
 185    case BRW_OPCODE_AND:
 186    case BRW_OPCODE_XOR:
 187    case BRW_OPCODE_ADDC:
 188       if (arg == 1) {
 189          inst->src[arg] = value;
 190          return true;
 191       } else if (arg == 0 && inst->src[1].file != IMM) {
 192          /* Fit this constant in by commuting the operands.  Exception: we
 193           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 194           */
 195          if ((inst->opcode == BRW_OPCODE_MUL ||
 196               inst->opcode == BRW_OPCODE_MACH) &&
 197              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 198               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 199             break;
 200          inst->src[0] = inst->src[1];
 201          inst->src[1] = value;
 202          return true;
 203       }
 204       break;
 205
 206    case BRW_OPCODE_CMP:
 207       if (arg == 1) {
 208          inst->src[arg] = value;
 209          return true;
 210       } else if (arg == 0 && inst->src[1].file != IMM) {
 211          enum brw_conditional_mod new_cmod;
 212
 213          new_cmod = brw_swap_cmod(inst->conditional_mod);
 214          if (new_cmod != BRW_CONDITIONAL_NONE) {
 215             /* Fit this constant in by swapping the operands and
 216              * flipping the test.
 217              */
 218             inst->src[0] = inst->src[1];
 219             inst->src[1] = value;
 220             inst->conditional_mod = new_cmod;
 221             return true;
 222          }
 223       }
 224       break;
 225
 226    case BRW_OPCODE_SEL:
 227       if (arg == 1) {
 228          inst->src[arg] = value;
 229          return true;
 230       } else if (arg == 0 && inst->src[1].file != IMM) {
 231          inst->src[0] = inst->src[1];
 232          inst->src[1] = value;
 233
 234          /* If this was predicated, flipping operands means
 235           * we also need to flip the predicate.
 236           */
 237          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 238             inst->predicate_inverse = !inst->predicate_inverse;
 239          }
 240          return true;
 241       }
 242       break;
 243
 244    default:
 245       break;
 246    }
 247
 248    return false;
 249 }
 250
 251 static bool
 252 try_copy_propagate(const struct brw_device_info *devinfo,
 253                    vec4_instruction *inst,
 254                    int arg, struct copy_entry *entry)
 255 {
 256    /* For constant propagation, we only handle the same constant
 257     * across all 4 channels.  Some day, we should handle the 8-bit
 258     * float vector format, which would let us constant propagate
 259     * vectors better.
 260     */
 261    src_reg value = *entry->value[0];
 262    for (int i = 1; i < 4; i++) {
 263       /* This is equals() except we don't care about the swizzle. */
 264       if (value.file != entry->value[i]->file ||
 265           value.reg != entry->value[i]->reg ||
 266           value.reg_offset != entry->value[i]->reg_offset ||
 267           value.type != entry->value[i]->type ||
 268           value.negate != entry->value[i]->negate ||
 269           value.abs != entry->value[i]->abs) {
 270          return false;
 271       }
 272    }
 273
 274    /* Compute the swizzle of the original register by swizzling the
 275     * component loaded from each value according to the swizzle of
 276     * operand we're going to change.
 277     */
 278    int s[4];
 279    for (int i = 0; i < 4; i++) {
 280       s[i] = BRW_GET_SWZ(entry->value[i]->swizzle, i);
 281    }
 282    value.swizzle = brw_compose_swizzle(inst->src[arg].swizzle,
 283                                        BRW_SWIZZLE4(s[0], s[1], s[2], s[3]));
 284
 285    if (value.file != UNIFORM &&
 286        value.file != GRF &&
 287        value.file != ATTR)
 288       return false;
 289
 290    if (devinfo->gen >= 8 && (value.negate || value.abs) &&
 291        is_logic_op(inst->opcode)) {
 292       return false;
 293    }
 294
 295    if (inst->src[arg].abs) {
 296       value.negate = false;
 297       value.abs = true;
 298    }
 299    if (inst->src[arg].negate)
 300       value.negate = !value.negate;
 301
 302    bool has_source_modifiers = value.negate || value.abs;
 303
 304    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 305     * instructions.
 306     */
 307    if ((has_source_modifiers || value.file == UNIFORM ||
 308         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(devinfo))
 309       return false;
 310
 311    if (has_source_modifiers && value.type != inst->src[arg].type)
 312       return false;
 313
 314    if (has_source_modifiers &&
 315        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
 316       return false;
 317
 318    if (inst->is_3src() && value.file == UNIFORM)
 319       return false;
 320
 321    if (inst->is_send_from_grf())
 322       return false;
 323
 324    /* we can't generally copy-propagate UD negations becuse we
 325     * end up accessing the resulting values as signed integers
 326     * instead. See also resolve_ud_negate().
 327     */
 328    if (value.negate &&
 329        value.type == BRW_REGISTER_TYPE_UD)
 330       return false;
 331
 332    /* Don't report progress if this is a noop. */
 333    if (value.equals(inst->src[arg]))
 334       return false;
 335
 336    const unsigned dst_saturate_mask = inst->dst.writemask &
 337       brw_apply_swizzle_to_mask(inst->src[arg].swizzle, entry->saturatemask);
 338
 339    if (dst_saturate_mask) {
 340       /* We either saturate all or nothing. */
 341       if (dst_saturate_mask != inst->dst.writemask)
 342          return false;
 343
 344       /* Limit saturate propagation only to SEL with src1 bounded within 0.0
 345        * and 1.0, otherwise skip copy propagate altogether.
 346        */
 347       switch(inst->opcode) {
 348       case BRW_OPCODE_SEL:
 349          if (arg != 0 ||
 350              inst->src[0].type != BRW_REGISTER_TYPE_F ||
 351              inst->src[1].file != IMM ||
 352              inst->src[1].type != BRW_REGISTER_TYPE_F ||
 353              inst->src[1].fixed_hw_reg.dw1.f < 0.0 ||
 354              inst->src[1].fixed_hw_reg.dw1.f > 1.0) {
 355             return false;
 356          }
 357          if (!inst->saturate)
 358             inst->saturate = true;
 359          break;
 360       default:
 361          return false;
 362       }
 363    }
 364
 365    value.type = inst->src[arg].type;
 366    inst->src[arg] = value;
 367    return true;
 368 }
 369
 370 bool
 371 vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 372 {
 373    bool progress = false;
 374    struct copy_entry entries[alloc.total_size];
 375
 376    memset(&entries, 0, sizeof(entries));
 377
 378    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 379       /* This pass only works on basic blocks.  If there's flow
 380        * control, throw out all our information and start from
 381        * scratch.
 382        *
 383        * This should really be fixed by using a structure like in
 384        * src/glsl/opt_copy_propagation.cpp to track available copies.
 385        */
 386       if (!is_dominated_by_previous_instruction(inst)) {
 387          memset(&entries, 0, sizeof(entries));
 388          continue;
 389       }
 390
 391       /* For each source arg, see if each component comes from a copy
 392        * from the same type file (IMM, GRF, UNIFORM), and try
 393        * optimizing out access to the copy result
 394        */
 395       for (int i = 2; i >= 0; i--) {
 396          /* Copied values end up in GRFs, and we don't track reladdr
 397           * accesses.
 398           */
 399          if (inst->src[i].file != GRF ||
 400              inst->src[i].reladdr)
 401             continue;
 402
 403          /* We only handle single-register copies. */
 404          if (inst->regs_read(i) != 1)
 405             continue;
 406
 407          int reg = (alloc.offsets[inst->src[i].reg] +
 408                     inst->src[i].reg_offset);
 409
 410          /* Find the regs that each swizzle component came from.
 411           */
 412          struct copy_entry entry;
 413          memset(&entry, 0, sizeof(copy_entry));
 414          int c;
 415          for (c = 0; c < 4; c++) {
 416             int channel = BRW_GET_SWZ(inst->src[i].swizzle, c);
 417             entry.value[c] = entries[reg].value[channel];
 418
 419             /* If there's no available copy for this channel, bail.
 420              * We could be more aggressive here -- some channels might
 421              * not get used based on the destination writemask.
 422              */
 423             if (!entry.value[c])
 424                break;
 425
 426             entry.saturatemask |=
 427                (entries[reg].saturatemask & (1 << channel) ? 1 : 0) << c;
 428
 429             /* We'll only be able to copy propagate if the sources are
 430              * all from the same file -- there's no ability to swizzle
 431              * 0 or 1 constants in with source registers like in i915.
 432              */
 433             if (c > 0 && entry.value[c - 1]->file != entry.value[c]->file)
 434                break;
 435          }
 436
 437          if (c != 4)
 438             continue;
 439
 440          if (do_constant_prop && try_constant_propagate(devinfo, inst, i, &entry))
 441             progress = true;
 442
 443          if (try_copy_propagate(devinfo, inst, i, &entry))
 444             progress = true;
 445       }
 446
 447       /* Track available source registers. */
 448       if (inst->dst.file == GRF) {
 449          const int reg =
 450             alloc.offsets[inst->dst.reg] + inst->dst.reg_offset;
 451
 452          /* Update our destination's current channel values.  For a direct copy,
 453           * the value is the newly propagated source.  Otherwise, we don't know
 454           * the new value, so clear it.
 455           */
 456          bool direct_copy = is_direct_copy(inst);
 457          entries[reg].saturatemask &= ~inst->dst.writemask;
 458          for (int i = 0; i < 4; i++) {
 459             if (inst->dst.writemask & (1 << i)) {
 460                entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
 461                entries[reg].saturatemask |=
 462                   inst->saturate && direct_copy ? 1 << i : 0;
 463             }
 464          }
 465
 466          /* Clear the records for any registers whose current value came from
 467           * our destination's updated channels, as the two are no longer equal.
 468           */
 469          if (inst->dst.reladdr)
 470             memset(&entries, 0, sizeof(entries));
 471          else {
 472             for (unsigned i = 0; i < alloc.total_size; i++) {
 473                for (int j = 0; j < 4; j++) {
 474                   if (is_channel_updated(inst, entries[i].value, j)) {
 475                      entries[i].value[j] = NULL;
 476                      entries[i].saturatemask &= ~(1 << j);
 477                   }
 478                }
 479             }
 480          }
 481       }
 482    }
 483
 484    if (progress)
 485       invalidate_live_intervals();
 486
 487    return progress;
 488 }
 489
 490 } /* namespace brw */