src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 #include "brw_cfg.h"
  34 #include "brw_eu.h"
  35
  36 namespace brw {
  37
  38 struct copy_entry {
  39    src_reg *value[4];
  40    int saturatemask;
  41 };
  42
  43 static bool
  44 is_direct_copy(vec4_instruction *inst)
  45 {
  46    return (inst->opcode == BRW_OPCODE_MOV &&
  47            !inst->predicate &&
  48            inst->dst.file == VGRF &&
  49            !inst->dst.reladdr &&
  50            !inst->src[0].reladdr &&
  51            (inst->dst.type == inst->src[0].type ||
  52             (inst->dst.type == BRW_REGISTER_TYPE_F &&
  53              inst->src[0].type == BRW_REGISTER_TYPE_VF)));
  54 }
  55
  56 static bool
  57 is_dominated_by_previous_instruction(vec4_instruction *inst)
  58 {
  59    return (inst->opcode != BRW_OPCODE_DO &&
  60            inst->opcode != BRW_OPCODE_WHILE &&
  61            inst->opcode != BRW_OPCODE_ELSE &&
  62            inst->opcode != BRW_OPCODE_ENDIF);
  63 }
  64
  65 static bool
  66 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  67 {
  68    const src_reg *src = values[ch];
  69
  70    /* consider GRF only */
  71    assert(inst->dst.file == VGRF);
  72    if (!src || src->file != VGRF)
  73       return false;
  74
  75    return (src->in_range(inst->dst, inst->regs_written) &&
  76            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  77 }
  78
  79 static bool
  80 is_logic_op(enum opcode opcode)
  81 {
  82    return (opcode == BRW_OPCODE_AND ||
  83            opcode == BRW_OPCODE_OR  ||
  84            opcode == BRW_OPCODE_XOR ||
  85            opcode == BRW_OPCODE_NOT);
  86 }
  87
  88 /**
  89  * Get the origin of a copy as a single register if all components present in
  90  * the given readmask originate from the same register and have compatible
  91  * regions, otherwise return a BAD_FILE register.
  92  */
  93 static src_reg
  94 get_copy_value(const copy_entry &entry, unsigned readmask)
  95 {
  96    unsigned swz[4] = {};
  97    src_reg value;
  98
  99    for (unsigned i = 0; i < 4; i++) {
 100       if (readmask & (1 << i)) {
 101          if (entry.value[i]) {
 102             src_reg src = *entry.value[i];
 103
 104             if (src.file == IMM) {
 105                swz[i] = i;
 106             } else {
 107                swz[i] = BRW_GET_SWZ(src.swizzle, i);
 108                /* Overwrite the original swizzle so the src_reg::equals call
 109                 * below doesn't care about it, the correct swizzle will be
 110                 * calculated once the swizzles of all components are known.
 111                 */
 112                src.swizzle = BRW_SWIZZLE_XYZW;
 113             }
 114
 115             if (value.file == BAD_FILE) {
 116                value = src;
 117             } else if (!value.equals(src)) {
 118                return src_reg();
 119             }
 120          } else {
 121             return src_reg();
 122          }
 123       }
 124    }
 125
 126    return swizzle(value,
 127                   brw_compose_swizzle(brw_swizzle_for_mask(readmask),
 128                                       BRW_SWIZZLE4(swz[0], swz[1],
 129                                                    swz[2], swz[3])));
 130 }
 131
 132 static bool
 133 try_constant_propagate(const struct brw_device_info *devinfo,
 134                        vec4_instruction *inst,
 135                        int arg, const copy_entry *entry)
 136 {
 137    /* For constant propagation, we only handle the same constant
 138     * across all 4 channels.  Some day, we should handle the 8-bit
 139     * float vector format, which would let us constant propagate
 140     * vectors better.
 141     * We could be more aggressive here -- some channels might not get used
 142     * based on the destination writemask.
 143     */
 144    src_reg value =
 145       get_copy_value(*entry,
 146                      brw_apply_inv_swizzle_to_mask(inst->src[arg].swizzle,
 147                                                    WRITEMASK_XYZW));
 148
 149    if (value.file != IMM)
 150       return false;
 151
 152    if (value.type == BRW_REGISTER_TYPE_VF) {
 153       /* The result of bit-casting the component values of a vector float
 154        * cannot in general be represented as an immediate.
 155        */
 156       if (inst->src[arg].type != BRW_REGISTER_TYPE_F)
 157          return false;
 158    } else {
 159       value.type = inst->src[arg].type;
 160    }
 161
 162    if (inst->src[arg].abs) {
 163       if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
 164           !brw_abs_immediate(value.type, &value.as_brw_reg())) {
 165          return false;
 166       }
 167    }
 168
 169    if (inst->src[arg].negate) {
 170       if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
 171           !brw_negate_immediate(value.type, &value.as_brw_reg())) {
 172          return false;
 173       }
 174    }
 175
 176    value = swizzle(value, inst->src[arg].swizzle);
 177
 178    switch (inst->opcode) {
 179    case BRW_OPCODE_MOV:
 180    case SHADER_OPCODE_BROADCAST:
 181       inst->src[arg] = value;
 182       return true;
 183
 184    case SHADER_OPCODE_POW:
 185    case SHADER_OPCODE_INT_QUOTIENT:
 186    case SHADER_OPCODE_INT_REMAINDER:
 187       if (devinfo->gen < 8)
 188          break;
 189       /* fallthrough */
 190    case BRW_OPCODE_DP2:
 191    case BRW_OPCODE_DP3:
 192    case BRW_OPCODE_DP4:
 193    case BRW_OPCODE_DPH:
 194    case BRW_OPCODE_BFI1:
 195    case BRW_OPCODE_ASR:
 196    case BRW_OPCODE_SHL:
 197    case BRW_OPCODE_SHR:
 198    case BRW_OPCODE_SUBB:
 199       if (arg == 1) {
 200          inst->src[arg] = value;
 201          return true;
 202       }
 203       break;
 204
 205    case BRW_OPCODE_MACH:
 206    case BRW_OPCODE_MUL:
 207    case SHADER_OPCODE_MULH:
 208    case BRW_OPCODE_ADD:
 209    case BRW_OPCODE_OR:
 210    case BRW_OPCODE_AND:
 211    case BRW_OPCODE_XOR:
 212    case BRW_OPCODE_ADDC:
 213       if (arg == 1) {
 214          inst->src[arg] = value;
 215          return true;
 216       } else if (arg == 0 && inst->src[1].file != IMM) {
 217          /* Fit this constant in by commuting the operands.  Exception: we
 218           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 219           */
 220          if ((inst->opcode == BRW_OPCODE_MUL ||
 221               inst->opcode == BRW_OPCODE_MACH) &&
 222              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 223               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 224             break;
 225          inst->src[0] = inst->src[1];
 226          inst->src[1] = value;
 227          return true;
 228       }
 229       break;
 230    case GS_OPCODE_SET_WRITE_OFFSET:
 231       /* This is just a multiply by a constant with special strides.
 232        * The generator will handle immediates in both arguments (generating
 233        * a single MOV of the product).  So feel free to propagate in src0.
 234        */
 235       inst->src[arg] = value;
 236       return true;
 237
 238    case BRW_OPCODE_CMP:
 239       if (arg == 1) {
 240          inst->src[arg] = value;
 241          return true;
 242       } else if (arg == 0 && inst->src[1].file != IMM) {
 243          enum brw_conditional_mod new_cmod;
 244
 245          new_cmod = brw_swap_cmod(inst->conditional_mod);
 246          if (new_cmod != BRW_CONDITIONAL_NONE) {
 247             /* Fit this constant in by swapping the operands and
 248              * flipping the test.
 249              */
 250             inst->src[0] = inst->src[1];
 251             inst->src[1] = value;
 252             inst->conditional_mod = new_cmod;
 253             return true;
 254          }
 255       }
 256       break;
 257
 258    case BRW_OPCODE_SEL:
 259       if (arg == 1) {
 260          inst->src[arg] = value;
 261          return true;
 262       } else if (arg == 0 && inst->src[1].file != IMM) {
 263          inst->src[0] = inst->src[1];
 264          inst->src[1] = value;
 265
 266          /* If this was predicated, flipping operands means
 267           * we also need to flip the predicate.
 268           */
 269          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 270             inst->predicate_inverse = !inst->predicate_inverse;
 271          }
 272          return true;
 273       }
 274       break;
 275
 276    default:
 277       break;
 278    }
 279
 280    return false;
 281 }
 282
 283 static bool
 284 try_copy_propagate(const struct brw_device_info *devinfo,
 285                    vec4_instruction *inst, int arg,
 286                    const copy_entry *entry, int attributes_per_reg)
 287 {
 288    /* Build up the value we are propagating as if it were the source of a
 289     * single MOV
 290     */
 291    src_reg value =
 292       get_copy_value(*entry,
 293                      brw_apply_inv_swizzle_to_mask(inst->src[arg].swizzle,
 294                                                    WRITEMASK_XYZW));
 295
 296    /* Check that we can propagate that value */
 297    if (value.file != UNIFORM &&
 298        value.file != VGRF &&
 299        value.file != ATTR)
 300       return false;
 301
 302    if (devinfo->gen >= 8 && (value.negate || value.abs) &&
 303        is_logic_op(inst->opcode)) {
 304       return false;
 305    }
 306
 307    bool has_source_modifiers = value.negate || value.abs;
 308
 309    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 310     * instructions.
 311     */
 312    if ((has_source_modifiers || value.file == UNIFORM ||
 313         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(devinfo))
 314       return false;
 315
 316    if (has_source_modifiers &&
 317        value.type != inst->src[arg].type &&
 318        !inst->can_change_types())
 319       return false;
 320
 321    if (has_source_modifiers &&
 322        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
 323       return false;
 324
 325    unsigned composed_swizzle = brw_compose_swizzle(inst->src[arg].swizzle,
 326                                                    value.swizzle);
 327    if (inst->is_3src(devinfo) &&
 328        (value.file == UNIFORM ||
 329         (value.file == ATTR && attributes_per_reg != 1)) &&
 330        !brw_is_single_value_swizzle(composed_swizzle))
 331       return false;
 332
 333    if (inst->is_send_from_grf())
 334       return false;
 335
 336    /* we can't generally copy-propagate UD negations becuse we
 337     * end up accessing the resulting values as signed integers
 338     * instead. See also resolve_ud_negate().
 339     */
 340    if (value.negate &&
 341        value.type == BRW_REGISTER_TYPE_UD)
 342       return false;
 343
 344    /* Don't report progress if this is a noop. */
 345    if (value.equals(inst->src[arg]))
 346       return false;
 347
 348    const unsigned dst_saturate_mask = inst->dst.writemask &
 349       brw_apply_swizzle_to_mask(inst->src[arg].swizzle, entry->saturatemask);
 350
 351    if (dst_saturate_mask) {
 352       /* We either saturate all or nothing. */
 353       if (dst_saturate_mask != inst->dst.writemask)
 354          return false;
 355
 356       /* Limit saturate propagation only to SEL with src1 bounded within 0.0
 357        * and 1.0, otherwise skip copy propagate altogether.
 358        */
 359       switch(inst->opcode) {
 360       case BRW_OPCODE_SEL:
 361          if (arg != 0 ||
 362              inst->src[0].type != BRW_REGISTER_TYPE_F ||
 363              inst->src[1].file != IMM ||
 364              inst->src[1].type != BRW_REGISTER_TYPE_F ||
 365              inst->src[1].f < 0.0 ||
 366              inst->src[1].f > 1.0) {
 367             return false;
 368          }
 369          if (!inst->saturate)
 370             inst->saturate = true;
 371          break;
 372       default:
 373          return false;
 374       }
 375    }
 376
 377    /* Build the final value */
 378    if (inst->src[arg].abs) {
 379       value.negate = false;
 380       value.abs = true;
 381    }
 382    if (inst->src[arg].negate)
 383       value.negate = !value.negate;
 384
 385    value.swizzle = composed_swizzle;
 386    if (has_source_modifiers &&
 387        value.type != inst->src[arg].type) {
 388       assert(inst->can_change_types());
 389       for (int i = 0; i < 3; i++) {
 390          inst->src[i].type = value.type;
 391       }
 392       inst->dst.type = value.type;
 393    } else {
 394       value.type = inst->src[arg].type;
 395    }
 396
 397    inst->src[arg] = value;
 398    return true;
 399 }
 400
 401 bool
 402 vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 403 {
 404    /* If we are in dual instanced or single mode, then attributes are going
 405     * to be interleaved, so one register contains two attribute slots.
 406     */
 407    const int attributes_per_reg =
 408       prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
 409    bool progress = false;
 410    struct copy_entry entries[alloc.total_size];
 411
 412    memset(&entries, 0, sizeof(entries));
 413
 414    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 415       /* This pass only works on basic blocks.  If there's flow
 416        * control, throw out all our information and start from
 417        * scratch.
 418        *
 419        * This should really be fixed by using a structure like in
 420        * src/glsl/opt_copy_propagation.cpp to track available copies.
 421        */
 422       if (!is_dominated_by_previous_instruction(inst)) {
 423          memset(&entries, 0, sizeof(entries));
 424          continue;
 425       }
 426
 427       /* For each source arg, see if each component comes from a copy
 428        * from the same type file (IMM, VGRF, UNIFORM), and try
 429        * optimizing out access to the copy result
 430        */
 431       for (int i = 2; i >= 0; i--) {
 432          /* Copied values end up in GRFs, and we don't track reladdr
 433           * accesses.
 434           */
 435          if (inst->src[i].file != VGRF ||
 436              inst->src[i].reladdr)
 437             continue;
 438
 439          /* We only handle single-register copies. */
 440          if (inst->regs_read(i) != 1)
 441             continue;
 442
 443          const unsigned reg = (alloc.offsets[inst->src[i].nr] +
 444                                 inst->src[i].reg_offset);
 445          const copy_entry &entry = entries[reg];
 446
 447          if (do_constant_prop && try_constant_propagate(devinfo, inst, i, &entry))
 448             progress = true;
 449          else if (try_copy_propagate(devinfo, inst, i, &entry, attributes_per_reg))
 450             progress = true;
 451       }
 452
 453       /* Track available source registers. */
 454       if (inst->dst.file == VGRF) {
 455          const int reg =
 456             alloc.offsets[inst->dst.nr] + inst->dst.reg_offset;
 457
 458          /* Update our destination's current channel values.  For a direct copy,
 459           * the value is the newly propagated source.  Otherwise, we don't know
 460           * the new value, so clear it.
 461           */
 462          bool direct_copy = is_direct_copy(inst);
 463          entries[reg].saturatemask &= ~inst->dst.writemask;
 464          for (int i = 0; i < 4; i++) {
 465             if (inst->dst.writemask & (1 << i)) {
 466                entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
 467                entries[reg].saturatemask |=
 468                   inst->saturate && direct_copy ? 1 << i : 0;
 469             }
 470          }
 471
 472          /* Clear the records for any registers whose current value came from
 473           * our destination's updated channels, as the two are no longer equal.
 474           */
 475          if (inst->dst.reladdr)
 476             memset(&entries, 0, sizeof(entries));
 477          else {
 478             for (unsigned i = 0; i < alloc.total_size; i++) {
 479                for (int j = 0; j < 4; j++) {
 480                   if (is_channel_updated(inst, entries[i].value, j)) {
 481                      entries[i].value[j] = NULL;
 482                      entries[i].saturatemask &= ~(1 << j);
 483                   }
 484                }
 485             }
 486          }
 487       }
 488    }
 489
 490    if (progress)
 491       invalidate_live_intervals();
 492
 493    return progress;
 494 }
 495
 496 } /* namespace brw */