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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
34 #include "main/macros.h"
40 is_direct_copy(vec4_instruction
*inst
)
42 return (inst
->opcode
== BRW_OPCODE_MOV
&&
44 inst
->dst
.file
== GRF
&&
47 !inst
->src
[0].reladdr
&&
48 inst
->dst
.type
== inst
->src
[0].type
);
52 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
54 return (inst
->opcode
!= BRW_OPCODE_DO
&&
55 inst
->opcode
!= BRW_OPCODE_WHILE
&&
56 inst
->opcode
!= BRW_OPCODE_ELSE
&&
57 inst
->opcode
!= BRW_OPCODE_ENDIF
);
61 is_channel_updated(vec4_instruction
*inst
, src_reg
*values
[4], int ch
)
63 const src_reg
*src
= values
[ch
];
65 /* consider GRF only */
66 assert(inst
->dst
.file
== GRF
);
67 if (!src
|| src
->file
!= GRF
)
70 return (src
->reg
== inst
->dst
.reg
&&
71 src
->reg_offset
== inst
->dst
.reg_offset
&&
72 inst
->dst
.writemask
& (1 << BRW_GET_SWZ(src
->swizzle
, ch
)));
76 try_constant_propagate(struct brw_context
*brw
, vec4_instruction
*inst
,
77 int arg
, src_reg
*values
[4])
79 /* For constant propagation, we only handle the same constant
80 * across all 4 channels. Some day, we should handle the 8-bit
81 * float vector format, which would let us constant propagate
84 src_reg value
= *values
[0];
85 for (int i
= 1; i
< 4; i
++) {
86 if (!value
.equals(*values
[i
]))
90 if (value
.file
!= IMM
)
93 if (inst
->src
[arg
].abs
) {
94 if (value
.type
== BRW_REGISTER_TYPE_F
) {
95 value
.imm
.f
= fabs(value
.imm
.f
);
96 } else if (value
.type
== BRW_REGISTER_TYPE_D
) {
98 value
.imm
.i
= -value
.imm
.i
;
102 if (inst
->src
[arg
].negate
) {
103 if (value
.type
== BRW_REGISTER_TYPE_F
)
104 value
.imm
.f
= -value
.imm
.f
;
106 value
.imm
.u
= -value
.imm
.u
;
109 switch (inst
->opcode
) {
111 inst
->src
[arg
] = value
;
114 case SHADER_OPCODE_POW
:
115 case SHADER_OPCODE_INT_QUOTIENT
:
116 case SHADER_OPCODE_INT_REMAINDER
:
124 case BRW_OPCODE_BFI1
:
128 case BRW_OPCODE_SUBB
:
130 inst
->src
[arg
] = value
;
135 case BRW_OPCODE_MACH
:
141 case BRW_OPCODE_ADDC
:
143 inst
->src
[arg
] = value
;
145 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
146 /* Fit this constant in by commuting the operands. Exception: we
147 * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
149 if ((inst
->opcode
== BRW_OPCODE_MUL
||
150 inst
->opcode
== BRW_OPCODE_MACH
) &&
151 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
152 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
154 inst
->src
[0] = inst
->src
[1];
155 inst
->src
[1] = value
;
162 inst
->src
[arg
] = value
;
164 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
167 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
168 if (new_cmod
!= ~0u) {
169 /* Fit this constant in by swapping the operands and
172 inst
->src
[0] = inst
->src
[1];
173 inst
->src
[1] = value
;
174 inst
->conditional_mod
= new_cmod
;
182 inst
->src
[arg
] = value
;
184 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
185 inst
->src
[0] = inst
->src
[1];
186 inst
->src
[1] = value
;
188 /* If this was predicated, flipping operands means
189 * we also need to flip the predicate.
191 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
192 inst
->predicate_inverse
= !inst
->predicate_inverse
;
206 is_logic_op(enum opcode opcode
)
208 return (opcode
== BRW_OPCODE_AND
||
209 opcode
== BRW_OPCODE_OR
||
210 opcode
== BRW_OPCODE_XOR
||
211 opcode
== BRW_OPCODE_NOT
);
215 try_copy_propagate(struct brw_context
*brw
, vec4_instruction
*inst
,
216 int arg
, src_reg
*values
[4])
218 /* For constant propagation, we only handle the same constant
219 * across all 4 channels. Some day, we should handle the 8-bit
220 * float vector format, which would let us constant propagate
223 src_reg value
= *values
[0];
224 for (int i
= 1; i
< 4; i
++) {
225 /* This is equals() except we don't care about the swizzle. */
226 if (value
.file
!= values
[i
]->file
||
227 value
.reg
!= values
[i
]->reg
||
228 value
.reg_offset
!= values
[i
]->reg_offset
||
229 value
.type
!= values
[i
]->type
||
230 value
.negate
!= values
[i
]->negate
||
231 value
.abs
!= values
[i
]->abs
) {
236 /* Compute the swizzle of the original register by swizzling the
237 * component loaded from each value according to the swizzle of
238 * operand we're going to change.
241 for (int i
= 0; i
< 4; i
++) {
242 s
[i
] = BRW_GET_SWZ(values
[i
]->swizzle
,
243 BRW_GET_SWZ(inst
->src
[arg
].swizzle
, i
));
245 value
.swizzle
= BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]);
247 if (value
.file
!= UNIFORM
&&
254 if (is_logic_op(inst
->opcode
)) {
260 if (inst
->src
[arg
].abs
) {
261 value
.negate
= false;
264 if (inst
->src
[arg
].negate
)
265 value
.negate
= !value
.negate
;
267 bool has_source_modifiers
= value
.negate
|| value
.abs
;
269 /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
272 if ((has_source_modifiers
|| value
.file
== UNIFORM
||
273 value
.swizzle
!= BRW_SWIZZLE_XYZW
) && !inst
->can_do_source_mods(brw
))
276 if (has_source_modifiers
&& value
.type
!= inst
->src
[arg
].type
)
279 bool is_3src_inst
= (inst
->opcode
== BRW_OPCODE_LRP
||
280 inst
->opcode
== BRW_OPCODE_MAD
||
281 inst
->opcode
== BRW_OPCODE_BFE
||
282 inst
->opcode
== BRW_OPCODE_BFI2
);
283 if (is_3src_inst
&& value
.file
== UNIFORM
)
286 if (inst
->is_send_from_grf())
289 /* We can't copy-propagate a UD negation into a condmod
290 * instruction, because the condmod ends up looking at the 33-bit
291 * signed accumulator value instead of the 32-bit value we wanted
293 if (inst
->conditional_mod
&&
295 value
.type
== BRW_REGISTER_TYPE_UD
)
298 /* Don't report progress if this is a noop. */
299 if (value
.equals(inst
->src
[arg
]))
302 value
.type
= inst
->src
[arg
].type
;
303 inst
->src
[arg
] = value
;
308 vec4_visitor::opt_copy_propagation()
310 bool progress
= false;
311 src_reg
*cur_value
[virtual_grf_reg_count
][4];
313 memset(&cur_value
, 0, sizeof(cur_value
));
315 foreach_in_list(vec4_instruction
, inst
, &instructions
) {
316 /* This pass only works on basic blocks. If there's flow
317 * control, throw out all our information and start from
320 * This should really be fixed by using a structure like in
321 * src/glsl/opt_copy_propagation.cpp to track available copies.
323 if (!is_dominated_by_previous_instruction(inst
)) {
324 memset(cur_value
, 0, sizeof(cur_value
));
328 /* For each source arg, see if each component comes from a copy
329 * from the same type file (IMM, GRF, UNIFORM), and try
330 * optimizing out access to the copy result
332 for (int i
= 2; i
>= 0; i
--) {
333 /* Copied values end up in GRFs, and we don't track reladdr
336 if (inst
->src
[i
].file
!= GRF
||
337 inst
->src
[i
].reladdr
)
340 int reg
= (virtual_grf_reg_map
[inst
->src
[i
].reg
] +
341 inst
->src
[i
].reg_offset
);
343 /* Find the regs that each swizzle component came from.
347 for (c
= 0; c
< 4; c
++) {
348 values
[c
] = cur_value
[reg
][BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)];
350 /* If there's no available copy for this channel, bail.
351 * We could be more aggressive here -- some channels might
352 * not get used based on the destination writemask.
357 /* We'll only be able to copy propagate if the sources are
358 * all from the same file -- there's no ability to swizzle
359 * 0 or 1 constants in with source registers like in i915.
361 if (c
> 0 && values
[c
- 1]->file
!= values
[c
]->file
)
368 if (try_constant_propagate(brw
, inst
, i
, values
))
371 if (try_copy_propagate(brw
, inst
, i
, values
))
375 /* Track available source registers. */
376 if (inst
->dst
.file
== GRF
) {
378 virtual_grf_reg_map
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
380 /* Update our destination's current channel values. For a direct copy,
381 * the value is the newly propagated source. Otherwise, we don't know
382 * the new value, so clear it.
384 bool direct_copy
= is_direct_copy(inst
);
385 for (int i
= 0; i
< 4; i
++) {
386 if (inst
->dst
.writemask
& (1 << i
)) {
387 cur_value
[reg
][i
] = direct_copy
? &inst
->src
[0] : NULL
;
391 /* Clear the records for any registers whose current value came from
392 * our destination's updated channels, as the two are no longer equal.
394 if (inst
->dst
.reladdr
)
395 memset(cur_value
, 0, sizeof(cur_value
));
397 for (int i
= 0; i
< virtual_grf_reg_count
; i
++) {
398 for (int j
= 0; j
< 4; j
++) {
399 if (is_channel_updated(inst
, cur_value
[i
], j
)){
400 cur_value
[i
][j
] = NULL
;
409 invalidate_live_intervals();
414 } /* namespace brw */