src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
  62 {
  63    /* For constant propagation, we only handle the same constant
  64     * across all 4 channels.  Some day, we should handle the 8-bit
  65     * float vector format, which would let us constant propagate
  66     * vectors better.
  67     */
  68    src_reg value = *values[0];
  69    for (int i = 1; i < 4; i++) {
  70       if (!value.equals(values[i]))
  71          return false;
  72    }
  73
  74    if (value.file != IMM)
  75       return false;
  76
  77    if (inst->src[arg].abs) {
  78       if (value.type == BRW_REGISTER_TYPE_F) {
  79          value.imm.f = fabs(value.imm.f);
  80       } else if (value.type == BRW_REGISTER_TYPE_D) {
  81          if (value.imm.i < 0)
  82             value.imm.i = -value.imm.i;
  83       }
  84    }
  85
  86    if (inst->src[arg].negate) {
  87       if (value.type == BRW_REGISTER_TYPE_F)
  88          value.imm.f = -value.imm.f;
  89       else
  90          value.imm.u = -value.imm.u;
  91    }
  92
  93    switch (inst->opcode) {
  94    case BRW_OPCODE_MOV:
  95       inst->src[arg] = value;
  96       return true;
  97
  98    case BRW_OPCODE_BFI1:
  99    case BRW_OPCODE_ASR:
 100    case BRW_OPCODE_SHL:
 101    case BRW_OPCODE_SHR:
 102    case BRW_OPCODE_SUBB:
 103       if (arg == 1) {
 104          inst->src[arg] = value;
 105          return true;
 106       }
 107       break;
 108
 109    case BRW_OPCODE_MACH:
 110    case BRW_OPCODE_MUL:
 111    case BRW_OPCODE_ADD:
 112    case BRW_OPCODE_OR:
 113    case BRW_OPCODE_AND:
 114    case BRW_OPCODE_XOR:
 115    case BRW_OPCODE_ADDC:
 116       if (arg == 1) {
 117          inst->src[arg] = value;
 118          return true;
 119       } else if (arg == 0 && inst->src[1].file != IMM) {
 120          /* Fit this constant in by commuting the operands.  Exception: we
 121           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 122           */
 123          if ((inst->opcode == BRW_OPCODE_MUL ||
 124               inst->opcode == BRW_OPCODE_MACH) &&
 125              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 126               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 127             break;
 128          inst->src[0] = inst->src[1];
 129          inst->src[1] = value;
 130          return true;
 131       }
 132       break;
 133
 134    case BRW_OPCODE_CMP:
 135       if (arg == 1) {
 136          inst->src[arg] = value;
 137          return true;
 138       } else if (arg == 0 && inst->src[1].file != IMM) {
 139          uint32_t new_cmod;
 140
 141          new_cmod = brw_swap_cmod(inst->conditional_mod);
 142          if (new_cmod != ~0u) {
 143             /* Fit this constant in by swapping the operands and
 144              * flipping the test.
 145              */
 146             inst->src[0] = inst->src[1];
 147             inst->src[1] = value;
 148             inst->conditional_mod = new_cmod;
 149             return true;
 150          }
 151       }
 152       break;
 153
 154    case BRW_OPCODE_SEL:
 155       if (arg == 1) {
 156          inst->src[arg] = value;
 157          return true;
 158       } else if (arg == 0 && inst->src[1].file != IMM) {
 159          inst->src[0] = inst->src[1];
 160          inst->src[1] = value;
 161
 162          /* If this was predicated, flipping operands means
 163           * we also need to flip the predicate.
 164           */
 165          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 166             inst->predicate_inverse = !inst->predicate_inverse;
 167          }
 168          return true;
 169       }
 170       break;
 171
 172    default:
 173       break;
 174    }
 175
 176    return false;
 177 }
 178
 179 bool
 180 vec4_visitor::try_copy_propagation(vec4_instruction *inst, int arg,
 181                                    src_reg *values[4])
 182 {
 183    /* For constant propagation, we only handle the same constant
 184     * across all 4 channels.  Some day, we should handle the 8-bit
 185     * float vector format, which would let us constant propagate
 186     * vectors better.
 187     */
 188    src_reg value = *values[0];
 189    for (int i = 1; i < 4; i++) {
 190       /* This is equals() except we don't care about the swizzle. */
 191       if (value.file != values[i]->file ||
 192           value.reg != values[i]->reg ||
 193           value.reg_offset != values[i]->reg_offset ||
 194           value.type != values[i]->type ||
 195           value.negate != values[i]->negate ||
 196           value.abs != values[i]->abs) {
 197          return false;
 198       }
 199    }
 200
 201    /* Compute the swizzle of the original register by swizzling the
 202     * component loaded from each value according to the swizzle of
 203     * operand we're going to change.
 204     */
 205    int s[4];
 206    for (int i = 0; i < 4; i++) {
 207       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 208                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 209    }
 210    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 211
 212    if (value.file != UNIFORM &&
 213        value.file != GRF &&
 214        value.file != ATTR)
 215       return false;
 216
 217    if (inst->src[arg].abs) {
 218       value.negate = false;
 219       value.abs = true;
 220    }
 221    if (inst->src[arg].negate)
 222       value.negate = !value.negate;
 223
 224    bool has_source_modifiers = value.negate || value.abs;
 225
 226    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 227     * instructions.
 228     */
 229    if ((has_source_modifiers || value.file == UNIFORM ||
 230         value.swizzle != BRW_SWIZZLE_XYZW) && !can_do_source_mods(inst))
 231       return false;
 232
 233    if (has_source_modifiers && value.type != inst->src[arg].type)
 234       return false;
 235
 236    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 237                         inst->opcode == BRW_OPCODE_MAD ||
 238                         inst->opcode == BRW_OPCODE_BFE ||
 239                         inst->opcode == BRW_OPCODE_BFI2);
 240    if (is_3src_inst && value.file == UNIFORM)
 241       return false;
 242
 243    if (inst->is_send_from_grf())
 244       return false;
 245
 246    /* We can't copy-propagate a UD negation into a condmod
 247     * instruction, because the condmod ends up looking at the 33-bit
 248     * signed accumulator value instead of the 32-bit value we wanted
 249     */
 250    if (inst->conditional_mod &&
 251        value.negate &&
 252        value.type == BRW_REGISTER_TYPE_UD)
 253       return false;
 254
 255    /* Don't report progress if this is a noop. */
 256    if (value.equals(&inst->src[arg]))
 257       return false;
 258
 259    value.type = inst->src[arg].type;
 260    inst->src[arg] = value;
 261    return true;
 262 }
 263
 264 bool
 265 vec4_visitor::opt_copy_propagation()
 266 {
 267    bool progress = false;
 268    src_reg *cur_value[virtual_grf_reg_count][4];
 269
 270    memset(&cur_value, 0, sizeof(cur_value));
 271
 272    foreach_list(node, &this->instructions) {
 273       vec4_instruction *inst = (vec4_instruction *)node;
 274
 275       /* This pass only works on basic blocks.  If there's flow
 276        * control, throw out all our information and start from
 277        * scratch.
 278        *
 279        * This should really be fixed by using a structure like in
 280        * src/glsl/opt_copy_propagation.cpp to track available copies.
 281        */
 282       if (!is_dominated_by_previous_instruction(inst)) {
 283          memset(cur_value, 0, sizeof(cur_value));
 284          continue;
 285       }
 286
 287       /* For each source arg, see if each component comes from a copy
 288        * from the same type file (IMM, GRF, UNIFORM), and try
 289        * optimizing out access to the copy result
 290        */
 291       for (int i = 2; i >= 0; i--) {
 292          /* Copied values end up in GRFs, and we don't track reladdr
 293           * accesses.
 294           */
 295          if (inst->src[i].file != GRF ||
 296              inst->src[i].reladdr)
 297             continue;
 298
 299          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 300                     inst->src[i].reg_offset);
 301
 302          /* Find the regs that each swizzle component came from.
 303           */
 304          src_reg *values[4];
 305          int c;
 306          for (c = 0; c < 4; c++) {
 307             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 308
 309             /* If there's no available copy for this channel, bail.
 310              * We could be more aggressive here -- some channels might
 311              * not get used based on the destination writemask.
 312              */
 313             if (!values[c])
 314                break;
 315
 316             /* We'll only be able to copy propagate if the sources are
 317              * all from the same file -- there's no ability to swizzle
 318              * 0 or 1 constants in with source registers like in i915.
 319              */
 320             if (c > 0 && values[c - 1]->file != values[c]->file)
 321                break;
 322          }
 323
 324          if (c != 4)
 325             continue;
 326
 327          if (try_constant_propagation(inst, i, values) ||
 328              try_copy_propagation(inst, i, values))
 329             progress = true;
 330       }
 331
 332       /* Track available source registers. */
 333       if (inst->dst.file == GRF) {
 334          const int reg =
 335             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 336
 337          /* Update our destination's current channel values.  For a direct copy,
 338           * the value is the newly propagated source.  Otherwise, we don't know
 339           * the new value, so clear it.
 340           */
 341          bool direct_copy = is_direct_copy(inst);
 342          for (int i = 0; i < 4; i++) {
 343             if (inst->dst.writemask & (1 << i)) {
 344                cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
 345             }
 346          }
 347
 348          /* Clear the records for any registers whose current value came from
 349           * our destination's updated channels, as the two are no longer equal.
 350           */
 351          if (inst->dst.reladdr)
 352             memset(cur_value, 0, sizeof(cur_value));
 353          else {
 354             for (int i = 0; i < virtual_grf_reg_count; i++) {
 355                for (int j = 0; j < 4; j++) {
 356                   if (inst->dst.writemask & (1 << j) &&
 357                       cur_value[i][j] &&
 358                       cur_value[i][j]->file == GRF &&
 359                       cur_value[i][j]->reg == inst->dst.reg &&
 360                       cur_value[i][j]->reg_offset == inst->dst.reg_offset) {
 361                      cur_value[i][j] = NULL;
 362                   }
 363                }
 364             }
 365          }
 366       }
 367    }
 368
 369    if (progress)
 370       invalidate_live_intervals();
 371
 372    return progress;
 373 }
 374
 375 } /* namespace brw */