src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
  62 {
  63    /* For constant propagation, we only handle the same constant
  64     * across all 4 channels.  Some day, we should handle the 8-bit
  65     * float vector format, which would let us constant propagate
  66     * vectors better.
  67     */
  68    src_reg value = *values[0];
  69    for (int i = 1; i < 4; i++) {
  70       if (!value.equals(values[i]))
  71          return false;
  72    }
  73
  74    if (value.file != IMM)
  75       return false;
  76
  77    if (inst->src[arg].abs) {
  78       if (value.type == BRW_REGISTER_TYPE_F) {
  79          value.imm.f = fabs(value.imm.f);
  80       } else if (value.type == BRW_REGISTER_TYPE_D) {
  81          if (value.imm.i < 0)
  82             value.imm.i = -value.imm.i;
  83       }
  84    }
  85
  86    if (inst->src[arg].negate) {
  87       if (value.type == BRW_REGISTER_TYPE_F)
  88          value.imm.f = -value.imm.f;
  89       else
  90          value.imm.u = -value.imm.u;
  91    }
  92
  93    switch (inst->opcode) {
  94    case BRW_OPCODE_MOV:
  95       inst->src[arg] = value;
  96       return true;
  97
  98    case BRW_OPCODE_SHL:
  99    case BRW_OPCODE_SHR:
 100       if (arg == 1) {
 101          inst->src[arg] = value;
 102          return true;
 103       }
 104       break;
 105
 106    case BRW_OPCODE_MACH:
 107    case BRW_OPCODE_MUL:
 108    case BRW_OPCODE_ADD:
 109    case BRW_OPCODE_OR:
 110    case BRW_OPCODE_AND:
 111    case BRW_OPCODE_XOR:
 112       if (arg == 1) {
 113          inst->src[arg] = value;
 114          return true;
 115       } else if (arg == 0 && inst->src[1].file != IMM) {
 116          /* Fit this constant in by commuting the operands.  Exception: we
 117           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 118           */
 119          if ((inst->opcode == BRW_OPCODE_MUL ||
 120               inst->opcode == BRW_OPCODE_MACH) &&
 121              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 122               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 123             break;
 124          inst->src[0] = inst->src[1];
 125          inst->src[1] = value;
 126          return true;
 127       }
 128       break;
 129
 130    case BRW_OPCODE_CMP:
 131       if (arg == 1) {
 132          inst->src[arg] = value;
 133          return true;
 134       } else if (arg == 0 && inst->src[1].file != IMM) {
 135          uint32_t new_cmod;
 136
 137          new_cmod = brw_swap_cmod(inst->conditional_mod);
 138          if (new_cmod != ~0u) {
 139             /* Fit this constant in by swapping the operands and
 140              * flipping the test.
 141              */
 142             inst->src[0] = inst->src[1];
 143             inst->src[1] = value;
 144             inst->conditional_mod = new_cmod;
 145             return true;
 146          }
 147       }
 148       break;
 149
 150    case BRW_OPCODE_SEL:
 151       if (arg == 1) {
 152          inst->src[arg] = value;
 153          return true;
 154       } else if (arg == 0 && inst->src[1].file != IMM) {
 155          inst->src[0] = inst->src[1];
 156          inst->src[1] = value;
 157
 158          /* If this was predicated, flipping operands means
 159           * we also need to flip the predicate.
 160           */
 161          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 162             inst->predicate_inverse = !inst->predicate_inverse;
 163          }
 164          return true;
 165       }
 166       break;
 167
 168    default:
 169       break;
 170    }
 171
 172    return false;
 173 }
 174
 175 bool
 176 vec4_visitor::try_copy_propagation(vec4_instruction *inst, int arg,
 177                                    src_reg *values[4])
 178 {
 179    /* For constant propagation, we only handle the same constant
 180     * across all 4 channels.  Some day, we should handle the 8-bit
 181     * float vector format, which would let us constant propagate
 182     * vectors better.
 183     */
 184    src_reg value = *values[0];
 185    for (int i = 1; i < 4; i++) {
 186       /* This is equals() except we don't care about the swizzle. */
 187       if (value.file != values[i]->file ||
 188           value.reg != values[i]->reg ||
 189           value.reg_offset != values[i]->reg_offset ||
 190           value.type != values[i]->type ||
 191           value.negate != values[i]->negate ||
 192           value.abs != values[i]->abs) {
 193          return false;
 194       }
 195    }
 196
 197    /* Compute the swizzle of the original register by swizzling the
 198     * component loaded from each value according to the swizzle of
 199     * operand we're going to change.
 200     */
 201    int s[4];
 202    for (int i = 0; i < 4; i++) {
 203       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 204                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 205    }
 206    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 207
 208    if (value.file != UNIFORM &&
 209        value.file != GRF &&
 210        value.file != ATTR)
 211       return false;
 212
 213    if (inst->src[arg].abs) {
 214       value.negate = false;
 215       value.abs = true;
 216    }
 217    if (inst->src[arg].negate)
 218       value.negate = !value.negate;
 219
 220    bool has_source_modifiers = value.negate || value.abs;
 221
 222    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 223     * instructions.
 224     */
 225    if ((has_source_modifiers || value.file == UNIFORM ||
 226         value.swizzle != BRW_SWIZZLE_XYZW) && !can_do_source_mods(inst))
 227       return false;
 228
 229    if (has_source_modifiers && value.type != inst->src[arg].type)
 230       return false;
 231
 232    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 233                         inst->opcode == BRW_OPCODE_MAD ||
 234                         inst->opcode == BRW_OPCODE_BFE ||
 235                         inst->opcode == BRW_OPCODE_BFI2);
 236    if (is_3src_inst && value.file == UNIFORM)
 237       return false;
 238
 239    /* We can't copy-propagate a UD negation into a condmod
 240     * instruction, because the condmod ends up looking at the 33-bit
 241     * signed accumulator value instead of the 32-bit value we wanted
 242     */
 243    if (inst->conditional_mod &&
 244        value.negate &&
 245        value.type == BRW_REGISTER_TYPE_UD)
 246       return false;
 247
 248    /* Don't report progress if this is a noop. */
 249    if (value.equals(&inst->src[arg]))
 250       return false;
 251
 252    value.type = inst->src[arg].type;
 253    inst->src[arg] = value;
 254    return true;
 255 }
 256
 257 bool
 258 vec4_visitor::opt_copy_propagation()
 259 {
 260    bool progress = false;
 261    src_reg *cur_value[virtual_grf_reg_count][4];
 262
 263    memset(&cur_value, 0, sizeof(cur_value));
 264
 265    foreach_list(node, &this->instructions) {
 266       vec4_instruction *inst = (vec4_instruction *)node;
 267
 268       /* This pass only works on basic blocks.  If there's flow
 269        * control, throw out all our information and start from
 270        * scratch.
 271        *
 272        * This should really be fixed by using a structure like in
 273        * src/glsl/opt_copy_propagation.cpp to track available copies.
 274        */
 275       if (!is_dominated_by_previous_instruction(inst)) {
 276          memset(cur_value, 0, sizeof(cur_value));
 277          continue;
 278       }
 279
 280       /* For each source arg, see if each component comes from a copy
 281        * from the same type file (IMM, GRF, UNIFORM), and try
 282        * optimizing out access to the copy result
 283        */
 284       for (int i = 2; i >= 0; i--) {
 285          /* Copied values end up in GRFs, and we don't track reladdr
 286           * accesses.
 287           */
 288          if (inst->src[i].file != GRF ||
 289              inst->src[i].reladdr)
 290             continue;
 291
 292          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 293                     inst->src[i].reg_offset);
 294
 295          /* Find the regs that each swizzle component came from.
 296           */
 297          src_reg *values[4];
 298          int c;
 299          for (c = 0; c < 4; c++) {
 300             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 301
 302             /* If there's no available copy for this channel, bail.
 303              * We could be more aggressive here -- some channels might
 304              * not get used based on the destination writemask.
 305              */
 306             if (!values[c])
 307                break;
 308
 309             /* We'll only be able to copy propagate if the sources are
 310              * all from the same file -- there's no ability to swizzle
 311              * 0 or 1 constants in with source registers like in i915.
 312              */
 313             if (c > 0 && values[c - 1]->file != values[c]->file)
 314                break;
 315          }
 316
 317          if (c != 4)
 318             continue;
 319
 320          if (try_constant_propagation(inst, i, values) ||
 321              try_copy_propagation(inst, i, values))
 322             progress = true;
 323       }
 324
 325       /* Track available source registers. */
 326       if (inst->dst.file == GRF) {
 327          const int reg =
 328             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 329
 330          /* Update our destination's current channel values.  For a direct copy,
 331           * the value is the newly propagated source.  Otherwise, we don't know
 332           * the new value, so clear it.
 333           */
 334          bool direct_copy = is_direct_copy(inst);
 335          for (int i = 0; i < 4; i++) {
 336             if (inst->dst.writemask & (1 << i)) {
 337                cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
 338             }
 339          }
 340
 341          /* Clear the records for any registers whose current value came from
 342           * our destination's updated channels, as the two are no longer equal.
 343           */
 344          if (inst->dst.reladdr)
 345             memset(cur_value, 0, sizeof(cur_value));
 346          else {
 347             for (int i = 0; i < virtual_grf_reg_count; i++) {
 348                for (int j = 0; j < 4; j++) {
 349                   if (inst->dst.writemask & (1 << j) &&
 350                       cur_value[i][j] &&
 351                       cur_value[i][j]->file == GRF &&
 352                       cur_value[i][j]->reg == inst->dst.reg &&
 353                       cur_value[i][j]->reg_offset == inst->dst.reg_offset) {
 354                      cur_value[i][j] = NULL;
 355                   }
 356                }
 357             }
 358          }
 359       }
 360    }
 361
 362    if (progress)
 363       live_intervals_valid = false;
 364
 365    return progress;
 366 }
 367
 368 } /* namespace brw */