src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
  62 {
  63    /* For constant propagation, we only handle the same constant
  64     * across all 4 channels.  Some day, we should handle the 8-bit
  65     * float vector format, which would let us constant propagate
  66     * vectors better.
  67     */
  68    src_reg value = *values[0];
  69    for (int i = 1; i < 4; i++) {
  70       if (!value.equals(values[i]))
  71          return false;
  72    }
  73
  74    if (value.file != IMM)
  75       return false;
  76
  77    if (inst->src[arg].abs) {
  78       if (value.type == BRW_REGISTER_TYPE_F) {
  79          value.imm.f = fabs(value.imm.f);
  80       } else if (value.type == BRW_REGISTER_TYPE_D) {
  81          if (value.imm.i < 0)
  82             value.imm.i = -value.imm.i;
  83       }
  84    }
  85
  86    if (inst->src[arg].negate) {
  87       if (value.type == BRW_REGISTER_TYPE_F)
  88          value.imm.f = -value.imm.f;
  89       else
  90          value.imm.u = -value.imm.u;
  91    }
  92
  93    switch (inst->opcode) {
  94    case BRW_OPCODE_MOV:
  95       inst->src[arg] = value;
  96       return true;
  97
  98    case BRW_OPCODE_SHL:
  99    case BRW_OPCODE_SHR:
 100    case BRW_OPCODE_ADDC:
 101    case BRW_OPCODE_SUBB:
 102       if (arg == 1) {
 103          inst->src[arg] = value;
 104          return true;
 105       }
 106       break;
 107
 108    case BRW_OPCODE_MACH:
 109    case BRW_OPCODE_MUL:
 110    case BRW_OPCODE_ADD:
 111    case BRW_OPCODE_OR:
 112    case BRW_OPCODE_AND:
 113    case BRW_OPCODE_XOR:
 114       if (arg == 1) {
 115          inst->src[arg] = value;
 116          return true;
 117       } else if (arg == 0 && inst->src[1].file != IMM) {
 118          /* Fit this constant in by commuting the operands.  Exception: we
 119           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 120           */
 121          if ((inst->opcode == BRW_OPCODE_MUL ||
 122               inst->opcode == BRW_OPCODE_MACH) &&
 123              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 124               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 125             break;
 126          inst->src[0] = inst->src[1];
 127          inst->src[1] = value;
 128          return true;
 129       }
 130       break;
 131
 132    case BRW_OPCODE_CMP:
 133       if (arg == 1) {
 134          inst->src[arg] = value;
 135          return true;
 136       } else if (arg == 0 && inst->src[1].file != IMM) {
 137          uint32_t new_cmod;
 138
 139          new_cmod = brw_swap_cmod(inst->conditional_mod);
 140          if (new_cmod != ~0u) {
 141             /* Fit this constant in by swapping the operands and
 142              * flipping the test.
 143              */
 144             inst->src[0] = inst->src[1];
 145             inst->src[1] = value;
 146             inst->conditional_mod = new_cmod;
 147             return true;
 148          }
 149       }
 150       break;
 151
 152    case BRW_OPCODE_SEL:
 153       if (arg == 1) {
 154          inst->src[arg] = value;
 155          return true;
 156       } else if (arg == 0 && inst->src[1].file != IMM) {
 157          inst->src[0] = inst->src[1];
 158          inst->src[1] = value;
 159
 160          /* If this was predicated, flipping operands means
 161           * we also need to flip the predicate.
 162           */
 163          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 164             inst->predicate_inverse = !inst->predicate_inverse;
 165          }
 166          return true;
 167       }
 168       break;
 169
 170    default:
 171       break;
 172    }
 173
 174    return false;
 175 }
 176
 177 bool
 178 vec4_visitor::try_copy_propagation(vec4_instruction *inst, int arg,
 179                                    src_reg *values[4])
 180 {
 181    /* For constant propagation, we only handle the same constant
 182     * across all 4 channels.  Some day, we should handle the 8-bit
 183     * float vector format, which would let us constant propagate
 184     * vectors better.
 185     */
 186    src_reg value = *values[0];
 187    for (int i = 1; i < 4; i++) {
 188       /* This is equals() except we don't care about the swizzle. */
 189       if (value.file != values[i]->file ||
 190           value.reg != values[i]->reg ||
 191           value.reg_offset != values[i]->reg_offset ||
 192           value.type != values[i]->type ||
 193           value.negate != values[i]->negate ||
 194           value.abs != values[i]->abs) {
 195          return false;
 196       }
 197    }
 198
 199    /* Compute the swizzle of the original register by swizzling the
 200     * component loaded from each value according to the swizzle of
 201     * operand we're going to change.
 202     */
 203    int s[4];
 204    for (int i = 0; i < 4; i++) {
 205       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 206                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 207    }
 208    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 209
 210    if (value.file != UNIFORM &&
 211        value.file != GRF &&
 212        value.file != ATTR)
 213       return false;
 214
 215    if (inst->src[arg].abs) {
 216       value.negate = false;
 217       value.abs = true;
 218    }
 219    if (inst->src[arg].negate)
 220       value.negate = !value.negate;
 221
 222    bool has_source_modifiers = value.negate || value.abs;
 223
 224    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 225     * instructions.
 226     */
 227    if ((has_source_modifiers || value.file == UNIFORM ||
 228         value.swizzle != BRW_SWIZZLE_XYZW) && !can_do_source_mods(inst))
 229       return false;
 230
 231    if (has_source_modifiers && value.type != inst->src[arg].type)
 232       return false;
 233
 234    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 235                         inst->opcode == BRW_OPCODE_MAD ||
 236                         inst->opcode == BRW_OPCODE_BFE ||
 237                         inst->opcode == BRW_OPCODE_BFI2);
 238    if (is_3src_inst && value.file == UNIFORM)
 239       return false;
 240
 241    /* We can't copy-propagate a UD negation into a condmod
 242     * instruction, because the condmod ends up looking at the 33-bit
 243     * signed accumulator value instead of the 32-bit value we wanted
 244     */
 245    if (inst->conditional_mod &&
 246        value.negate &&
 247        value.type == BRW_REGISTER_TYPE_UD)
 248       return false;
 249
 250    /* Don't report progress if this is a noop. */
 251    if (value.equals(&inst->src[arg]))
 252       return false;
 253
 254    value.type = inst->src[arg].type;
 255    inst->src[arg] = value;
 256    return true;
 257 }
 258
 259 bool
 260 vec4_visitor::opt_copy_propagation()
 261 {
 262    bool progress = false;
 263    src_reg *cur_value[virtual_grf_reg_count][4];
 264
 265    memset(&cur_value, 0, sizeof(cur_value));
 266
 267    foreach_list(node, &this->instructions) {
 268       vec4_instruction *inst = (vec4_instruction *)node;
 269
 270       /* This pass only works on basic blocks.  If there's flow
 271        * control, throw out all our information and start from
 272        * scratch.
 273        *
 274        * This should really be fixed by using a structure like in
 275        * src/glsl/opt_copy_propagation.cpp to track available copies.
 276        */
 277       if (!is_dominated_by_previous_instruction(inst)) {
 278          memset(cur_value, 0, sizeof(cur_value));
 279          continue;
 280       }
 281
 282       /* For each source arg, see if each component comes from a copy
 283        * from the same type file (IMM, GRF, UNIFORM), and try
 284        * optimizing out access to the copy result
 285        */
 286       for (int i = 2; i >= 0; i--) {
 287          /* Copied values end up in GRFs, and we don't track reladdr
 288           * accesses.
 289           */
 290          if (inst->src[i].file != GRF ||
 291              inst->src[i].reladdr)
 292             continue;
 293
 294          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 295                     inst->src[i].reg_offset);
 296
 297          /* Find the regs that each swizzle component came from.
 298           */
 299          src_reg *values[4];
 300          int c;
 301          for (c = 0; c < 4; c++) {
 302             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 303
 304             /* If there's no available copy for this channel, bail.
 305              * We could be more aggressive here -- some channels might
 306              * not get used based on the destination writemask.
 307              */
 308             if (!values[c])
 309                break;
 310
 311             /* We'll only be able to copy propagate if the sources are
 312              * all from the same file -- there's no ability to swizzle
 313              * 0 or 1 constants in with source registers like in i915.
 314              */
 315             if (c > 0 && values[c - 1]->file != values[c]->file)
 316                break;
 317          }
 318
 319          if (c != 4)
 320             continue;
 321
 322          if (try_constant_propagation(inst, i, values) ||
 323              try_copy_propagation(inst, i, values))
 324             progress = true;
 325       }
 326
 327       /* Track available source registers. */
 328       if (inst->dst.file == GRF) {
 329          const int reg =
 330             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 331
 332          /* Update our destination's current channel values.  For a direct copy,
 333           * the value is the newly propagated source.  Otherwise, we don't know
 334           * the new value, so clear it.
 335           */
 336          bool direct_copy = is_direct_copy(inst);
 337          for (int i = 0; i < 4; i++) {
 338             if (inst->dst.writemask & (1 << i)) {
 339                cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
 340             }
 341          }
 342
 343          /* Clear the records for any registers whose current value came from
 344           * our destination's updated channels, as the two are no longer equal.
 345           */
 346          if (inst->dst.reladdr)
 347             memset(cur_value, 0, sizeof(cur_value));
 348          else {
 349             for (int i = 0; i < virtual_grf_reg_count; i++) {
 350                for (int j = 0; j < 4; j++) {
 351                   if (inst->dst.writemask & (1 << j) &&
 352                       cur_value[i][j] &&
 353                       cur_value[i][j]->file == GRF &&
 354                       cur_value[i][j]->reg == inst->dst.reg &&
 355                       cur_value[i][j]->reg_offset == inst->dst.reg_offset) {
 356                      cur_value[i][j] = NULL;
 357                   }
 358                }
 359             }
 360          }
 361       }
 362    }
 363
 364    if (progress)
 365       live_intervals_valid = false;
 366
 367    return progress;
 368 }
 369
 370 } /* namespace brw */