src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
  62 {
  63    /* For constant propagation, we only handle the same constant
  64     * across all 4 channels.  Some day, we should handle the 8-bit
  65     * float vector format, which would let us constant propagate
  66     * vectors better.
  67     */
  68    src_reg value = *values[0];
  69    for (int i = 1; i < 4; i++) {
  70       if (!value.equals(values[i]))
  71          return false;
  72    }
  73
  74    if (value.file != IMM)
  75       return false;
  76
  77    if (inst->src[arg].abs) {
  78       if (value.type == BRW_REGISTER_TYPE_F) {
  79          value.imm.f = fabs(value.imm.f);
  80       } else if (value.type == BRW_REGISTER_TYPE_D) {
  81          if (value.imm.i < 0)
  82             value.imm.i = -value.imm.i;
  83       }
  84    }
  85
  86    if (inst->src[arg].negate) {
  87       if (value.type == BRW_REGISTER_TYPE_F)
  88          value.imm.f = -value.imm.f;
  89       else
  90          value.imm.u = -value.imm.u;
  91    }
  92
  93    switch (inst->opcode) {
  94    case BRW_OPCODE_MOV:
  95       inst->src[arg] = value;
  96       return true;
  97
  98    case BRW_OPCODE_MUL:
  99    case BRW_OPCODE_ADD:
 100       if (arg == 1) {
 101          inst->src[arg] = value;
 102          return true;
 103       } else if (arg == 0 && inst->src[1].file != IMM) {
 104          /* Fit this constant in by commuting the operands.  Exception: we
 105           * can't do this for 32-bit integer MUL because it's asymmetric.
 106           */
 107          if (inst->opcode == BRW_OPCODE_MUL &&
 108              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 109               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 110             break;
 111          inst->src[0] = inst->src[1];
 112          inst->src[1] = value;
 113          return true;
 114       }
 115       break;
 116
 117    case BRW_OPCODE_CMP:
 118       if (arg == 1) {
 119          inst->src[arg] = value;
 120          return true;
 121       } else if (arg == 0 && inst->src[1].file != IMM) {
 122          uint32_t new_cmod;
 123
 124          new_cmod = brw_swap_cmod(inst->conditional_mod);
 125          if (new_cmod != ~0u) {
 126             /* Fit this constant in by swapping the operands and
 127              * flipping the test.
 128              */
 129             inst->src[0] = inst->src[1];
 130             inst->src[1] = value;
 131             inst->conditional_mod = new_cmod;
 132             return true;
 133          }
 134       }
 135       break;
 136
 137    case BRW_OPCODE_SEL:
 138       if (arg == 1) {
 139          inst->src[arg] = value;
 140          return true;
 141       } else if (arg == 0 && inst->src[1].file != IMM) {
 142          inst->src[0] = inst->src[1];
 143          inst->src[1] = value;
 144
 145          /* If this was predicated, flipping operands means
 146           * we also need to flip the predicate.
 147           */
 148          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 149             inst->predicate_inverse = !inst->predicate_inverse;
 150          }
 151          return true;
 152       }
 153       break;
 154
 155    default:
 156       break;
 157    }
 158
 159    return false;
 160 }
 161
 162 bool
 163 vec4_visitor::try_copy_propagation(struct intel_context *intel,
 164                                    vec4_instruction *inst, int arg,
 165                                    src_reg *values[4])
 166 {
 167    /* For constant propagation, we only handle the same constant
 168     * across all 4 channels.  Some day, we should handle the 8-bit
 169     * float vector format, which would let us constant propagate
 170     * vectors better.
 171     */
 172    src_reg value = *values[0];
 173    for (int i = 1; i < 4; i++) {
 174       /* This is equals() except we don't care about the swizzle. */
 175       if (value.file != values[i]->file ||
 176           value.reg != values[i]->reg ||
 177           value.reg_offset != values[i]->reg_offset ||
 178           value.type != values[i]->type ||
 179           value.negate != values[i]->negate ||
 180           value.abs != values[i]->abs) {
 181          return false;
 182       }
 183    }
 184
 185    /* Compute the swizzle of the original register by swizzling the
 186     * component loaded from each value according to the swizzle of
 187     * operand we're going to change.
 188     */
 189    int s[4];
 190    for (int i = 0; i < 4; i++) {
 191       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 192                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 193    }
 194    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 195
 196    if (value.file != UNIFORM &&
 197        value.file != GRF &&
 198        value.file != ATTR)
 199       return false;
 200
 201    if (inst->src[arg].abs) {
 202       value.negate = false;
 203       value.abs = true;
 204    }
 205    if (inst->src[arg].negate)
 206       value.negate = !value.negate;
 207
 208    bool has_source_modifiers = (value.negate || value.abs ||
 209                                 value.swizzle != BRW_SWIZZLE_XYZW ||
 210                                 value.file == UNIFORM);
 211
 212    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 213     * instructions.
 214     */
 215    if (has_source_modifiers && !can_do_source_mods(inst))
 216       return false;
 217
 218    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 219                         inst->opcode == BRW_OPCODE_MAD ||
 220                         inst->opcode == BRW_OPCODE_BFE ||
 221                         inst->opcode == BRW_OPCODE_BFI2);
 222    if (is_3src_inst && value.file == UNIFORM)
 223       return false;
 224
 225    /* We can't copy-propagate a UD negation into a condmod
 226     * instruction, because the condmod ends up looking at the 33-bit
 227     * signed accumulator value instead of the 32-bit value we wanted
 228     */
 229    if (inst->conditional_mod &&
 230        value.negate &&
 231        value.type == BRW_REGISTER_TYPE_UD)
 232       return false;
 233
 234    /* Don't report progress if this is a noop. */
 235    if (value.equals(&inst->src[arg]))
 236       return false;
 237
 238    value.type = inst->src[arg].type;
 239    inst->src[arg] = value;
 240    return true;
 241 }
 242
 243 bool
 244 vec4_visitor::opt_copy_propagation()
 245 {
 246    bool progress = false;
 247    src_reg *cur_value[virtual_grf_reg_count][4];
 248
 249    memset(&cur_value, 0, sizeof(cur_value));
 250
 251    foreach_list(node, &this->instructions) {
 252       vec4_instruction *inst = (vec4_instruction *)node;
 253
 254       /* This pass only works on basic blocks.  If there's flow
 255        * control, throw out all our information and start from
 256        * scratch.
 257        *
 258        * This should really be fixed by using a structure like in
 259        * src/glsl/opt_copy_propagation.cpp to track available copies.
 260        */
 261       if (!is_dominated_by_previous_instruction(inst)) {
 262          memset(cur_value, 0, sizeof(cur_value));
 263          continue;
 264       }
 265
 266       /* For each source arg, see if each component comes from a copy
 267        * from the same type file (IMM, GRF, UNIFORM), and try
 268        * optimizing out access to the copy result
 269        */
 270       for (int i = 2; i >= 0; i--) {
 271          /* Copied values end up in GRFs, and we don't track reladdr
 272           * accesses.
 273           */
 274          if (inst->src[i].file != GRF ||
 275              inst->src[i].reladdr)
 276             continue;
 277
 278          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 279                     inst->src[i].reg_offset);
 280
 281          /* Find the regs that each swizzle component came from.
 282           */
 283          src_reg *values[4];
 284          int c;
 285          for (c = 0; c < 4; c++) {
 286             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 287
 288             /* If there's no available copy for this channel, bail.
 289              * We could be more aggressive here -- some channels might
 290              * not get used based on the destination writemask.
 291              */
 292             if (!values[c])
 293                break;
 294
 295             /* We'll only be able to copy propagate if the sources are
 296              * all from the same file -- there's no ability to swizzle
 297              * 0 or 1 constants in with source registers like in i915.
 298              */
 299             if (c > 0 && values[c - 1]->file != values[c]->file)
 300                break;
 301          }
 302
 303          if (c != 4)
 304             continue;
 305
 306          if (try_constant_propagation(inst, i, values) ||
 307              try_copy_propagation(intel, inst, i, values))
 308             progress = true;
 309       }
 310
 311       /* Track available source registers. */
 312       if (inst->dst.file == GRF) {
 313          const int reg =
 314             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 315
 316          /* Update our destination's current channel values.  For a direct copy,
 317           * the value is the newly propagated source.  Otherwise, we don't know
 318           * the new value, so clear it.
 319           */
 320          bool direct_copy = is_direct_copy(inst);
 321          for (int i = 0; i < 4; i++) {
 322             if (inst->dst.writemask & (1 << i)) {
 323                cur_value[reg][i] = direct_copy ? &inst->src[0] : NULL;
 324             }
 325          }
 326
 327          /* Clear the records for any registers whose current value came from
 328           * our destination's updated channels, as the two are no longer equal.
 329           */
 330          if (inst->dst.reladdr)
 331             memset(cur_value, 0, sizeof(cur_value));
 332          else {
 333             for (int i = 0; i < virtual_grf_reg_count; i++) {
 334                for (int j = 0; j < 4; j++) {
 335                   if (inst->dst.writemask & (1 << j) &&
 336                       cur_value[i][j] &&
 337                       cur_value[i][j]->file == GRF &&
 338                       cur_value[i][j]->reg == inst->dst.reg &&
 339                       cur_value[i][j]->reg_offset == inst->dst.reg_offset) {
 340                      cur_value[i][j] = NULL;
 341                   }
 342                }
 343             }
 344          }
 345       }
 346    }
 347
 348    if (progress)
 349       live_intervals_valid = false;
 350
 351    return progress;
 352 }
 353
 354 } /* namespace brw */