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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
35 #include "main/macros.h"
46 is_direct_copy(vec4_instruction
*inst
)
48 return (inst
->opcode
== BRW_OPCODE_MOV
&&
50 inst
->dst
.file
== VGRF
&&
52 !inst
->src
[0].reladdr
&&
53 (inst
->dst
.type
== inst
->src
[0].type
||
54 (inst
->dst
.type
== BRW_REGISTER_TYPE_F
&&
55 inst
->src
[0].type
== BRW_REGISTER_TYPE_VF
)));
59 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
61 return (inst
->opcode
!= BRW_OPCODE_DO
&&
62 inst
->opcode
!= BRW_OPCODE_WHILE
&&
63 inst
->opcode
!= BRW_OPCODE_ELSE
&&
64 inst
->opcode
!= BRW_OPCODE_ENDIF
);
68 is_channel_updated(vec4_instruction
*inst
, src_reg
*values
[4], int ch
)
70 const src_reg
*src
= values
[ch
];
72 /* consider GRF only */
73 assert(inst
->dst
.file
== VGRF
);
74 if (!src
|| src
->file
!= VGRF
)
77 return (src
->in_range(inst
->dst
, inst
->regs_written
) &&
78 inst
->dst
.writemask
& (1 << BRW_GET_SWZ(src
->swizzle
, ch
)));
82 swizzle_vf_imm(unsigned vf4
, unsigned swizzle
)
89 ret
.vf
[0] = v
.vf
[BRW_GET_SWZ(swizzle
, 0)];
90 ret
.vf
[1] = v
.vf
[BRW_GET_SWZ(swizzle
, 1)];
91 ret
.vf
[2] = v
.vf
[BRW_GET_SWZ(swizzle
, 2)];
92 ret
.vf
[3] = v
.vf
[BRW_GET_SWZ(swizzle
, 3)];
98 is_logic_op(enum opcode opcode
)
100 return (opcode
== BRW_OPCODE_AND
||
101 opcode
== BRW_OPCODE_OR
||
102 opcode
== BRW_OPCODE_XOR
||
103 opcode
== BRW_OPCODE_NOT
);
107 try_constant_propagate(const struct brw_device_info
*devinfo
,
108 vec4_instruction
*inst
,
109 int arg
, struct copy_entry
*entry
)
111 /* For constant propagation, we only handle the same constant
112 * across all 4 channels. Some day, we should handle the 8-bit
113 * float vector format, which would let us constant propagate
116 src_reg value
= *entry
->value
[0];
117 for (int i
= 1; i
< 4; i
++) {
118 if (!value
.equals(*entry
->value
[i
]))
122 if (value
.file
!= IMM
)
125 if (value
.type
== BRW_REGISTER_TYPE_VF
) {
126 /* The result of bit-casting the component values of a vector float
127 * cannot in general be represented as an immediate.
129 if (inst
->src
[arg
].type
!= BRW_REGISTER_TYPE_F
)
132 value
.type
= inst
->src
[arg
].type
;
135 if (inst
->src
[arg
].abs
) {
136 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
137 !brw_abs_immediate(value
.type
, &value
.as_brw_reg())) {
142 if (inst
->src
[arg
].negate
) {
143 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
144 !brw_negate_immediate(value
.type
, &value
.as_brw_reg())) {
149 if (value
.type
== BRW_REGISTER_TYPE_VF
)
150 value
.ud
= swizzle_vf_imm(value
.ud
, inst
->src
[arg
].swizzle
);
152 switch (inst
->opcode
) {
154 case SHADER_OPCODE_BROADCAST
:
155 inst
->src
[arg
] = value
;
158 case SHADER_OPCODE_POW
:
159 case SHADER_OPCODE_INT_QUOTIENT
:
160 case SHADER_OPCODE_INT_REMAINDER
:
161 if (devinfo
->gen
< 8)
168 case BRW_OPCODE_BFI1
:
172 case BRW_OPCODE_SUBB
:
174 inst
->src
[arg
] = value
;
179 case BRW_OPCODE_MACH
:
181 case SHADER_OPCODE_MULH
:
186 case BRW_OPCODE_ADDC
:
188 inst
->src
[arg
] = value
;
190 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
191 /* Fit this constant in by commuting the operands. Exception: we
192 * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
194 if ((inst
->opcode
== BRW_OPCODE_MUL
||
195 inst
->opcode
== BRW_OPCODE_MACH
) &&
196 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
197 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
199 inst
->src
[0] = inst
->src
[1];
200 inst
->src
[1] = value
;
204 case GS_OPCODE_SET_WRITE_OFFSET
:
205 /* This is just a multiply by a constant with special strides.
206 * The generator will handle immediates in both arguments (generating
207 * a single MOV of the product). So feel free to propagate in src0.
209 inst
->src
[arg
] = value
;
214 inst
->src
[arg
] = value
;
216 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
217 enum brw_conditional_mod new_cmod
;
219 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
220 if (new_cmod
!= BRW_CONDITIONAL_NONE
) {
221 /* Fit this constant in by swapping the operands and
224 inst
->src
[0] = inst
->src
[1];
225 inst
->src
[1] = value
;
226 inst
->conditional_mod
= new_cmod
;
234 inst
->src
[arg
] = value
;
236 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
237 inst
->src
[0] = inst
->src
[1];
238 inst
->src
[1] = value
;
240 /* If this was predicated, flipping operands means
241 * we also need to flip the predicate.
243 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
244 inst
->predicate_inverse
= !inst
->predicate_inverse
;
258 try_copy_propagate(const struct brw_device_info
*devinfo
,
259 vec4_instruction
*inst
,
260 int arg
, struct copy_entry
*entry
)
262 /* Build up the value we are propagating as if it were the source of a
265 /* For constant propagation, we only handle the same constant
266 * across all 4 channels. Some day, we should handle the 8-bit
267 * float vector format, which would let us constant propagate
270 src_reg value
= *entry
->value
[0];
271 for (int i
= 1; i
< 4; i
++) {
272 /* This is equals() except we don't care about the swizzle. */
273 if (value
.file
!= entry
->value
[i
]->file
||
274 value
.nr
!= entry
->value
[i
]->nr
||
275 value
.reg_offset
!= entry
->value
[i
]->reg_offset
||
276 value
.type
!= entry
->value
[i
]->type
||
277 value
.negate
!= entry
->value
[i
]->negate
||
278 value
.abs
!= entry
->value
[i
]->abs
) {
283 /* Compute the swizzle of the original register by swizzling the
284 * component loaded from each value according to the swizzle of
285 * operand we're going to change.
288 for (int i
= 0; i
< 4; i
++) {
289 s
[i
] = BRW_GET_SWZ(entry
->value
[i
]->swizzle
, i
);
291 value
.swizzle
= BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]);
293 /* Check that we can propagate that value */
294 if (value
.file
!= UNIFORM
&&
295 value
.file
!= VGRF
&&
299 if (devinfo
->gen
>= 8 && (value
.negate
|| value
.abs
) &&
300 is_logic_op(inst
->opcode
)) {
304 bool has_source_modifiers
= value
.negate
|| value
.abs
;
306 /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
309 if ((has_source_modifiers
|| value
.file
== UNIFORM
||
310 value
.swizzle
!= BRW_SWIZZLE_XYZW
) && !inst
->can_do_source_mods(devinfo
))
313 if (has_source_modifiers
&&
314 value
.type
!= inst
->src
[arg
].type
&&
315 !inst
->can_change_types())
318 if (has_source_modifiers
&&
319 inst
->opcode
== SHADER_OPCODE_GEN4_SCRATCH_WRITE
)
322 unsigned composed_swizzle
= brw_compose_swizzle(inst
->src
[arg
].swizzle
,
324 if (inst
->is_3src() &&
325 value
.file
== UNIFORM
&&
326 !brw_is_single_value_swizzle(composed_swizzle
))
329 if (inst
->is_send_from_grf())
332 /* we can't generally copy-propagate UD negations becuse we
333 * end up accessing the resulting values as signed integers
334 * instead. See also resolve_ud_negate().
337 value
.type
== BRW_REGISTER_TYPE_UD
)
340 /* Don't report progress if this is a noop. */
341 if (value
.equals(inst
->src
[arg
]))
344 const unsigned dst_saturate_mask
= inst
->dst
.writemask
&
345 brw_apply_swizzle_to_mask(inst
->src
[arg
].swizzle
, entry
->saturatemask
);
347 if (dst_saturate_mask
) {
348 /* We either saturate all or nothing. */
349 if (dst_saturate_mask
!= inst
->dst
.writemask
)
352 /* Limit saturate propagation only to SEL with src1 bounded within 0.0
353 * and 1.0, otherwise skip copy propagate altogether.
355 switch(inst
->opcode
) {
358 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
359 inst
->src
[1].file
!= IMM
||
360 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
361 inst
->src
[1].f
< 0.0 ||
362 inst
->src
[1].f
> 1.0) {
366 inst
->saturate
= true;
373 /* Build the final value */
374 if (inst
->src
[arg
].abs
) {
375 value
.negate
= false;
378 if (inst
->src
[arg
].negate
)
379 value
.negate
= !value
.negate
;
381 value
.swizzle
= composed_swizzle
;
382 if (has_source_modifiers
&&
383 value
.type
!= inst
->src
[arg
].type
) {
384 assert(inst
->can_change_types());
385 for (int i
= 0; i
< 3; i
++) {
386 inst
->src
[i
].type
= value
.type
;
388 inst
->dst
.type
= value
.type
;
390 value
.type
= inst
->src
[arg
].type
;
393 inst
->src
[arg
] = value
;
398 vec4_visitor::opt_copy_propagation(bool do_constant_prop
)
400 bool progress
= false;
401 struct copy_entry entries
[alloc
.total_size
];
403 memset(&entries
, 0, sizeof(entries
));
405 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
406 /* This pass only works on basic blocks. If there's flow
407 * control, throw out all our information and start from
410 * This should really be fixed by using a structure like in
411 * src/glsl/opt_copy_propagation.cpp to track available copies.
413 if (!is_dominated_by_previous_instruction(inst
)) {
414 memset(&entries
, 0, sizeof(entries
));
418 /* For each source arg, see if each component comes from a copy
419 * from the same type file (IMM, VGRF, UNIFORM), and try
420 * optimizing out access to the copy result
422 for (int i
= 2; i
>= 0; i
--) {
423 /* Copied values end up in GRFs, and we don't track reladdr
426 if (inst
->src
[i
].file
!= VGRF
||
427 inst
->src
[i
].reladdr
)
430 /* We only handle single-register copies. */
431 if (inst
->regs_read(i
) != 1)
434 int reg
= (alloc
.offsets
[inst
->src
[i
].nr
] +
435 inst
->src
[i
].reg_offset
);
437 /* Find the regs that each swizzle component came from.
439 struct copy_entry entry
;
440 memset(&entry
, 0, sizeof(copy_entry
));
442 for (c
= 0; c
< 4; c
++) {
443 int channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
);
444 entry
.value
[c
] = entries
[reg
].value
[channel
];
446 /* If there's no available copy for this channel, bail.
447 * We could be more aggressive here -- some channels might
448 * not get used based on the destination writemask.
453 entry
.saturatemask
|=
454 (entries
[reg
].saturatemask
& (1 << channel
) ? 1 : 0) << c
;
456 /* We'll only be able to copy propagate if the sources are
457 * all from the same file -- there's no ability to swizzle
458 * 0 or 1 constants in with source registers like in i915.
460 if (c
> 0 && entry
.value
[c
- 1]->file
!= entry
.value
[c
]->file
)
467 if (do_constant_prop
&& try_constant_propagate(devinfo
, inst
, i
, &entry
))
470 if (try_copy_propagate(devinfo
, inst
, i
, &entry
))
474 /* Track available source registers. */
475 if (inst
->dst
.file
== VGRF
) {
477 alloc
.offsets
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
479 /* Update our destination's current channel values. For a direct copy,
480 * the value is the newly propagated source. Otherwise, we don't know
481 * the new value, so clear it.
483 bool direct_copy
= is_direct_copy(inst
);
484 entries
[reg
].saturatemask
&= ~inst
->dst
.writemask
;
485 for (int i
= 0; i
< 4; i
++) {
486 if (inst
->dst
.writemask
& (1 << i
)) {
487 entries
[reg
].value
[i
] = direct_copy
? &inst
->src
[0] : NULL
;
488 entries
[reg
].saturatemask
|=
489 inst
->saturate
&& direct_copy
? 1 << i
: 0;
493 /* Clear the records for any registers whose current value came from
494 * our destination's updated channels, as the two are no longer equal.
496 if (inst
->dst
.reladdr
)
497 memset(&entries
, 0, sizeof(entries
));
499 for (unsigned i
= 0; i
< alloc
.total_size
; i
++) {
500 for (int j
= 0; j
< 4; j
++) {
501 if (is_channel_updated(inst
, entries
[i
].value
, j
)) {
502 entries
[i
].value
[j
] = NULL
;
503 entries
[i
].saturatemask
&= ~(1 << j
);
512 invalidate_live_intervals();
517 } /* namespace brw */