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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
34 #include "main/macros.h"
40 is_direct_copy(vec4_instruction
*inst
)
42 return (inst
->opcode
== BRW_OPCODE_MOV
&&
44 inst
->dst
.file
== GRF
&&
47 !inst
->src
[0].reladdr
&&
48 inst
->dst
.type
== inst
->src
[0].type
);
52 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
54 return (inst
->opcode
!= BRW_OPCODE_DO
&&
55 inst
->opcode
!= BRW_OPCODE_WHILE
&&
56 inst
->opcode
!= BRW_OPCODE_ELSE
&&
57 inst
->opcode
!= BRW_OPCODE_ENDIF
);
61 try_constant_propagation(vec4_instruction
*inst
, int arg
, src_reg
*values
[4])
63 /* For constant propagation, we only handle the same constant
64 * across all 4 channels. Some day, we should handle the 8-bit
65 * float vector format, which would let us constant propagate
68 src_reg value
= *values
[0];
69 for (int i
= 1; i
< 4; i
++) {
70 if (!value
.equals(values
[i
]))
74 if (value
.file
!= IMM
)
77 if (inst
->src
[arg
].abs
) {
78 if (value
.type
== BRW_REGISTER_TYPE_F
) {
79 value
.imm
.f
= fabs(value
.imm
.f
);
80 } else if (value
.type
== BRW_REGISTER_TYPE_D
) {
82 value
.imm
.i
= -value
.imm
.i
;
86 if (inst
->src
[arg
].negate
) {
87 if (value
.type
== BRW_REGISTER_TYPE_F
)
88 value
.imm
.f
= -value
.imm
.f
;
90 value
.imm
.u
= -value
.imm
.u
;
93 switch (inst
->opcode
) {
95 inst
->src
[arg
] = value
;
101 inst
->src
[arg
] = value
;
103 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
104 /* Fit this constant in by commuting the operands */
105 inst
->src
[0] = inst
->src
[1];
106 inst
->src
[1] = value
;
113 inst
->src
[arg
] = value
;
115 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
118 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
119 if (new_cmod
!= ~0u) {
120 /* Fit this constant in by swapping the operands and
123 inst
->src
[0] = inst
->src
[1];
124 inst
->src
[1] = value
;
125 inst
->conditional_mod
= new_cmod
;
133 inst
->src
[arg
] = value
;
135 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
136 inst
->src
[0] = inst
->src
[1];
137 inst
->src
[1] = value
;
139 /* If this was predicated, flipping operands means
140 * we also need to flip the predicate.
142 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
143 inst
->predicate_inverse
= !inst
->predicate_inverse
;
157 try_copy_propagation(struct intel_context
*intel
,
158 vec4_instruction
*inst
, int arg
, src_reg
*values
[4])
160 /* For constant propagation, we only handle the same constant
161 * across all 4 channels. Some day, we should handle the 8-bit
162 * float vector format, which would let us constant propagate
165 src_reg value
= *values
[0];
166 for (int i
= 1; i
< 4; i
++) {
167 /* This is equals() except we don't care about the swizzle. */
168 if (value
.file
!= values
[i
]->file
||
169 value
.reg
!= values
[i
]->reg
||
170 value
.reg_offset
!= values
[i
]->reg_offset
||
171 value
.type
!= values
[i
]->type
||
172 value
.negate
!= values
[i
]->negate
||
173 value
.abs
!= values
[i
]->abs
) {
178 /* Compute the swizzle of the original register by swizzling the
179 * component loaded from each value according to the swizzle of
180 * operand we're going to change.
183 for (int i
= 0; i
< 4; i
++) {
184 s
[i
] = BRW_GET_SWZ(values
[i
]->swizzle
,
185 BRW_GET_SWZ(inst
->src
[arg
].swizzle
, i
));
187 value
.swizzle
= BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]);
189 if (value
.file
!= UNIFORM
&&
194 if (inst
->src
[arg
].abs
) {
195 value
.negate
= false;
198 if (inst
->src
[arg
].negate
)
199 value
.negate
= !value
.negate
;
201 /* FINISHME: We can't copy-propagate things that aren't normal
202 * vec8s into gen6 math instructions, because of the weird src
203 * handling for those instructions. Just ignore them for now.
205 if (intel
->gen
>= 6 && inst
->is_math())
208 /* We can't copy-propagate a UD negation into a condmod
209 * instruction, because the condmod ends up looking at the 33-bit
210 * signed accumulator value instead of the 32-bit value we wanted
212 if (inst
->conditional_mod
&&
214 value
.type
== BRW_REGISTER_TYPE_UD
)
217 /* Don't report progress if this is a noop. */
218 if (value
.equals(&inst
->src
[arg
]))
221 inst
->src
[arg
] = value
;
226 vec4_visitor::opt_copy_propagation()
228 bool progress
= false;
229 src_reg
*cur_value
[virtual_grf_reg_count
][4];
231 memset(&cur_value
, 0, sizeof(cur_value
));
233 foreach_list(node
, &this->instructions
) {
234 vec4_instruction
*inst
= (vec4_instruction
*)node
;
236 /* This pass only works on basic blocks. If there's flow
237 * control, throw out all our information and start from
240 * This should really be fixed by using a structure like in
241 * src/glsl/opt_copy_propagation.cpp to track available copies.
243 if (!is_dominated_by_previous_instruction(inst
)) {
244 memset(cur_value
, 0, sizeof(cur_value
));
248 /* For each source arg, see if each component comes from a copy
249 * from the same type file (IMM, GRF, UNIFORM), and try
250 * optimizing out access to the copy result
252 for (int i
= 2; i
>= 0; i
--) {
253 /* Copied values end up in GRFs, and we don't track reladdr
256 if (inst
->src
[i
].file
!= GRF
||
257 inst
->src
[i
].reladdr
)
260 int reg
= (virtual_grf_reg_map
[inst
->src
[i
].reg
] +
261 inst
->src
[i
].reg_offset
);
263 /* Find the regs that each swizzle component came from.
267 for (c
= 0; c
< 4; c
++) {
268 values
[c
] = cur_value
[reg
][BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)];
270 /* If there's no available copy for this channel, bail.
271 * We could be more aggressive here -- some channels might
272 * not get used based on the destination writemask.
277 /* We'll only be able to copy propagate if the sources are
278 * all from the same file -- there's no ability to swizzle
279 * 0 or 1 constants in with source registers like in i915.
281 if (c
> 0 && values
[c
- 1]->file
!= values
[c
]->file
)
288 if (try_constant_propagation(inst
, i
, values
) ||
289 try_copy_propagation(intel
, inst
, i
, values
))
293 /* Track available source registers. */
294 if (is_direct_copy(inst
)) {
295 int reg
= virtual_grf_reg_map
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
296 for (int i
= 0; i
< 4; i
++) {
297 if (inst
->dst
.writemask
& (1 << i
)) {
298 cur_value
[reg
][i
] = &inst
->src
[0];
304 /* For any updated channels, clear tracking of them as a source
307 if (inst
->dst
.file
== GRF
) {
308 if (inst
->dst
.reladdr
)
309 memset(cur_value
, 0, sizeof(cur_value
));
311 int reg
= virtual_grf_reg_map
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
313 for (int i
= 0; i
< 4; i
++) {
314 if (inst
->dst
.writemask
& (1 << i
))
315 cur_value
[reg
][i
] = NULL
;
318 for (int i
= 0; i
< virtual_grf_reg_count
; i
++) {
319 for (int j
= 0; j
< 4; j
++) {
320 if (inst
->dst
.writemask
& (1 << i
) &&
322 cur_value
[i
][j
]->file
== GRF
&&
323 cur_value
[i
][j
]->reg
== inst
->dst
.reg
&&
324 cur_value
[i
][j
]->reg_offset
== inst
->dst
.reg_offset
) {
325 cur_value
[i
][j
] = NULL
;
334 live_intervals_valid
= false;
339 } /* namespace brw */