src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 extern "C" {
  34 #include "main/macros.h"
  35 }
  36
  37 namespace brw {
  38
  39 static bool
  40 is_direct_copy(vec4_instruction *inst)
  41 {
  42    return (inst->opcode == BRW_OPCODE_MOV &&
  43            !inst->predicate &&
  44            inst->dst.file == GRF &&
  45            !inst->saturate &&
  46            !inst->dst.reladdr &&
  47            !inst->src[0].reladdr &&
  48            inst->dst.type == inst->src[0].type);
  49 }
  50
  51 static bool
  52 is_dominated_by_previous_instruction(vec4_instruction *inst)
  53 {
  54    return (inst->opcode != BRW_OPCODE_DO &&
  55            inst->opcode != BRW_OPCODE_WHILE &&
  56            inst->opcode != BRW_OPCODE_ELSE &&
  57            inst->opcode != BRW_OPCODE_ENDIF);
  58 }
  59
  60 static bool
  61 try_constant_propagation(vec4_instruction *inst, int arg, src_reg *values[4])
  62 {
  63    /* For constant propagation, we only handle the same constant
  64     * across all 4 channels.  Some day, we should handle the 8-bit
  65     * float vector format, which would let us constant propagate
  66     * vectors better.
  67     */
  68    src_reg value = *values[0];
  69    for (int i = 1; i < 4; i++) {
  70       if (!value.equals(values[i]))
  71          return false;
  72    }
  73
  74    if (value.file != IMM)
  75       return false;
  76
  77    if (inst->src[arg].abs) {
  78       if (value.type == BRW_REGISTER_TYPE_F) {
  79          value.imm.f = fabs(value.imm.f);
  80       } else if (value.type == BRW_REGISTER_TYPE_D) {
  81          if (value.imm.i < 0)
  82             value.imm.i = -value.imm.i;
  83       }
  84    }
  85
  86    if (inst->src[arg].negate) {
  87       if (value.type == BRW_REGISTER_TYPE_F)
  88          value.imm.f = -value.imm.f;
  89       else
  90          value.imm.u = -value.imm.u;
  91    }
  92
  93    switch (inst->opcode) {
  94    case BRW_OPCODE_MOV:
  95       inst->src[arg] = value;
  96       return true;
  97
  98    case BRW_OPCODE_MUL:
  99    case BRW_OPCODE_ADD:
 100       if (arg == 1) {
 101          inst->src[arg] = value;
 102          return true;
 103       } else if (arg == 0 && inst->src[1].file != IMM) {
 104          /* Fit this constant in by commuting the operands */
 105          inst->src[0] = inst->src[1];
 106          inst->src[1] = value;
 107          return true;
 108       }
 109       break;
 110
 111    case BRW_OPCODE_CMP:
 112       if (arg == 1) {
 113          inst->src[arg] = value;
 114          return true;
 115       } else if (arg == 0 && inst->src[1].file != IMM) {
 116          uint32_t new_cmod;
 117
 118          new_cmod = brw_swap_cmod(inst->conditional_mod);
 119          if (new_cmod != ~0u) {
 120             /* Fit this constant in by swapping the operands and
 121              * flipping the test.
 122              */
 123             inst->src[0] = inst->src[1];
 124             inst->src[1] = value;
 125             inst->conditional_mod = new_cmod;
 126             return true;
 127          }
 128       }
 129       break;
 130
 131    case BRW_OPCODE_SEL:
 132       if (arg == 1) {
 133          inst->src[arg] = value;
 134          return true;
 135       } else if (arg == 0 && inst->src[1].file != IMM) {
 136          inst->src[0] = inst->src[1];
 137          inst->src[1] = value;
 138
 139          /* If this was predicated, flipping operands means
 140           * we also need to flip the predicate.
 141           */
 142          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 143             inst->predicate_inverse = !inst->predicate_inverse;
 144          }
 145          return true;
 146       }
 147       break;
 148
 149    default:
 150       break;
 151    }
 152
 153    return false;
 154 }
 155
 156 static bool
 157 try_copy_propagation(struct intel_context *intel,
 158                      vec4_instruction *inst, int arg, src_reg *values[4])
 159 {
 160    /* For constant propagation, we only handle the same constant
 161     * across all 4 channels.  Some day, we should handle the 8-bit
 162     * float vector format, which would let us constant propagate
 163     * vectors better.
 164     */
 165    src_reg value = *values[0];
 166    for (int i = 1; i < 4; i++) {
 167       /* This is equals() except we don't care about the swizzle. */
 168       if (value.file != values[i]->file ||
 169           value.reg != values[i]->reg ||
 170           value.reg_offset != values[i]->reg_offset ||
 171           value.type != values[i]->type ||
 172           value.negate != values[i]->negate ||
 173           value.abs != values[i]->abs) {
 174          return false;
 175       }
 176    }
 177
 178    /* Compute the swizzle of the original register by swizzling the
 179     * component loaded from each value according to the swizzle of
 180     * operand we're going to change.
 181     */
 182    int s[4];
 183    for (int i = 0; i < 4; i++) {
 184       s[i] = BRW_GET_SWZ(values[i]->swizzle,
 185                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 186    }
 187    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 188
 189    if (value.file != UNIFORM &&
 190        value.file != GRF &&
 191        value.file != ATTR)
 192       return false;
 193
 194    if (inst->src[arg].abs) {
 195       value.negate = false;
 196       value.abs = true;
 197    }
 198    if (inst->src[arg].negate)
 199       value.negate = !value.negate;
 200
 201    /* FINISHME: We can't copy-propagate things that aren't normal
 202     * vec8s into gen6 math instructions, because of the weird src
 203     * handling for those instructions.  Just ignore them for now.
 204     */
 205    if (intel->gen >= 6 && inst->is_math())
 206       return false;
 207
 208    /* Don't report progress if this is a noop. */
 209    if (value.equals(&inst->src[arg]))
 210       return false;
 211
 212    inst->src[arg] = value;
 213    return true;
 214 }
 215
 216 bool
 217 vec4_visitor::opt_copy_propagation()
 218 {
 219    bool progress = false;
 220    src_reg *cur_value[virtual_grf_reg_count][4];
 221
 222    memset(&cur_value, 0, sizeof(cur_value));
 223
 224    foreach_list(node, &this->instructions) {
 225       vec4_instruction *inst = (vec4_instruction *)node;
 226
 227       /* This pass only works on basic blocks.  If there's flow
 228        * control, throw out all our information and start from
 229        * scratch.
 230        *
 231        * This should really be fixed by using a structure like in
 232        * src/glsl/opt_copy_propagation.cpp to track available copies.
 233        */
 234       if (!is_dominated_by_previous_instruction(inst)) {
 235          memset(cur_value, 0, sizeof(cur_value));
 236          continue;
 237       }
 238
 239       /* For each source arg, see if each component comes from a copy
 240        * from the same type file (IMM, GRF, UNIFORM), and try
 241        * optimizing out access to the copy result
 242        */
 243       for (int i = 2; i >= 0; i--) {
 244          /* Copied values end up in GRFs, and we don't track reladdr
 245           * accesses.
 246           */
 247          if (inst->src[i].file != GRF ||
 248              inst->src[i].reladdr)
 249             continue;
 250
 251          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 252                     inst->src[i].reg_offset);
 253
 254          /* Find the regs that each swizzle component came from.
 255           */
 256          src_reg *values[4];
 257          int c;
 258          for (c = 0; c < 4; c++) {
 259             values[c] = cur_value[reg][BRW_GET_SWZ(inst->src[i].swizzle, c)];
 260
 261             /* If there's no available copy for this channel, bail.
 262              * We could be more aggressive here -- some channels might
 263              * not get used based on the destination writemask.
 264              */
 265             if (!values[c])
 266                break;
 267
 268             /* We'll only be able to copy propagate if the sources are
 269              * all from the same file -- there's no ability to swizzle
 270              * 0 or 1 constants in with source registers like in i915.
 271              */
 272             if (c > 0 && values[c - 1]->file != values[c]->file)
 273                break;
 274          }
 275
 276          if (c != 4)
 277             continue;
 278
 279          if (try_constant_propagation(inst, i, values) ||
 280              try_copy_propagation(intel, inst, i, values))
 281             progress = true;
 282       }
 283
 284       /* Track available source registers. */
 285       if (is_direct_copy(inst)) {
 286          int reg = virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 287          for (int i = 0; i < 4; i++) {
 288             if (inst->dst.writemask & (1 << i)) {
 289                cur_value[reg][i] = &inst->src[0];
 290             }
 291          }
 292          continue;
 293       }
 294
 295       /* For any updated channels, clear tracking of them as a source
 296        * or destination.
 297        */
 298       if (inst->dst.file == GRF) {
 299          if (inst->dst.reladdr)
 300             memset(cur_value, 0, sizeof(cur_value));
 301          else {
 302             int reg = virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 303
 304             for (int i = 0; i < 4; i++) {
 305                if (inst->dst.writemask & (1 << i))
 306                   cur_value[reg][i] = NULL;
 307             }
 308
 309             for (int i = 0; i < virtual_grf_reg_count; i++) {
 310                for (int j = 0; j < 4; j++) {
 311                   if (inst->dst.writemask & (1 << i) &&
 312                       cur_value[i][j] &&
 313                       cur_value[i][j]->file == GRF &&
 314                       cur_value[i][j]->reg == inst->dst.reg &&
 315                       cur_value[i][j]->reg_offset == inst->dst.reg_offset) {
 316                      cur_value[i][j] = NULL;
 317                   }
 318                }
 319             }
 320          }
 321       }
 322    }
 323
 324    if (progress)
 325       live_intervals_valid = false;
 326
 327    return progress;
 328 }
 329
 330 } /* namespace brw */