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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
35 #include "main/macros.h"
46 is_direct_copy(vec4_instruction
*inst
)
48 return (inst
->opcode
== BRW_OPCODE_MOV
&&
50 inst
->dst
.file
== GRF
&&
52 !inst
->src
[0].reladdr
&&
53 (inst
->dst
.type
== inst
->src
[0].type
||
54 (inst
->dst
.type
== BRW_REGISTER_TYPE_F
&&
55 inst
->src
[0].type
== BRW_REGISTER_TYPE_VF
)));
59 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
61 return (inst
->opcode
!= BRW_OPCODE_DO
&&
62 inst
->opcode
!= BRW_OPCODE_WHILE
&&
63 inst
->opcode
!= BRW_OPCODE_ELSE
&&
64 inst
->opcode
!= BRW_OPCODE_ENDIF
);
68 is_channel_updated(vec4_instruction
*inst
, src_reg
*values
[4], int ch
)
70 const src_reg
*src
= values
[ch
];
72 /* consider GRF only */
73 assert(inst
->dst
.file
== GRF
);
74 if (!src
|| src
->file
!= GRF
)
77 return (src
->reg
== inst
->dst
.reg
&&
78 src
->reg_offset
== inst
->dst
.reg_offset
&&
79 inst
->dst
.writemask
& (1 << BRW_GET_SWZ(src
->swizzle
, ch
)));
83 swizzle_vf_imm(unsigned vf4
, unsigned swizzle
)
90 ret
.vf
[0] = v
.vf
[BRW_GET_SWZ(swizzle
, 0)];
91 ret
.vf
[1] = v
.vf
[BRW_GET_SWZ(swizzle
, 1)];
92 ret
.vf
[2] = v
.vf
[BRW_GET_SWZ(swizzle
, 2)];
93 ret
.vf
[3] = v
.vf
[BRW_GET_SWZ(swizzle
, 3)];
99 is_logic_op(enum opcode opcode
)
101 return (opcode
== BRW_OPCODE_AND
||
102 opcode
== BRW_OPCODE_OR
||
103 opcode
== BRW_OPCODE_XOR
||
104 opcode
== BRW_OPCODE_NOT
);
108 try_constant_propagate(struct brw_context
*brw
, vec4_instruction
*inst
,
109 int arg
, struct copy_entry
*entry
)
111 /* For constant propagation, we only handle the same constant
112 * across all 4 channels. Some day, we should handle the 8-bit
113 * float vector format, which would let us constant propagate
116 src_reg value
= *entry
->value
[0];
117 for (int i
= 1; i
< 4; i
++) {
118 if (!value
.equals(*entry
->value
[i
]))
122 if (value
.file
!= IMM
)
125 if (value
.type
== BRW_REGISTER_TYPE_VF
) {
126 /* The result of bit-casting the component values of a vector float
127 * cannot in general be represented as an immediate.
129 if (inst
->src
[arg
].type
!= BRW_REGISTER_TYPE_F
)
132 value
.type
= inst
->src
[arg
].type
;
135 if (inst
->src
[arg
].abs
) {
136 if ((brw
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
137 !brw_abs_immediate(value
.type
, &value
.fixed_hw_reg
)) {
142 if (inst
->src
[arg
].negate
) {
143 if ((brw
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
144 !brw_negate_immediate(value
.type
, &value
.fixed_hw_reg
)) {
149 if (value
.type
== BRW_REGISTER_TYPE_VF
)
150 value
.fixed_hw_reg
.dw1
.ud
= swizzle_vf_imm(value
.fixed_hw_reg
.dw1
.ud
,
151 inst
->src
[arg
].swizzle
);
153 switch (inst
->opcode
) {
155 inst
->src
[arg
] = value
;
158 case SHADER_OPCODE_POW
:
159 case SHADER_OPCODE_INT_QUOTIENT
:
160 case SHADER_OPCODE_INT_REMAINDER
:
168 case BRW_OPCODE_BFI1
:
172 case BRW_OPCODE_SUBB
:
174 inst
->src
[arg
] = value
;
179 case BRW_OPCODE_MACH
:
185 case BRW_OPCODE_ADDC
:
187 inst
->src
[arg
] = value
;
189 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
190 /* Fit this constant in by commuting the operands. Exception: we
191 * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
193 if ((inst
->opcode
== BRW_OPCODE_MUL
||
194 inst
->opcode
== BRW_OPCODE_MACH
) &&
195 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
196 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
198 inst
->src
[0] = inst
->src
[1];
199 inst
->src
[1] = value
;
206 inst
->src
[arg
] = value
;
208 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
209 enum brw_conditional_mod new_cmod
;
211 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
212 if (new_cmod
!= BRW_CONDITIONAL_NONE
) {
213 /* Fit this constant in by swapping the operands and
216 inst
->src
[0] = inst
->src
[1];
217 inst
->src
[1] = value
;
218 inst
->conditional_mod
= new_cmod
;
226 inst
->src
[arg
] = value
;
228 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
229 inst
->src
[0] = inst
->src
[1];
230 inst
->src
[1] = value
;
232 /* If this was predicated, flipping operands means
233 * we also need to flip the predicate.
235 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
236 inst
->predicate_inverse
= !inst
->predicate_inverse
;
250 try_copy_propagate(struct brw_context
*brw
, vec4_instruction
*inst
,
251 int arg
, struct copy_entry
*entry
)
253 /* For constant propagation, we only handle the same constant
254 * across all 4 channels. Some day, we should handle the 8-bit
255 * float vector format, which would let us constant propagate
258 src_reg value
= *entry
->value
[0];
259 for (int i
= 1; i
< 4; i
++) {
260 /* This is equals() except we don't care about the swizzle. */
261 if (value
.file
!= entry
->value
[i
]->file
||
262 value
.reg
!= entry
->value
[i
]->reg
||
263 value
.reg_offset
!= entry
->value
[i
]->reg_offset
||
264 value
.type
!= entry
->value
[i
]->type
||
265 value
.negate
!= entry
->value
[i
]->negate
||
266 value
.abs
!= entry
->value
[i
]->abs
) {
271 /* Compute the swizzle of the original register by swizzling the
272 * component loaded from each value according to the swizzle of
273 * operand we're going to change.
276 for (int i
= 0; i
< 4; i
++) {
277 s
[i
] = BRW_GET_SWZ(entry
->value
[i
]->swizzle
, i
);
279 value
.swizzle
= brw_compose_swizzle(inst
->src
[arg
].swizzle
,
280 BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]));
282 if (value
.file
!= UNIFORM
&&
287 if (brw
->gen
>= 8 && (value
.negate
|| value
.abs
) &&
288 is_logic_op(inst
->opcode
)) {
292 if (inst
->src
[arg
].abs
) {
293 value
.negate
= false;
296 if (inst
->src
[arg
].negate
)
297 value
.negate
= !value
.negate
;
299 bool has_source_modifiers
= value
.negate
|| value
.abs
;
301 /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
304 if ((has_source_modifiers
|| value
.file
== UNIFORM
||
305 value
.swizzle
!= BRW_SWIZZLE_XYZW
) && !inst
->can_do_source_mods(brw
))
308 if (has_source_modifiers
&& value
.type
!= inst
->src
[arg
].type
)
311 if (has_source_modifiers
&&
312 inst
->opcode
== SHADER_OPCODE_GEN4_SCRATCH_WRITE
)
315 if (inst
->is_3src() && value
.file
== UNIFORM
)
318 if (inst
->is_send_from_grf())
321 /* we can't generally copy-propagate UD negations becuse we
322 * end up accessing the resulting values as signed integers
323 * instead. See also resolve_ud_negate().
326 value
.type
== BRW_REGISTER_TYPE_UD
)
329 /* Don't report progress if this is a noop. */
330 if (value
.equals(inst
->src
[arg
]))
333 /* Limit saturate propagation only to SEL with src1 bounded within 1.0 and 1.0
334 * otherwise, skip copy propagate altogether
336 if (entry
->saturatemask
& (1 << arg
)) {
337 switch(inst
->opcode
) {
339 if (inst
->src
[1].file
!= IMM
||
340 inst
->src
[1].fixed_hw_reg
.dw1
.f
< 0.0 ||
341 inst
->src
[1].fixed_hw_reg
.dw1
.f
> 1.0) {
345 inst
->saturate
= true;
352 value
.type
= inst
->src
[arg
].type
;
353 inst
->src
[arg
] = value
;
358 vec4_visitor::opt_copy_propagation(bool do_constant_prop
)
360 bool progress
= false;
361 struct copy_entry entries
[alloc
.total_size
];
363 memset(&entries
, 0, sizeof(entries
));
365 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
366 /* This pass only works on basic blocks. If there's flow
367 * control, throw out all our information and start from
370 * This should really be fixed by using a structure like in
371 * src/glsl/opt_copy_propagation.cpp to track available copies.
373 if (!is_dominated_by_previous_instruction(inst
)) {
374 memset(&entries
, 0, sizeof(entries
));
378 /* For each source arg, see if each component comes from a copy
379 * from the same type file (IMM, GRF, UNIFORM), and try
380 * optimizing out access to the copy result
382 for (int i
= 2; i
>= 0; i
--) {
383 /* Copied values end up in GRFs, and we don't track reladdr
386 if (inst
->src
[i
].file
!= GRF
||
387 inst
->src
[i
].reladdr
)
390 int reg
= (alloc
.offsets
[inst
->src
[i
].reg
] +
391 inst
->src
[i
].reg_offset
);
393 /* Find the regs that each swizzle component came from.
395 struct copy_entry entry
;
396 memset(&entry
, 0, sizeof(copy_entry
));
398 for (c
= 0; c
< 4; c
++) {
399 int channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
);
400 entry
.value
[c
] = entries
[reg
].value
[channel
];
402 /* If there's no available copy for this channel, bail.
403 * We could be more aggressive here -- some channels might
404 * not get used based on the destination writemask.
409 entry
.saturatemask
|=
410 (entries
[reg
].saturatemask
& (1 << channel
) ? 1 : 0) << c
;
412 /* We'll only be able to copy propagate if the sources are
413 * all from the same file -- there's no ability to swizzle
414 * 0 or 1 constants in with source registers like in i915.
416 if (c
> 0 && entry
.value
[c
- 1]->file
!= entry
.value
[c
]->file
)
423 if (do_constant_prop
&& try_constant_propagate(brw
, inst
, i
, &entry
))
426 if (try_copy_propagate(brw
, inst
, i
, &entry
))
430 /* Track available source registers. */
431 if (inst
->dst
.file
== GRF
) {
433 alloc
.offsets
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
435 /* Update our destination's current channel values. For a direct copy,
436 * the value is the newly propagated source. Otherwise, we don't know
437 * the new value, so clear it.
439 bool direct_copy
= is_direct_copy(inst
);
440 entries
[reg
].saturatemask
= 0x0;
441 for (int i
= 0; i
< 4; i
++) {
442 if (inst
->dst
.writemask
& (1 << i
)) {
443 entries
[reg
].value
[i
] = (!inst
->saturate
&& direct_copy
) ? &inst
->src
[0] : NULL
;
444 entries
[reg
].saturatemask
|= (((inst
->saturate
&& direct_copy
) ? 1 : 0) << i
);
448 /* Clear the records for any registers whose current value came from
449 * our destination's updated channels, as the two are no longer equal.
451 if (inst
->dst
.reladdr
)
452 memset(&entries
, 0, sizeof(entries
));
454 for (unsigned i
= 0; i
< alloc
.total_size
; i
++) {
455 for (int j
= 0; j
< 4; j
++) {
456 if (is_channel_updated(inst
, entries
[i
].value
, j
)){
457 entries
[i
].value
[j
] = NULL
;
458 entries
[i
].saturatemask
&= ~(1 << j
);
467 invalidate_live_intervals();
472 } /* namespace brw */