src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 #include "brw_cfg.h"
  34 extern "C" {
  35 #include "main/macros.h"
  36 }
  37
  38 namespace brw {
  39
  40 struct copy_entry {
  41    src_reg *value[4];
  42    int saturatemask;
  43 };
  44
  45 static bool
  46 is_direct_copy(vec4_instruction *inst)
  47 {
  48    return (inst->opcode == BRW_OPCODE_MOV &&
  49            !inst->predicate &&
  50            inst->dst.file == GRF &&
  51            !inst->dst.reladdr &&
  52            !inst->src[0].reladdr &&
  53            (inst->dst.type == inst->src[0].type ||
  54             (inst->dst.type == BRW_REGISTER_TYPE_F &&
  55              inst->src[0].type == BRW_REGISTER_TYPE_VF)));
  56 }
  57
  58 static bool
  59 is_dominated_by_previous_instruction(vec4_instruction *inst)
  60 {
  61    return (inst->opcode != BRW_OPCODE_DO &&
  62            inst->opcode != BRW_OPCODE_WHILE &&
  63            inst->opcode != BRW_OPCODE_ELSE &&
  64            inst->opcode != BRW_OPCODE_ENDIF);
  65 }
  66
  67 static bool
  68 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  69 {
  70    const src_reg *src = values[ch];
  71
  72    /* consider GRF only */
  73    assert(inst->dst.file == GRF);
  74    if (!src || src->file != GRF)
  75       return false;
  76
  77    return (src->in_range(inst->dst, inst->regs_written) &&
  78            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  79 }
  80
  81 static unsigned
  82 swizzle_vf_imm(unsigned vf4, unsigned swizzle)
  83 {
  84    union {
  85       unsigned vf4;
  86       uint8_t vf[4];
  87    } v = { vf4 }, ret;
  88
  89    ret.vf[0] = v.vf[BRW_GET_SWZ(swizzle, 0)];
  90    ret.vf[1] = v.vf[BRW_GET_SWZ(swizzle, 1)];
  91    ret.vf[2] = v.vf[BRW_GET_SWZ(swizzle, 2)];
  92    ret.vf[3] = v.vf[BRW_GET_SWZ(swizzle, 3)];
  93
  94    return ret.vf4;
  95 }
  96
  97 static bool
  98 is_logic_op(enum opcode opcode)
  99 {
 100    return (opcode == BRW_OPCODE_AND ||
 101            opcode == BRW_OPCODE_OR  ||
 102            opcode == BRW_OPCODE_XOR ||
 103            opcode == BRW_OPCODE_NOT);
 104 }
 105
 106 static bool
 107 try_constant_propagate(const struct brw_device_info *devinfo,
 108                        vec4_instruction *inst,
 109                        int arg, struct copy_entry *entry)
 110 {
 111    /* For constant propagation, we only handle the same constant
 112     * across all 4 channels.  Some day, we should handle the 8-bit
 113     * float vector format, which would let us constant propagate
 114     * vectors better.
 115     */
 116    src_reg value = *entry->value[0];
 117    for (int i = 1; i < 4; i++) {
 118       if (!value.equals(*entry->value[i]))
 119          return false;
 120    }
 121
 122    if (value.file != IMM)
 123       return false;
 124
 125    if (value.type == BRW_REGISTER_TYPE_VF) {
 126       /* The result of bit-casting the component values of a vector float
 127        * cannot in general be represented as an immediate.
 128        */
 129       if (inst->src[arg].type != BRW_REGISTER_TYPE_F)
 130          return false;
 131    } else {
 132       value.type = inst->src[arg].type;
 133    }
 134
 135    if (inst->src[arg].abs) {
 136       if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
 137           !brw_abs_immediate(value.type, &value)) {
 138          return false;
 139       }
 140    }
 141
 142    if (inst->src[arg].negate) {
 143       if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
 144           !brw_negate_immediate(value.type, &value)) {
 145          return false;
 146       }
 147    }
 148
 149    if (value.type == BRW_REGISTER_TYPE_VF)
 150       value.ud = swizzle_vf_imm(value.ud, inst->src[arg].swizzle);
 151
 152    switch (inst->opcode) {
 153    case BRW_OPCODE_MOV:
 154    case SHADER_OPCODE_BROADCAST:
 155       inst->src[arg] = value;
 156       return true;
 157
 158    case SHADER_OPCODE_POW:
 159    case SHADER_OPCODE_INT_QUOTIENT:
 160    case SHADER_OPCODE_INT_REMAINDER:
 161       if (devinfo->gen < 8)
 162          break;
 163       /* fallthrough */
 164    case BRW_OPCODE_DP2:
 165    case BRW_OPCODE_DP3:
 166    case BRW_OPCODE_DP4:
 167    case BRW_OPCODE_DPH:
 168    case BRW_OPCODE_BFI1:
 169    case BRW_OPCODE_ASR:
 170    case BRW_OPCODE_SHL:
 171    case BRW_OPCODE_SHR:
 172    case BRW_OPCODE_SUBB:
 173       if (arg == 1) {
 174          inst->src[arg] = value;
 175          return true;
 176       }
 177       break;
 178
 179    case BRW_OPCODE_MACH:
 180    case BRW_OPCODE_MUL:
 181    case SHADER_OPCODE_MULH:
 182    case BRW_OPCODE_ADD:
 183    case BRW_OPCODE_OR:
 184    case BRW_OPCODE_AND:
 185    case BRW_OPCODE_XOR:
 186    case BRW_OPCODE_ADDC:
 187       if (arg == 1) {
 188          inst->src[arg] = value;
 189          return true;
 190       } else if (arg == 0 && inst->src[1].file != IMM) {
 191          /* Fit this constant in by commuting the operands.  Exception: we
 192           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 193           */
 194          if ((inst->opcode == BRW_OPCODE_MUL ||
 195               inst->opcode == BRW_OPCODE_MACH) &&
 196              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 197               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 198             break;
 199          inst->src[0] = inst->src[1];
 200          inst->src[1] = value;
 201          return true;
 202       }
 203       break;
 204    case GS_OPCODE_SET_WRITE_OFFSET:
 205       /* This is just a multiply by a constant with special strides.
 206        * The generator will handle immediates in both arguments (generating
 207        * a single MOV of the product).  So feel free to propagate in src0.
 208        */
 209       inst->src[arg] = value;
 210       return true;
 211
 212    case BRW_OPCODE_CMP:
 213       if (arg == 1) {
 214          inst->src[arg] = value;
 215          return true;
 216       } else if (arg == 0 && inst->src[1].file != IMM) {
 217          enum brw_conditional_mod new_cmod;
 218
 219          new_cmod = brw_swap_cmod(inst->conditional_mod);
 220          if (new_cmod != BRW_CONDITIONAL_NONE) {
 221             /* Fit this constant in by swapping the operands and
 222              * flipping the test.
 223              */
 224             inst->src[0] = inst->src[1];
 225             inst->src[1] = value;
 226             inst->conditional_mod = new_cmod;
 227             return true;
 228          }
 229       }
 230       break;
 231
 232    case BRW_OPCODE_SEL:
 233       if (arg == 1) {
 234          inst->src[arg] = value;
 235          return true;
 236       } else if (arg == 0 && inst->src[1].file != IMM) {
 237          inst->src[0] = inst->src[1];
 238          inst->src[1] = value;
 239
 240          /* If this was predicated, flipping operands means
 241           * we also need to flip the predicate.
 242           */
 243          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 244             inst->predicate_inverse = !inst->predicate_inverse;
 245          }
 246          return true;
 247       }
 248       break;
 249
 250    default:
 251       break;
 252    }
 253
 254    return false;
 255 }
 256
 257 static bool
 258 try_copy_propagate(const struct brw_device_info *devinfo,
 259                    vec4_instruction *inst,
 260                    int arg, struct copy_entry *entry)
 261 {
 262    /* Build up the value we are propagating as if it were the source of a
 263     * single MOV
 264     */
 265    /* For constant propagation, we only handle the same constant
 266     * across all 4 channels.  Some day, we should handle the 8-bit
 267     * float vector format, which would let us constant propagate
 268     * vectors better.
 269     */
 270    src_reg value = *entry->value[0];
 271    for (int i = 1; i < 4; i++) {
 272       /* This is equals() except we don't care about the swizzle. */
 273       if (value.file != entry->value[i]->file ||
 274           value.nr != entry->value[i]->nr ||
 275           value.reg_offset != entry->value[i]->reg_offset ||
 276           value.type != entry->value[i]->type ||
 277           value.negate != entry->value[i]->negate ||
 278           value.abs != entry->value[i]->abs) {
 279          return false;
 280       }
 281    }
 282
 283    /* Compute the swizzle of the original register by swizzling the
 284     * component loaded from each value according to the swizzle of
 285     * operand we're going to change.
 286     */
 287    int s[4];
 288    for (int i = 0; i < 4; i++) {
 289       s[i] = BRW_GET_SWZ(entry->value[i]->swizzle, i);
 290    }
 291    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 292
 293    /* Check that we can propagate that value */
 294    if (value.file != UNIFORM &&
 295        value.file != GRF &&
 296        value.file != ATTR)
 297       return false;
 298
 299    if (devinfo->gen >= 8 && (value.negate || value.abs) &&
 300        is_logic_op(inst->opcode)) {
 301       return false;
 302    }
 303
 304    bool has_source_modifiers = value.negate || value.abs;
 305
 306    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 307     * instructions.
 308     */
 309    if ((has_source_modifiers || value.file == UNIFORM ||
 310         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(devinfo))
 311       return false;
 312
 313    if (has_source_modifiers &&
 314        value.type != inst->src[arg].type &&
 315        !inst->can_change_types())
 316       return false;
 317
 318    if (has_source_modifiers &&
 319        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
 320       return false;
 321
 322    unsigned composed_swizzle = brw_compose_swizzle(inst->src[arg].swizzle,
 323                                                    value.swizzle);
 324    if (inst->is_3src() &&
 325        value.file == UNIFORM &&
 326        !brw_is_single_value_swizzle(composed_swizzle))
 327       return false;
 328
 329    if (inst->is_send_from_grf())
 330       return false;
 331
 332    /* we can't generally copy-propagate UD negations becuse we
 333     * end up accessing the resulting values as signed integers
 334     * instead. See also resolve_ud_negate().
 335     */
 336    if (value.negate &&
 337        value.type == BRW_REGISTER_TYPE_UD)
 338       return false;
 339
 340    /* Don't report progress if this is a noop. */
 341    if (value.equals(inst->src[arg]))
 342       return false;
 343
 344    const unsigned dst_saturate_mask = inst->dst.writemask &
 345       brw_apply_swizzle_to_mask(inst->src[arg].swizzle, entry->saturatemask);
 346
 347    if (dst_saturate_mask) {
 348       /* We either saturate all or nothing. */
 349       if (dst_saturate_mask != inst->dst.writemask)
 350          return false;
 351
 352       /* Limit saturate propagation only to SEL with src1 bounded within 0.0
 353        * and 1.0, otherwise skip copy propagate altogether.
 354        */
 355       switch(inst->opcode) {
 356       case BRW_OPCODE_SEL:
 357          if (arg != 0 ||
 358              inst->src[0].type != BRW_REGISTER_TYPE_F ||
 359              inst->src[1].file != IMM ||
 360              inst->src[1].type != BRW_REGISTER_TYPE_F ||
 361              inst->src[1].f < 0.0 ||
 362              inst->src[1].f > 1.0) {
 363             return false;
 364          }
 365          if (!inst->saturate)
 366             inst->saturate = true;
 367          break;
 368       default:
 369          return false;
 370       }
 371    }
 372
 373    /* Build the final value */
 374    if (inst->src[arg].abs) {
 375       value.negate = false;
 376       value.abs = true;
 377    }
 378    if (inst->src[arg].negate)
 379       value.negate = !value.negate;
 380
 381    value.swizzle = composed_swizzle;
 382    if (has_source_modifiers &&
 383        value.type != inst->src[arg].type) {
 384       assert(inst->can_change_types());
 385       for (int i = 0; i < 3; i++) {
 386          inst->src[i].type = value.type;
 387       }
 388       inst->dst.type = value.type;
 389    } else {
 390       value.type = inst->src[arg].type;
 391    }
 392
 393    inst->src[arg] = value;
 394    return true;
 395 }
 396
 397 bool
 398 vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 399 {
 400    bool progress = false;
 401    struct copy_entry entries[alloc.total_size];
 402
 403    memset(&entries, 0, sizeof(entries));
 404
 405    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 406       /* This pass only works on basic blocks.  If there's flow
 407        * control, throw out all our information and start from
 408        * scratch.
 409        *
 410        * This should really be fixed by using a structure like in
 411        * src/glsl/opt_copy_propagation.cpp to track available copies.
 412        */
 413       if (!is_dominated_by_previous_instruction(inst)) {
 414          memset(&entries, 0, sizeof(entries));
 415          continue;
 416       }
 417
 418       /* For each source arg, see if each component comes from a copy
 419        * from the same type file (IMM, GRF, UNIFORM), and try
 420        * optimizing out access to the copy result
 421        */
 422       for (int i = 2; i >= 0; i--) {
 423          /* Copied values end up in GRFs, and we don't track reladdr
 424           * accesses.
 425           */
 426          if (inst->src[i].file != GRF ||
 427              inst->src[i].reladdr)
 428             continue;
 429
 430          /* We only handle single-register copies. */
 431          if (inst->regs_read(i) != 1)
 432             continue;
 433
 434          int reg = (alloc.offsets[inst->src[i].nr] +
 435                     inst->src[i].reg_offset);
 436
 437          /* Find the regs that each swizzle component came from.
 438           */
 439          struct copy_entry entry;
 440          memset(&entry, 0, sizeof(copy_entry));
 441          int c;
 442          for (c = 0; c < 4; c++) {
 443             int channel = BRW_GET_SWZ(inst->src[i].swizzle, c);
 444             entry.value[c] = entries[reg].value[channel];
 445
 446             /* If there's no available copy for this channel, bail.
 447              * We could be more aggressive here -- some channels might
 448              * not get used based on the destination writemask.
 449              */
 450             if (!entry.value[c])
 451                break;
 452
 453             entry.saturatemask |=
 454                (entries[reg].saturatemask & (1 << channel) ? 1 : 0) << c;
 455
 456             /* We'll only be able to copy propagate if the sources are
 457              * all from the same file -- there's no ability to swizzle
 458              * 0 or 1 constants in with source registers like in i915.
 459              */
 460             if (c > 0 && entry.value[c - 1]->file != entry.value[c]->file)
 461                break;
 462          }
 463
 464          if (c != 4)
 465             continue;
 466
 467          if (do_constant_prop && try_constant_propagate(devinfo, inst, i, &entry))
 468             progress = true;
 469
 470          if (try_copy_propagate(devinfo, inst, i, &entry))
 471             progress = true;
 472       }
 473
 474       /* Track available source registers. */
 475       if (inst->dst.file == GRF) {
 476          const int reg =
 477             alloc.offsets[inst->dst.nr] + inst->dst.reg_offset;
 478
 479          /* Update our destination's current channel values.  For a direct copy,
 480           * the value is the newly propagated source.  Otherwise, we don't know
 481           * the new value, so clear it.
 482           */
 483          bool direct_copy = is_direct_copy(inst);
 484          entries[reg].saturatemask &= ~inst->dst.writemask;
 485          for (int i = 0; i < 4; i++) {
 486             if (inst->dst.writemask & (1 << i)) {
 487                entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
 488                entries[reg].saturatemask |=
 489                   inst->saturate && direct_copy ? 1 << i : 0;
 490             }
 491          }
 492
 493          /* Clear the records for any registers whose current value came from
 494           * our destination's updated channels, as the two are no longer equal.
 495           */
 496          if (inst->dst.reladdr)
 497             memset(&entries, 0, sizeof(entries));
 498          else {
 499             for (unsigned i = 0; i < alloc.total_size; i++) {
 500                for (int j = 0; j < 4; j++) {
 501                   if (is_channel_updated(inst, entries[i].value, j)) {
 502                      entries[i].value[j] = NULL;
 503                      entries[i].saturatemask &= ~(1 << j);
 504                   }
 505                }
 506             }
 507          }
 508       }
 509    }
 510
 511    if (progress)
 512       invalidate_live_intervals();
 513
 514    return progress;
 515 }
 516
 517 } /* namespace brw */