src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 #include "brw_cfg.h"
  34 extern "C" {
  35 #include "main/macros.h"
  36 }
  37
  38 namespace brw {
  39
  40 struct copy_entry {
  41    src_reg *value[4];
  42    int saturatemask;
  43 };
  44
  45 static bool
  46 is_direct_copy(vec4_instruction *inst)
  47 {
  48    return (inst->opcode == BRW_OPCODE_MOV &&
  49            !inst->predicate &&
  50            inst->dst.file == GRF &&
  51            !inst->dst.reladdr &&
  52            !inst->src[0].reladdr &&
  53            (inst->dst.type == inst->src[0].type ||
  54             (inst->dst.type == BRW_REGISTER_TYPE_F &&
  55              inst->src[0].type == BRW_REGISTER_TYPE_VF)));
  56 }
  57
  58 static bool
  59 is_dominated_by_previous_instruction(vec4_instruction *inst)
  60 {
  61    return (inst->opcode != BRW_OPCODE_DO &&
  62            inst->opcode != BRW_OPCODE_WHILE &&
  63            inst->opcode != BRW_OPCODE_ELSE &&
  64            inst->opcode != BRW_OPCODE_ENDIF);
  65 }
  66
  67 static bool
  68 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  69 {
  70    const src_reg *src = values[ch];
  71
  72    /* consider GRF only */
  73    assert(inst->dst.file == GRF);
  74    if (!src || src->file != GRF)
  75       return false;
  76
  77    return (src->reg == inst->dst.reg &&
  78            src->reg_offset == inst->dst.reg_offset &&
  79            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  80 }
  81
  82 static unsigned
  83 swizzle_vf_imm(unsigned vf4, unsigned swizzle)
  84 {
  85    union {
  86       unsigned vf4;
  87       uint8_t vf[4];
  88    } v = { vf4 }, ret;
  89
  90    ret.vf[0] = v.vf[BRW_GET_SWZ(swizzle, 0)];
  91    ret.vf[1] = v.vf[BRW_GET_SWZ(swizzle, 1)];
  92    ret.vf[2] = v.vf[BRW_GET_SWZ(swizzle, 2)];
  93    ret.vf[3] = v.vf[BRW_GET_SWZ(swizzle, 3)];
  94
  95    return ret.vf4;
  96 }
  97
  98 static bool
  99 is_logic_op(enum opcode opcode)
 100 {
 101    return (opcode == BRW_OPCODE_AND ||
 102            opcode == BRW_OPCODE_OR  ||
 103            opcode == BRW_OPCODE_XOR ||
 104            opcode == BRW_OPCODE_NOT);
 105 }
 106
 107 static bool
 108 try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
 109                        int arg, struct copy_entry *entry)
 110 {
 111    /* For constant propagation, we only handle the same constant
 112     * across all 4 channels.  Some day, we should handle the 8-bit
 113     * float vector format, which would let us constant propagate
 114     * vectors better.
 115     */
 116    src_reg value = *entry->value[0];
 117    for (int i = 1; i < 4; i++) {
 118       if (!value.equals(*entry->value[i]))
 119          return false;
 120    }
 121
 122    if (value.file != IMM)
 123       return false;
 124
 125    if (value.type == BRW_REGISTER_TYPE_VF) {
 126       /* The result of bit-casting the component values of a vector float
 127        * cannot in general be represented as an immediate.
 128        */
 129       if (inst->src[arg].type != BRW_REGISTER_TYPE_F)
 130          return false;
 131    } else {
 132       value.type = inst->src[arg].type;
 133    }
 134
 135    if (inst->src[arg].abs) {
 136       if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
 137           !brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
 138          return false;
 139       }
 140    }
 141
 142    if (inst->src[arg].negate) {
 143       if ((brw->gen >= 8 && is_logic_op(inst->opcode)) ||
 144           !brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
 145          return false;
 146       }
 147    }
 148
 149    if (value.type == BRW_REGISTER_TYPE_VF)
 150       value.fixed_hw_reg.dw1.ud = swizzle_vf_imm(value.fixed_hw_reg.dw1.ud,
 151                                                  inst->src[arg].swizzle);
 152
 153    switch (inst->opcode) {
 154    case BRW_OPCODE_MOV:
 155       inst->src[arg] = value;
 156       return true;
 157
 158    case SHADER_OPCODE_POW:
 159    case SHADER_OPCODE_INT_QUOTIENT:
 160    case SHADER_OPCODE_INT_REMAINDER:
 161       if (brw->gen < 8)
 162          break;
 163       /* fallthrough */
 164    case BRW_OPCODE_DP2:
 165    case BRW_OPCODE_DP3:
 166    case BRW_OPCODE_DP4:
 167    case BRW_OPCODE_DPH:
 168    case BRW_OPCODE_BFI1:
 169    case BRW_OPCODE_ASR:
 170    case BRW_OPCODE_SHL:
 171    case BRW_OPCODE_SHR:
 172    case BRW_OPCODE_SUBB:
 173       if (arg == 1) {
 174          inst->src[arg] = value;
 175          return true;
 176       }
 177       break;
 178
 179    case BRW_OPCODE_MACH:
 180    case BRW_OPCODE_MUL:
 181    case BRW_OPCODE_ADD:
 182    case BRW_OPCODE_OR:
 183    case BRW_OPCODE_AND:
 184    case BRW_OPCODE_XOR:
 185    case BRW_OPCODE_ADDC:
 186       if (arg == 1) {
 187          inst->src[arg] = value;
 188          return true;
 189       } else if (arg == 0 && inst->src[1].file != IMM) {
 190          /* Fit this constant in by commuting the operands.  Exception: we
 191           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 192           */
 193          if ((inst->opcode == BRW_OPCODE_MUL ||
 194               inst->opcode == BRW_OPCODE_MACH) &&
 195              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 196               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 197             break;
 198          inst->src[0] = inst->src[1];
 199          inst->src[1] = value;
 200          return true;
 201       }
 202       break;
 203
 204    case BRW_OPCODE_CMP:
 205       if (arg == 1) {
 206          inst->src[arg] = value;
 207          return true;
 208       } else if (arg == 0 && inst->src[1].file != IMM) {
 209          enum brw_conditional_mod new_cmod;
 210
 211          new_cmod = brw_swap_cmod(inst->conditional_mod);
 212          if (new_cmod != BRW_CONDITIONAL_NONE) {
 213             /* Fit this constant in by swapping the operands and
 214              * flipping the test.
 215              */
 216             inst->src[0] = inst->src[1];
 217             inst->src[1] = value;
 218             inst->conditional_mod = new_cmod;
 219             return true;
 220          }
 221       }
 222       break;
 223
 224    case BRW_OPCODE_SEL:
 225       if (arg == 1) {
 226          inst->src[arg] = value;
 227          return true;
 228       } else if (arg == 0 && inst->src[1].file != IMM) {
 229          inst->src[0] = inst->src[1];
 230          inst->src[1] = value;
 231
 232          /* If this was predicated, flipping operands means
 233           * we also need to flip the predicate.
 234           */
 235          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 236             inst->predicate_inverse = !inst->predicate_inverse;
 237          }
 238          return true;
 239       }
 240       break;
 241
 242    default:
 243       break;
 244    }
 245
 246    return false;
 247 }
 248
 249 static bool
 250 try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
 251                    int arg, struct copy_entry *entry)
 252 {
 253    /* For constant propagation, we only handle the same constant
 254     * across all 4 channels.  Some day, we should handle the 8-bit
 255     * float vector format, which would let us constant propagate
 256     * vectors better.
 257     */
 258    src_reg value = *entry->value[0];
 259    for (int i = 1; i < 4; i++) {
 260       /* This is equals() except we don't care about the swizzle. */
 261       if (value.file != entry->value[i]->file ||
 262           value.reg != entry->value[i]->reg ||
 263           value.reg_offset != entry->value[i]->reg_offset ||
 264           value.type != entry->value[i]->type ||
 265           value.negate != entry->value[i]->negate ||
 266           value.abs != entry->value[i]->abs) {
 267          return false;
 268       }
 269    }
 270
 271    /* Compute the swizzle of the original register by swizzling the
 272     * component loaded from each value according to the swizzle of
 273     * operand we're going to change.
 274     */
 275    int s[4];
 276    for (int i = 0; i < 4; i++) {
 277       s[i] = BRW_GET_SWZ(entry->value[i]->swizzle, i);
 278    }
 279    value.swizzle = brw_compose_swizzle(inst->src[arg].swizzle,
 280                                        BRW_SWIZZLE4(s[0], s[1], s[2], s[3]));
 281
 282    if (value.file != UNIFORM &&
 283        value.file != GRF &&
 284        value.file != ATTR)
 285       return false;
 286
 287    if (brw->gen >= 8 && (value.negate || value.abs) &&
 288        is_logic_op(inst->opcode)) {
 289       return false;
 290    }
 291
 292    if (inst->src[arg].abs) {
 293       value.negate = false;
 294       value.abs = true;
 295    }
 296    if (inst->src[arg].negate)
 297       value.negate = !value.negate;
 298
 299    bool has_source_modifiers = value.negate || value.abs;
 300
 301    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 302     * instructions.
 303     */
 304    if ((has_source_modifiers || value.file == UNIFORM ||
 305         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
 306       return false;
 307
 308    if (has_source_modifiers && value.type != inst->src[arg].type)
 309       return false;
 310
 311    if (has_source_modifiers &&
 312        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
 313       return false;
 314
 315    if (inst->is_3src() && value.file == UNIFORM)
 316       return false;
 317
 318    if (inst->is_send_from_grf())
 319       return false;
 320
 321    /* we can't generally copy-propagate UD negations becuse we
 322     * end up accessing the resulting values as signed integers
 323     * instead. See also resolve_ud_negate().
 324     */
 325    if (value.negate &&
 326        value.type == BRW_REGISTER_TYPE_UD)
 327       return false;
 328
 329    /* Don't report progress if this is a noop. */
 330    if (value.equals(inst->src[arg]))
 331       return false;
 332
 333    /* Limit saturate propagation only to SEL with src1 bounded within 1.0 and 1.0
 334     * otherwise, skip copy propagate altogether
 335     */
 336    if (entry->saturatemask & (1 << arg)) {
 337       switch(inst->opcode) {
 338       case BRW_OPCODE_SEL:
 339          if (inst->src[1].file != IMM ||
 340              inst->src[1].fixed_hw_reg.dw1.f < 0.0 ||
 341              inst->src[1].fixed_hw_reg.dw1.f > 1.0) {
 342             return false;
 343          }
 344          if (!inst->saturate)
 345             inst->saturate = true;
 346          break;
 347       default:
 348          return false;
 349       }
 350    }
 351
 352    value.type = inst->src[arg].type;
 353    inst->src[arg] = value;
 354    return true;
 355 }
 356
 357 bool
 358 vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 359 {
 360    bool progress = false;
 361    struct copy_entry entries[alloc.total_size];
 362
 363    memset(&entries, 0, sizeof(entries));
 364
 365    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 366       /* This pass only works on basic blocks.  If there's flow
 367        * control, throw out all our information and start from
 368        * scratch.
 369        *
 370        * This should really be fixed by using a structure like in
 371        * src/glsl/opt_copy_propagation.cpp to track available copies.
 372        */
 373       if (!is_dominated_by_previous_instruction(inst)) {
 374          memset(&entries, 0, sizeof(entries));
 375          continue;
 376       }
 377
 378       /* For each source arg, see if each component comes from a copy
 379        * from the same type file (IMM, GRF, UNIFORM), and try
 380        * optimizing out access to the copy result
 381        */
 382       for (int i = 2; i >= 0; i--) {
 383          /* Copied values end up in GRFs, and we don't track reladdr
 384           * accesses.
 385           */
 386          if (inst->src[i].file != GRF ||
 387              inst->src[i].reladdr)
 388             continue;
 389
 390          int reg = (alloc.offsets[inst->src[i].reg] +
 391                     inst->src[i].reg_offset);
 392
 393          /* Find the regs that each swizzle component came from.
 394           */
 395          struct copy_entry entry;
 396          memset(&entry, 0, sizeof(copy_entry));
 397          int c;
 398          for (c = 0; c < 4; c++) {
 399             int channel = BRW_GET_SWZ(inst->src[i].swizzle, c);
 400             entry.value[c] = entries[reg].value[channel];
 401
 402             /* If there's no available copy for this channel, bail.
 403              * We could be more aggressive here -- some channels might
 404              * not get used based on the destination writemask.
 405              */
 406             if (!entry.value[c])
 407                break;
 408
 409             entry.saturatemask |=
 410                (entries[reg].saturatemask & (1 << channel) ? 1 : 0) << c;
 411
 412             /* We'll only be able to copy propagate if the sources are
 413              * all from the same file -- there's no ability to swizzle
 414              * 0 or 1 constants in with source registers like in i915.
 415              */
 416             if (c > 0 && entry.value[c - 1]->file != entry.value[c]->file)
 417                break;
 418          }
 419
 420          if (c != 4)
 421             continue;
 422
 423          if (do_constant_prop && try_constant_propagate(brw, inst, i, &entry))
 424             progress = true;
 425
 426          if (try_copy_propagate(brw, inst, i, &entry))
 427             progress = true;
 428       }
 429
 430       /* Track available source registers. */
 431       if (inst->dst.file == GRF) {
 432          const int reg =
 433             alloc.offsets[inst->dst.reg] + inst->dst.reg_offset;
 434
 435          /* Update our destination's current channel values.  For a direct copy,
 436           * the value is the newly propagated source.  Otherwise, we don't know
 437           * the new value, so clear it.
 438           */
 439          bool direct_copy = is_direct_copy(inst);
 440          entries[reg].saturatemask = 0x0;
 441          for (int i = 0; i < 4; i++) {
 442             if (inst->dst.writemask & (1 << i)) {
 443                entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
 444                entries[reg].saturatemask |= (((inst->saturate && direct_copy) ? 1 : 0) << i);
 445             }
 446          }
 447
 448          /* Clear the records for any registers whose current value came from
 449           * our destination's updated channels, as the two are no longer equal.
 450           */
 451          if (inst->dst.reladdr)
 452             memset(&entries, 0, sizeof(entries));
 453          else {
 454             for (unsigned i = 0; i < alloc.total_size; i++) {
 455                for (int j = 0; j < 4; j++) {
 456                   if (is_channel_updated(inst, entries[i].value, j)){
 457                      entries[i].value[j] = NULL;
 458                      entries[i].saturatemask &= ~(1 << j);
 459                   }
 460                }
 461             }
 462          }
 463       }
 464    }
 465
 466    if (progress)
 467       invalidate_live_intervals();
 468
 469    return progress;
 470 }
 471
 472 } /* namespace brw */