src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 #include "brw_cfg.h"
  34 extern "C" {
  35 #include "main/macros.h"
  36 }
  37
  38 namespace brw {
  39
  40 struct copy_entry {
  41    src_reg *value[4];
  42    int saturatemask;
  43 };
  44
  45 static bool
  46 is_direct_copy(vec4_instruction *inst)
  47 {
  48    return (inst->opcode == BRW_OPCODE_MOV &&
  49            !inst->predicate &&
  50            inst->dst.file == GRF &&
  51            !inst->dst.reladdr &&
  52            !inst->src[0].reladdr &&
  53            inst->dst.type == inst->src[0].type);
  54 }
  55
  56 static bool
  57 is_dominated_by_previous_instruction(vec4_instruction *inst)
  58 {
  59    return (inst->opcode != BRW_OPCODE_DO &&
  60            inst->opcode != BRW_OPCODE_WHILE &&
  61            inst->opcode != BRW_OPCODE_ELSE &&
  62            inst->opcode != BRW_OPCODE_ENDIF);
  63 }
  64
  65 static bool
  66 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  67 {
  68    const src_reg *src = values[ch];
  69
  70    /* consider GRF only */
  71    assert(inst->dst.file == GRF);
  72    if (!src || src->file != GRF)
  73       return false;
  74
  75    return (src->reg == inst->dst.reg &&
  76            src->reg_offset == inst->dst.reg_offset &&
  77            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  78 }
  79
  80 static bool
  81 try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
  82                        int arg, struct copy_entry *entry)
  83 {
  84    /* For constant propagation, we only handle the same constant
  85     * across all 4 channels.  Some day, we should handle the 8-bit
  86     * float vector format, which would let us constant propagate
  87     * vectors better.
  88     */
  89    src_reg value = *entry->value[0];
  90    for (int i = 1; i < 4; i++) {
  91       if (!value.equals(*entry->value[i]))
  92          return false;
  93    }
  94
  95    if (value.file != IMM)
  96       return false;
  97
  98    if (inst->src[arg].abs) {
  99       if (value.type == BRW_REGISTER_TYPE_F) {
 100          value.fixed_hw_reg.dw1.f = fabs(value.fixed_hw_reg.dw1.f);
 101       } else if (value.type == BRW_REGISTER_TYPE_D) {
 102          if (value.fixed_hw_reg.dw1.d < 0)
 103             value.fixed_hw_reg.dw1.d = -value.fixed_hw_reg.dw1.d;
 104       }
 105    }
 106
 107    if (inst->src[arg].negate) {
 108       if (value.type == BRW_REGISTER_TYPE_F)
 109          value.fixed_hw_reg.dw1.f = -value.fixed_hw_reg.dw1.f;
 110       else
 111          value.fixed_hw_reg.dw1.ud = -value.fixed_hw_reg.dw1.ud;
 112    }
 113
 114    switch (inst->opcode) {
 115    case BRW_OPCODE_MOV:
 116       inst->src[arg] = value;
 117       return true;
 118
 119    case SHADER_OPCODE_POW:
 120    case SHADER_OPCODE_INT_QUOTIENT:
 121    case SHADER_OPCODE_INT_REMAINDER:
 122       if (brw->gen < 8)
 123          break;
 124       /* fallthrough */
 125    case BRW_OPCODE_DP2:
 126    case BRW_OPCODE_DP3:
 127    case BRW_OPCODE_DP4:
 128    case BRW_OPCODE_DPH:
 129    case BRW_OPCODE_BFI1:
 130    case BRW_OPCODE_ASR:
 131    case BRW_OPCODE_SHL:
 132    case BRW_OPCODE_SHR:
 133    case BRW_OPCODE_SUBB:
 134       if (arg == 1) {
 135          inst->src[arg] = value;
 136          return true;
 137       }
 138       break;
 139
 140    case BRW_OPCODE_MACH:
 141    case BRW_OPCODE_MUL:
 142    case BRW_OPCODE_ADD:
 143    case BRW_OPCODE_OR:
 144    case BRW_OPCODE_AND:
 145    case BRW_OPCODE_XOR:
 146    case BRW_OPCODE_ADDC:
 147       if (arg == 1) {
 148          inst->src[arg] = value;
 149          return true;
 150       } else if (arg == 0 && inst->src[1].file != IMM) {
 151          /* Fit this constant in by commuting the operands.  Exception: we
 152           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 153           */
 154          if ((inst->opcode == BRW_OPCODE_MUL ||
 155               inst->opcode == BRW_OPCODE_MACH) &&
 156              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 157               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 158             break;
 159          inst->src[0] = inst->src[1];
 160          inst->src[1] = value;
 161          return true;
 162       }
 163       break;
 164
 165    case BRW_OPCODE_CMP:
 166       if (arg == 1) {
 167          inst->src[arg] = value;
 168          return true;
 169       } else if (arg == 0 && inst->src[1].file != IMM) {
 170          enum brw_conditional_mod new_cmod;
 171
 172          new_cmod = brw_swap_cmod(inst->conditional_mod);
 173          if (new_cmod != BRW_CONDITIONAL_NONE) {
 174             /* Fit this constant in by swapping the operands and
 175              * flipping the test.
 176              */
 177             inst->src[0] = inst->src[1];
 178             inst->src[1] = value;
 179             inst->conditional_mod = new_cmod;
 180             return true;
 181          }
 182       }
 183       break;
 184
 185    case BRW_OPCODE_SEL:
 186       if (arg == 1) {
 187          inst->src[arg] = value;
 188          return true;
 189       } else if (arg == 0 && inst->src[1].file != IMM) {
 190          inst->src[0] = inst->src[1];
 191          inst->src[1] = value;
 192
 193          /* If this was predicated, flipping operands means
 194           * we also need to flip the predicate.
 195           */
 196          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 197             inst->predicate_inverse = !inst->predicate_inverse;
 198          }
 199          return true;
 200       }
 201       break;
 202
 203    default:
 204       break;
 205    }
 206
 207    return false;
 208 }
 209
 210 static bool
 211 is_logic_op(enum opcode opcode)
 212 {
 213    return (opcode == BRW_OPCODE_AND ||
 214            opcode == BRW_OPCODE_OR  ||
 215            opcode == BRW_OPCODE_XOR ||
 216            opcode == BRW_OPCODE_NOT);
 217 }
 218
 219 static bool
 220 try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
 221                    int arg, struct copy_entry *entry, int reg)
 222 {
 223    /* For constant propagation, we only handle the same constant
 224     * across all 4 channels.  Some day, we should handle the 8-bit
 225     * float vector format, which would let us constant propagate
 226     * vectors better.
 227     */
 228    src_reg value = *entry->value[0];
 229    for (int i = 1; i < 4; i++) {
 230       /* This is equals() except we don't care about the swizzle. */
 231       if (value.file != entry->value[i]->file ||
 232           value.reg != entry->value[i]->reg ||
 233           value.reg_offset != entry->value[i]->reg_offset ||
 234           value.type != entry->value[i]->type ||
 235           value.negate != entry->value[i]->negate ||
 236           value.abs != entry->value[i]->abs) {
 237          return false;
 238       }
 239    }
 240
 241    /* Compute the swizzle of the original register by swizzling the
 242     * component loaded from each value according to the swizzle of
 243     * operand we're going to change.
 244     */
 245    int s[4];
 246    for (int i = 0; i < 4; i++) {
 247       s[i] = BRW_GET_SWZ(entry->value[i]->swizzle,
 248                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 249    }
 250    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 251
 252    if (value.file != UNIFORM &&
 253        value.file != GRF &&
 254        value.file != ATTR)
 255       return false;
 256
 257    if (brw->gen >= 8 && (value.negate || value.abs) &&
 258        is_logic_op(inst->opcode)) {
 259       return false;
 260    }
 261
 262    if (inst->src[arg].abs) {
 263       value.negate = false;
 264       value.abs = true;
 265    }
 266    if (inst->src[arg].negate)
 267       value.negate = !value.negate;
 268
 269    bool has_source_modifiers = value.negate || value.abs;
 270
 271    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 272     * instructions.
 273     */
 274    if ((has_source_modifiers || value.file == UNIFORM ||
 275         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
 276       return false;
 277
 278    if (has_source_modifiers && value.type != inst->src[arg].type)
 279       return false;
 280
 281    if (has_source_modifiers &&
 282        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
 283       return false;
 284
 285    bool is_3src_inst = (inst->opcode == BRW_OPCODE_LRP ||
 286                         inst->opcode == BRW_OPCODE_MAD ||
 287                         inst->opcode == BRW_OPCODE_BFE ||
 288                         inst->opcode == BRW_OPCODE_BFI2);
 289    if (is_3src_inst && value.file == UNIFORM)
 290       return false;
 291
 292    if (inst->is_send_from_grf())
 293       return false;
 294
 295    /* We can't copy-propagate a UD negation into a condmod
 296     * instruction, because the condmod ends up looking at the 33-bit
 297     * signed accumulator value instead of the 32-bit value we wanted
 298     */
 299    if (inst->conditional_mod &&
 300        value.negate &&
 301        value.type == BRW_REGISTER_TYPE_UD)
 302       return false;
 303
 304    /* Don't report progress if this is a noop. */
 305    if (value.equals(inst->src[arg]))
 306       return false;
 307
 308    /* Limit saturate propagation only to SEL with src1 bounded within 1.0 and 1.0
 309     * otherwise, skip copy propagate altogether
 310     */
 311    if (entry->saturatemask & (1 << arg)) {
 312       switch(inst->opcode) {
 313       case BRW_OPCODE_SEL:
 314          if (inst->src[1].file != IMM ||
 315              inst->src[1].fixed_hw_reg.dw1.f < 0.0 ||
 316              inst->src[1].fixed_hw_reg.dw1.f > 1.0) {
 317             return false;
 318          }
 319          if (!inst->saturate)
 320             inst->saturate = true;
 321          break;
 322       default:
 323          return false;
 324       }
 325    }
 326
 327    value.type = inst->src[arg].type;
 328    inst->src[arg] = value;
 329    return true;
 330 }
 331
 332 bool
 333 vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 334 {
 335    bool progress = false;
 336    struct copy_entry entries[virtual_grf_reg_count];
 337
 338    memset(&entries, 0, sizeof(entries));
 339
 340    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 341       /* This pass only works on basic blocks.  If there's flow
 342        * control, throw out all our information and start from
 343        * scratch.
 344        *
 345        * This should really be fixed by using a structure like in
 346        * src/glsl/opt_copy_propagation.cpp to track available copies.
 347        */
 348       if (!is_dominated_by_previous_instruction(inst)) {
 349          memset(&entries, 0, sizeof(entries));
 350          continue;
 351       }
 352
 353       /* For each source arg, see if each component comes from a copy
 354        * from the same type file (IMM, GRF, UNIFORM), and try
 355        * optimizing out access to the copy result
 356        */
 357       for (int i = 2; i >= 0; i--) {
 358          /* Copied values end up in GRFs, and we don't track reladdr
 359           * accesses.
 360           */
 361          if (inst->src[i].file != GRF ||
 362              inst->src[i].reladdr)
 363             continue;
 364
 365          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 366                     inst->src[i].reg_offset);
 367
 368          /* Find the regs that each swizzle component came from.
 369           */
 370          struct copy_entry entry;
 371          memset(&entry, 0, sizeof(copy_entry));
 372          int c;
 373          for (c = 0; c < 4; c++) {
 374             int channel = BRW_GET_SWZ(inst->src[i].swizzle, c);
 375             entry.value[c] = entries[reg].value[channel];
 376
 377             /* If there's no available copy for this channel, bail.
 378              * We could be more aggressive here -- some channels might
 379              * not get used based on the destination writemask.
 380              */
 381             if (!entry.value[c])
 382                break;
 383
 384             entry.saturatemask |=
 385                (entries[reg].saturatemask & (1 << channel) ? 1 : 0) << c;
 386
 387             /* We'll only be able to copy propagate if the sources are
 388              * all from the same file -- there's no ability to swizzle
 389              * 0 or 1 constants in with source registers like in i915.
 390              */
 391             if (c > 0 && entry.value[c - 1]->file != entry.value[c]->file)
 392                break;
 393          }
 394
 395          if (c != 4)
 396             continue;
 397
 398          if (do_constant_prop && try_constant_propagate(brw, inst, i, &entry))
 399             progress = true;
 400
 401          if (try_copy_propagate(brw, inst, i, &entry, reg))
 402             progress = true;
 403       }
 404
 405       /* Track available source registers. */
 406       if (inst->dst.file == GRF) {
 407          const int reg =
 408             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 409
 410          /* Update our destination's current channel values.  For a direct copy,
 411           * the value is the newly propagated source.  Otherwise, we don't know
 412           * the new value, so clear it.
 413           */
 414          bool direct_copy = is_direct_copy(inst);
 415          entries[reg].saturatemask = 0x0;
 416          for (int i = 0; i < 4; i++) {
 417             if (inst->dst.writemask & (1 << i)) {
 418                entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
 419                entries[reg].saturatemask |= (((inst->saturate && direct_copy) ? 1 : 0) << i);
 420             }
 421          }
 422
 423          /* Clear the records for any registers whose current value came from
 424           * our destination's updated channels, as the two are no longer equal.
 425           */
 426          if (inst->dst.reladdr)
 427             memset(&entries, 0, sizeof(entries));
 428          else {
 429             for (int i = 0; i < virtual_grf_reg_count; i++) {
 430                for (int j = 0; j < 4; j++) {
 431                   if (is_channel_updated(inst, entries[i].value, j)){
 432                      entries[i].value[j] = NULL;
 433                      entries[i].saturatemask &= ~(1 << j);
 434                   }
 435                }
 436             }
 437          }
 438       }
 439    }
 440
 441    if (progress)
 442       invalidate_live_intervals();
 443
 444    return progress;
 445 }
 446
 447 } /* namespace brw */