src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file brw_vec4_copy_propagation.cpp
  26  *
  27  * Implements tracking of values copied between registers, and
  28  * optimizations based on that: copy propagation and constant
  29  * propagation.
  30  */
  31
  32 #include "brw_vec4.h"
  33 #include "brw_cfg.h"
  34 extern "C" {
  35 #include "main/macros.h"
  36 }
  37
  38 namespace brw {
  39
  40 struct copy_entry {
  41    src_reg *value[4];
  42    int saturatemask;
  43 };
  44
  45 static bool
  46 is_direct_copy(vec4_instruction *inst)
  47 {
  48    return (inst->opcode == BRW_OPCODE_MOV &&
  49            !inst->predicate &&
  50            inst->dst.file == GRF &&
  51            !inst->dst.reladdr &&
  52            !inst->src[0].reladdr &&
  53            (inst->dst.type == inst->src[0].type ||
  54             (inst->dst.type == BRW_REGISTER_TYPE_F &&
  55              inst->src[0].type == BRW_REGISTER_TYPE_VF)));
  56 }
  57
  58 static bool
  59 is_dominated_by_previous_instruction(vec4_instruction *inst)
  60 {
  61    return (inst->opcode != BRW_OPCODE_DO &&
  62            inst->opcode != BRW_OPCODE_WHILE &&
  63            inst->opcode != BRW_OPCODE_ELSE &&
  64            inst->opcode != BRW_OPCODE_ENDIF);
  65 }
  66
  67 static bool
  68 is_channel_updated(vec4_instruction *inst, src_reg *values[4], int ch)
  69 {
  70    const src_reg *src = values[ch];
  71
  72    /* consider GRF only */
  73    assert(inst->dst.file == GRF);
  74    if (!src || src->file != GRF)
  75       return false;
  76
  77    return (src->reg == inst->dst.reg &&
  78            src->reg_offset == inst->dst.reg_offset &&
  79            inst->dst.writemask & (1 << BRW_GET_SWZ(src->swizzle, ch)));
  80 }
  81
  82 static unsigned
  83 swizzle_vf_imm(unsigned vf4, unsigned swizzle)
  84 {
  85    union {
  86       unsigned vf4;
  87       uint8_t vf[4];
  88    } v = { vf4 }, ret;
  89
  90    ret.vf[0] = v.vf[BRW_GET_SWZ(swizzle, 0)];
  91    ret.vf[1] = v.vf[BRW_GET_SWZ(swizzle, 1)];
  92    ret.vf[2] = v.vf[BRW_GET_SWZ(swizzle, 2)];
  93    ret.vf[3] = v.vf[BRW_GET_SWZ(swizzle, 3)];
  94
  95    return ret.vf4;
  96 }
  97
  98 static bool
  99 try_constant_propagate(struct brw_context *brw, vec4_instruction *inst,
 100                        int arg, struct copy_entry *entry)
 101 {
 102    /* For constant propagation, we only handle the same constant
 103     * across all 4 channels.  Some day, we should handle the 8-bit
 104     * float vector format, which would let us constant propagate
 105     * vectors better.
 106     */
 107    src_reg value = *entry->value[0];
 108    for (int i = 1; i < 4; i++) {
 109       if (!value.equals(*entry->value[i]))
 110          return false;
 111    }
 112
 113    if (value.file != IMM)
 114       return false;
 115
 116    if (inst->src[arg].abs) {
 117       if (!brw_abs_immediate(value.type, &value.fixed_hw_reg)) {
 118          return false;
 119       }
 120    }
 121
 122    if (inst->src[arg].negate) {
 123       if (!brw_negate_immediate(value.type, &value.fixed_hw_reg)) {
 124          return false;
 125       }
 126    }
 127
 128    if (value.type == BRW_REGISTER_TYPE_VF)
 129       value.fixed_hw_reg.dw1.ud = swizzle_vf_imm(value.fixed_hw_reg.dw1.ud,
 130                                                  inst->src[arg].swizzle);
 131
 132    switch (inst->opcode) {
 133    case BRW_OPCODE_MOV:
 134       inst->src[arg] = value;
 135       return true;
 136
 137    case SHADER_OPCODE_POW:
 138    case SHADER_OPCODE_INT_QUOTIENT:
 139    case SHADER_OPCODE_INT_REMAINDER:
 140       if (brw->gen < 8)
 141          break;
 142       /* fallthrough */
 143    case BRW_OPCODE_DP2:
 144    case BRW_OPCODE_DP3:
 145    case BRW_OPCODE_DP4:
 146    case BRW_OPCODE_DPH:
 147    case BRW_OPCODE_BFI1:
 148    case BRW_OPCODE_ASR:
 149    case BRW_OPCODE_SHL:
 150    case BRW_OPCODE_SHR:
 151    case BRW_OPCODE_SUBB:
 152       if (arg == 1) {
 153          inst->src[arg] = value;
 154          return true;
 155       }
 156       break;
 157
 158    case BRW_OPCODE_MACH:
 159    case BRW_OPCODE_MUL:
 160    case BRW_OPCODE_ADD:
 161    case BRW_OPCODE_OR:
 162    case BRW_OPCODE_AND:
 163    case BRW_OPCODE_XOR:
 164    case BRW_OPCODE_ADDC:
 165       if (arg == 1) {
 166          inst->src[arg] = value;
 167          return true;
 168       } else if (arg == 0 && inst->src[1].file != IMM) {
 169          /* Fit this constant in by commuting the operands.  Exception: we
 170           * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
 171           */
 172          if ((inst->opcode == BRW_OPCODE_MUL ||
 173               inst->opcode == BRW_OPCODE_MACH) &&
 174              (inst->src[1].type == BRW_REGISTER_TYPE_D ||
 175               inst->src[1].type == BRW_REGISTER_TYPE_UD))
 176             break;
 177          inst->src[0] = inst->src[1];
 178          inst->src[1] = value;
 179          return true;
 180       }
 181       break;
 182
 183    case BRW_OPCODE_CMP:
 184       if (arg == 1) {
 185          inst->src[arg] = value;
 186          return true;
 187       } else if (arg == 0 && inst->src[1].file != IMM) {
 188          enum brw_conditional_mod new_cmod;
 189
 190          new_cmod = brw_swap_cmod(inst->conditional_mod);
 191          if (new_cmod != BRW_CONDITIONAL_NONE) {
 192             /* Fit this constant in by swapping the operands and
 193              * flipping the test.
 194              */
 195             inst->src[0] = inst->src[1];
 196             inst->src[1] = value;
 197             inst->conditional_mod = new_cmod;
 198             return true;
 199          }
 200       }
 201       break;
 202
 203    case BRW_OPCODE_SEL:
 204       if (arg == 1) {
 205          inst->src[arg] = value;
 206          return true;
 207       } else if (arg == 0 && inst->src[1].file != IMM) {
 208          inst->src[0] = inst->src[1];
 209          inst->src[1] = value;
 210
 211          /* If this was predicated, flipping operands means
 212           * we also need to flip the predicate.
 213           */
 214          if (inst->conditional_mod == BRW_CONDITIONAL_NONE) {
 215             inst->predicate_inverse = !inst->predicate_inverse;
 216          }
 217          return true;
 218       }
 219       break;
 220
 221    default:
 222       break;
 223    }
 224
 225    return false;
 226 }
 227
 228 static bool
 229 is_logic_op(enum opcode opcode)
 230 {
 231    return (opcode == BRW_OPCODE_AND ||
 232            opcode == BRW_OPCODE_OR  ||
 233            opcode == BRW_OPCODE_XOR ||
 234            opcode == BRW_OPCODE_NOT);
 235 }
 236
 237 static bool
 238 try_copy_propagate(struct brw_context *brw, vec4_instruction *inst,
 239                    int arg, struct copy_entry *entry, int reg)
 240 {
 241    /* For constant propagation, we only handle the same constant
 242     * across all 4 channels.  Some day, we should handle the 8-bit
 243     * float vector format, which would let us constant propagate
 244     * vectors better.
 245     */
 246    src_reg value = *entry->value[0];
 247    for (int i = 1; i < 4; i++) {
 248       /* This is equals() except we don't care about the swizzle. */
 249       if (value.file != entry->value[i]->file ||
 250           value.reg != entry->value[i]->reg ||
 251           value.reg_offset != entry->value[i]->reg_offset ||
 252           value.type != entry->value[i]->type ||
 253           value.negate != entry->value[i]->negate ||
 254           value.abs != entry->value[i]->abs) {
 255          return false;
 256       }
 257    }
 258
 259    /* Compute the swizzle of the original register by swizzling the
 260     * component loaded from each value according to the swizzle of
 261     * operand we're going to change.
 262     */
 263    int s[4];
 264    for (int i = 0; i < 4; i++) {
 265       s[i] = BRW_GET_SWZ(entry->value[i]->swizzle,
 266                          BRW_GET_SWZ(inst->src[arg].swizzle, i));
 267    }
 268    value.swizzle = BRW_SWIZZLE4(s[0], s[1], s[2], s[3]);
 269
 270    if (value.file != UNIFORM &&
 271        value.file != GRF &&
 272        value.file != ATTR)
 273       return false;
 274
 275    if (brw->gen >= 8 && (value.negate || value.abs) &&
 276        is_logic_op(inst->opcode)) {
 277       return false;
 278    }
 279
 280    if (inst->src[arg].abs) {
 281       value.negate = false;
 282       value.abs = true;
 283    }
 284    if (inst->src[arg].negate)
 285       value.negate = !value.negate;
 286
 287    bool has_source_modifiers = value.negate || value.abs;
 288
 289    /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
 290     * instructions.
 291     */
 292    if ((has_source_modifiers || value.file == UNIFORM ||
 293         value.swizzle != BRW_SWIZZLE_XYZW) && !inst->can_do_source_mods(brw))
 294       return false;
 295
 296    if (has_source_modifiers && value.type != inst->src[arg].type)
 297       return false;
 298
 299    if (has_source_modifiers &&
 300        inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE)
 301       return false;
 302
 303    if (inst->is_3src() && value.file == UNIFORM)
 304       return false;
 305
 306    if (inst->is_send_from_grf())
 307       return false;
 308
 309    /* we can't generally copy-propagate UD negations becuse we
 310     * end up accessing the resulting values as signed integers
 311     * instead. See also resolve_ud_negate().
 312     */
 313    if (value.negate &&
 314        value.type == BRW_REGISTER_TYPE_UD)
 315       return false;
 316
 317    /* Don't report progress if this is a noop. */
 318    if (value.equals(inst->src[arg]))
 319       return false;
 320
 321    /* Limit saturate propagation only to SEL with src1 bounded within 1.0 and 1.0
 322     * otherwise, skip copy propagate altogether
 323     */
 324    if (entry->saturatemask & (1 << arg)) {
 325       switch(inst->opcode) {
 326       case BRW_OPCODE_SEL:
 327          if (inst->src[1].file != IMM ||
 328              inst->src[1].fixed_hw_reg.dw1.f < 0.0 ||
 329              inst->src[1].fixed_hw_reg.dw1.f > 1.0) {
 330             return false;
 331          }
 332          if (!inst->saturate)
 333             inst->saturate = true;
 334          break;
 335       default:
 336          return false;
 337       }
 338    }
 339
 340    value.type = inst->src[arg].type;
 341    inst->src[arg] = value;
 342    return true;
 343 }
 344
 345 bool
 346 vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 347 {
 348    bool progress = false;
 349    struct copy_entry entries[virtual_grf_reg_count];
 350
 351    memset(&entries, 0, sizeof(entries));
 352
 353    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
 354       /* This pass only works on basic blocks.  If there's flow
 355        * control, throw out all our information and start from
 356        * scratch.
 357        *
 358        * This should really be fixed by using a structure like in
 359        * src/glsl/opt_copy_propagation.cpp to track available copies.
 360        */
 361       if (!is_dominated_by_previous_instruction(inst)) {
 362          memset(&entries, 0, sizeof(entries));
 363          continue;
 364       }
 365
 366       /* For each source arg, see if each component comes from a copy
 367        * from the same type file (IMM, GRF, UNIFORM), and try
 368        * optimizing out access to the copy result
 369        */
 370       for (int i = 2; i >= 0; i--) {
 371          /* Copied values end up in GRFs, and we don't track reladdr
 372           * accesses.
 373           */
 374          if (inst->src[i].file != GRF ||
 375              inst->src[i].reladdr)
 376             continue;
 377
 378          int reg = (virtual_grf_reg_map[inst->src[i].reg] +
 379                     inst->src[i].reg_offset);
 380
 381          /* Find the regs that each swizzle component came from.
 382           */
 383          struct copy_entry entry;
 384          memset(&entry, 0, sizeof(copy_entry));
 385          int c;
 386          for (c = 0; c < 4; c++) {
 387             int channel = BRW_GET_SWZ(inst->src[i].swizzle, c);
 388             entry.value[c] = entries[reg].value[channel];
 389
 390             /* If there's no available copy for this channel, bail.
 391              * We could be more aggressive here -- some channels might
 392              * not get used based on the destination writemask.
 393              */
 394             if (!entry.value[c])
 395                break;
 396
 397             entry.saturatemask |=
 398                (entries[reg].saturatemask & (1 << channel) ? 1 : 0) << c;
 399
 400             /* We'll only be able to copy propagate if the sources are
 401              * all from the same file -- there's no ability to swizzle
 402              * 0 or 1 constants in with source registers like in i915.
 403              */
 404             if (c > 0 && entry.value[c - 1]->file != entry.value[c]->file)
 405                break;
 406          }
 407
 408          if (c != 4)
 409             continue;
 410
 411          if (do_constant_prop && try_constant_propagate(brw, inst, i, &entry))
 412             progress = true;
 413
 414          if (try_copy_propagate(brw, inst, i, &entry, reg))
 415             progress = true;
 416       }
 417
 418       /* Track available source registers. */
 419       if (inst->dst.file == GRF) {
 420          const int reg =
 421             virtual_grf_reg_map[inst->dst.reg] + inst->dst.reg_offset;
 422
 423          /* Update our destination's current channel values.  For a direct copy,
 424           * the value is the newly propagated source.  Otherwise, we don't know
 425           * the new value, so clear it.
 426           */
 427          bool direct_copy = is_direct_copy(inst);
 428          entries[reg].saturatemask = 0x0;
 429          for (int i = 0; i < 4; i++) {
 430             if (inst->dst.writemask & (1 << i)) {
 431                entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL;
 432                entries[reg].saturatemask |= (((inst->saturate && direct_copy) ? 1 : 0) << i);
 433             }
 434          }
 435
 436          /* Clear the records for any registers whose current value came from
 437           * our destination's updated channels, as the two are no longer equal.
 438           */
 439          if (inst->dst.reladdr)
 440             memset(&entries, 0, sizeof(entries));
 441          else {
 442             for (int i = 0; i < virtual_grf_reg_count; i++) {
 443                for (int j = 0; j < 4; j++) {
 444                   if (is_channel_updated(inst, entries[i].value, j)){
 445                      entries[i].value[j] = NULL;
 446                      entries[i].saturatemask &= ~(1 << j);
 447                   }
 448                }
 449             }
 450          }
 451       }
 452    }
 453
 454    if (progress)
 455       invalidate_live_intervals();
 456
 457    return progress;
 458 }
 459
 460 } /* namespace brw */