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25 * @file brw_vec4_copy_propagation.cpp
27 * Implements tracking of values copied between registers, and
28 * optimizations based on that: copy propagation and constant
44 is_direct_copy(vec4_instruction
*inst
)
46 return (inst
->opcode
== BRW_OPCODE_MOV
&&
48 inst
->dst
.file
== VGRF
&&
50 !inst
->src
[0].reladdr
&&
51 (inst
->dst
.type
== inst
->src
[0].type
||
52 (inst
->dst
.type
== BRW_REGISTER_TYPE_F
&&
53 inst
->src
[0].type
== BRW_REGISTER_TYPE_VF
)));
57 is_dominated_by_previous_instruction(vec4_instruction
*inst
)
59 return (inst
->opcode
!= BRW_OPCODE_DO
&&
60 inst
->opcode
!= BRW_OPCODE_WHILE
&&
61 inst
->opcode
!= BRW_OPCODE_ELSE
&&
62 inst
->opcode
!= BRW_OPCODE_ENDIF
);
66 is_channel_updated(vec4_instruction
*inst
, src_reg
*values
[4], int ch
)
68 const src_reg
*src
= values
[ch
];
70 /* consider GRF only */
71 assert(inst
->dst
.file
== VGRF
);
72 if (!src
|| src
->file
!= VGRF
)
75 return (src
->in_range(inst
->dst
, inst
->regs_written
) &&
76 inst
->dst
.writemask
& (1 << BRW_GET_SWZ(src
->swizzle
, ch
)));
80 is_logic_op(enum opcode opcode
)
82 return (opcode
== BRW_OPCODE_AND
||
83 opcode
== BRW_OPCODE_OR
||
84 opcode
== BRW_OPCODE_XOR
||
85 opcode
== BRW_OPCODE_NOT
);
89 try_constant_propagate(const struct brw_device_info
*devinfo
,
90 vec4_instruction
*inst
,
91 int arg
, struct copy_entry
*entry
)
93 /* For constant propagation, we only handle the same constant
94 * across all 4 channels. Some day, we should handle the 8-bit
95 * float vector format, which would let us constant propagate
98 src_reg value
= *entry
->value
[0];
99 for (int i
= 1; i
< 4; i
++) {
100 if (!value
.equals(*entry
->value
[i
]))
104 if (value
.file
!= IMM
)
107 if (value
.type
== BRW_REGISTER_TYPE_VF
) {
108 /* The result of bit-casting the component values of a vector float
109 * cannot in general be represented as an immediate.
111 if (inst
->src
[arg
].type
!= BRW_REGISTER_TYPE_F
)
114 value
.type
= inst
->src
[arg
].type
;
117 if (inst
->src
[arg
].abs
) {
118 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
119 !brw_abs_immediate(value
.type
, &value
.as_brw_reg())) {
124 if (inst
->src
[arg
].negate
) {
125 if ((devinfo
->gen
>= 8 && is_logic_op(inst
->opcode
)) ||
126 !brw_negate_immediate(value
.type
, &value
.as_brw_reg())) {
131 value
= swizzle(value
, inst
->src
[arg
].swizzle
);
133 switch (inst
->opcode
) {
135 case SHADER_OPCODE_BROADCAST
:
136 inst
->src
[arg
] = value
;
139 case SHADER_OPCODE_POW
:
140 case SHADER_OPCODE_INT_QUOTIENT
:
141 case SHADER_OPCODE_INT_REMAINDER
:
142 if (devinfo
->gen
< 8)
149 case BRW_OPCODE_BFI1
:
153 case BRW_OPCODE_SUBB
:
155 inst
->src
[arg
] = value
;
160 case BRW_OPCODE_MACH
:
162 case SHADER_OPCODE_MULH
:
167 case BRW_OPCODE_ADDC
:
169 inst
->src
[arg
] = value
;
171 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
172 /* Fit this constant in by commuting the operands. Exception: we
173 * can't do this for 32-bit integer MUL/MACH because it's asymmetric.
175 if ((inst
->opcode
== BRW_OPCODE_MUL
||
176 inst
->opcode
== BRW_OPCODE_MACH
) &&
177 (inst
->src
[1].type
== BRW_REGISTER_TYPE_D
||
178 inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
))
180 inst
->src
[0] = inst
->src
[1];
181 inst
->src
[1] = value
;
185 case GS_OPCODE_SET_WRITE_OFFSET
:
186 /* This is just a multiply by a constant with special strides.
187 * The generator will handle immediates in both arguments (generating
188 * a single MOV of the product). So feel free to propagate in src0.
190 inst
->src
[arg
] = value
;
195 inst
->src
[arg
] = value
;
197 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
198 enum brw_conditional_mod new_cmod
;
200 new_cmod
= brw_swap_cmod(inst
->conditional_mod
);
201 if (new_cmod
!= BRW_CONDITIONAL_NONE
) {
202 /* Fit this constant in by swapping the operands and
205 inst
->src
[0] = inst
->src
[1];
206 inst
->src
[1] = value
;
207 inst
->conditional_mod
= new_cmod
;
215 inst
->src
[arg
] = value
;
217 } else if (arg
== 0 && inst
->src
[1].file
!= IMM
) {
218 inst
->src
[0] = inst
->src
[1];
219 inst
->src
[1] = value
;
221 /* If this was predicated, flipping operands means
222 * we also need to flip the predicate.
224 if (inst
->conditional_mod
== BRW_CONDITIONAL_NONE
) {
225 inst
->predicate_inverse
= !inst
->predicate_inverse
;
239 try_copy_propagate(const struct brw_device_info
*devinfo
,
240 vec4_instruction
*inst
, int arg
,
241 struct copy_entry
*entry
, int attributes_per_reg
)
243 /* Build up the value we are propagating as if it were the source of a
246 /* For constant propagation, we only handle the same constant
247 * across all 4 channels. Some day, we should handle the 8-bit
248 * float vector format, which would let us constant propagate
251 src_reg value
= *entry
->value
[0];
252 for (int i
= 1; i
< 4; i
++) {
253 /* This is equals() except we don't care about the swizzle. */
254 if (value
.file
!= entry
->value
[i
]->file
||
255 value
.nr
!= entry
->value
[i
]->nr
||
256 value
.reg_offset
!= entry
->value
[i
]->reg_offset
||
257 value
.type
!= entry
->value
[i
]->type
||
258 value
.negate
!= entry
->value
[i
]->negate
||
259 value
.abs
!= entry
->value
[i
]->abs
) {
264 /* Compute the swizzle of the original register by swizzling the
265 * component loaded from each value according to the swizzle of
266 * operand we're going to change.
269 for (int i
= 0; i
< 4; i
++) {
270 s
[i
] = BRW_GET_SWZ(entry
->value
[i
]->swizzle
, i
);
272 value
.swizzle
= BRW_SWIZZLE4(s
[0], s
[1], s
[2], s
[3]);
274 /* Check that we can propagate that value */
275 if (value
.file
!= UNIFORM
&&
276 value
.file
!= VGRF
&&
280 if (devinfo
->gen
>= 8 && (value
.negate
|| value
.abs
) &&
281 is_logic_op(inst
->opcode
)) {
285 bool has_source_modifiers
= value
.negate
|| value
.abs
;
287 /* gen6 math and gen7+ SENDs from GRFs ignore source modifiers on
290 if ((has_source_modifiers
|| value
.file
== UNIFORM
||
291 value
.swizzle
!= BRW_SWIZZLE_XYZW
) && !inst
->can_do_source_mods(devinfo
))
294 if (has_source_modifiers
&&
295 value
.type
!= inst
->src
[arg
].type
&&
296 !inst
->can_change_types())
299 if (has_source_modifiers
&&
300 inst
->opcode
== SHADER_OPCODE_GEN4_SCRATCH_WRITE
)
303 unsigned composed_swizzle
= brw_compose_swizzle(inst
->src
[arg
].swizzle
,
305 if (inst
->is_3src() &&
306 (value
.file
== UNIFORM
||
307 (value
.file
== ATTR
&& attributes_per_reg
!= 1)) &&
308 !brw_is_single_value_swizzle(composed_swizzle
))
311 if (inst
->is_send_from_grf())
314 /* we can't generally copy-propagate UD negations becuse we
315 * end up accessing the resulting values as signed integers
316 * instead. See also resolve_ud_negate().
319 value
.type
== BRW_REGISTER_TYPE_UD
)
322 /* Don't report progress if this is a noop. */
323 if (value
.equals(inst
->src
[arg
]))
326 const unsigned dst_saturate_mask
= inst
->dst
.writemask
&
327 brw_apply_swizzle_to_mask(inst
->src
[arg
].swizzle
, entry
->saturatemask
);
329 if (dst_saturate_mask
) {
330 /* We either saturate all or nothing. */
331 if (dst_saturate_mask
!= inst
->dst
.writemask
)
334 /* Limit saturate propagation only to SEL with src1 bounded within 0.0
335 * and 1.0, otherwise skip copy propagate altogether.
337 switch(inst
->opcode
) {
340 inst
->src
[0].type
!= BRW_REGISTER_TYPE_F
||
341 inst
->src
[1].file
!= IMM
||
342 inst
->src
[1].type
!= BRW_REGISTER_TYPE_F
||
343 inst
->src
[1].f
< 0.0 ||
344 inst
->src
[1].f
> 1.0) {
348 inst
->saturate
= true;
355 /* Build the final value */
356 if (inst
->src
[arg
].abs
) {
357 value
.negate
= false;
360 if (inst
->src
[arg
].negate
)
361 value
.negate
= !value
.negate
;
363 value
.swizzle
= composed_swizzle
;
364 if (has_source_modifiers
&&
365 value
.type
!= inst
->src
[arg
].type
) {
366 assert(inst
->can_change_types());
367 for (int i
= 0; i
< 3; i
++) {
368 inst
->src
[i
].type
= value
.type
;
370 inst
->dst
.type
= value
.type
;
372 value
.type
= inst
->src
[arg
].type
;
375 inst
->src
[arg
] = value
;
380 vec4_visitor::opt_copy_propagation(bool do_constant_prop
)
382 /* If we are in dual instanced or single mode, then attributes are going
383 * to be interleaved, so one register contains two attribute slots.
385 const int attributes_per_reg
=
386 prog_data
->dispatch_mode
== DISPATCH_MODE_4X2_DUAL_OBJECT
? 1 : 2;
387 bool progress
= false;
388 struct copy_entry entries
[alloc
.total_size
];
390 memset(&entries
, 0, sizeof(entries
));
392 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
393 /* This pass only works on basic blocks. If there's flow
394 * control, throw out all our information and start from
397 * This should really be fixed by using a structure like in
398 * src/glsl/opt_copy_propagation.cpp to track available copies.
400 if (!is_dominated_by_previous_instruction(inst
)) {
401 memset(&entries
, 0, sizeof(entries
));
405 /* For each source arg, see if each component comes from a copy
406 * from the same type file (IMM, VGRF, UNIFORM), and try
407 * optimizing out access to the copy result
409 for (int i
= 2; i
>= 0; i
--) {
410 /* Copied values end up in GRFs, and we don't track reladdr
413 if (inst
->src
[i
].file
!= VGRF
||
414 inst
->src
[i
].reladdr
)
417 /* We only handle single-register copies. */
418 if (inst
->regs_read(i
) != 1)
421 int reg
= (alloc
.offsets
[inst
->src
[i
].nr
] +
422 inst
->src
[i
].reg_offset
);
424 /* Find the regs that each swizzle component came from.
426 struct copy_entry entry
;
427 memset(&entry
, 0, sizeof(copy_entry
));
429 for (c
= 0; c
< 4; c
++) {
430 int channel
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
);
431 entry
.value
[c
] = entries
[reg
].value
[channel
];
433 /* If there's no available copy for this channel, bail.
434 * We could be more aggressive here -- some channels might
435 * not get used based on the destination writemask.
440 entry
.saturatemask
|=
441 (entries
[reg
].saturatemask
& (1 << channel
) ? 1 : 0) << c
;
443 /* We'll only be able to copy propagate if the sources are
444 * all from the same file -- there's no ability to swizzle
445 * 0 or 1 constants in with source registers like in i915.
447 if (c
> 0 && entry
.value
[c
- 1]->file
!= entry
.value
[c
]->file
)
454 if (do_constant_prop
&& try_constant_propagate(devinfo
, inst
, i
, &entry
))
457 if (try_copy_propagate(devinfo
, inst
, i
, &entry
, attributes_per_reg
))
461 /* Track available source registers. */
462 if (inst
->dst
.file
== VGRF
) {
464 alloc
.offsets
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
466 /* Update our destination's current channel values. For a direct copy,
467 * the value is the newly propagated source. Otherwise, we don't know
468 * the new value, so clear it.
470 bool direct_copy
= is_direct_copy(inst
);
471 entries
[reg
].saturatemask
&= ~inst
->dst
.writemask
;
472 for (int i
= 0; i
< 4; i
++) {
473 if (inst
->dst
.writemask
& (1 << i
)) {
474 entries
[reg
].value
[i
] = direct_copy
? &inst
->src
[0] : NULL
;
475 entries
[reg
].saturatemask
|=
476 inst
->saturate
&& direct_copy
? 1 << i
: 0;
480 /* Clear the records for any registers whose current value came from
481 * our destination's updated channels, as the two are no longer equal.
483 if (inst
->dst
.reladdr
)
484 memset(&entries
, 0, sizeof(entries
));
486 for (unsigned i
= 0; i
< alloc
.total_size
; i
++) {
487 for (int j
= 0; j
< 4; j
++) {
488 if (is_channel_updated(inst
, entries
[i
].value
, j
)) {
489 entries
[i
].value
[j
] = NULL
;
490 entries
[i
].saturatemask
&= ~(1 << j
);
499 invalidate_live_intervals();
504 } /* namespace brw */