src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_cfg.h"
  26
  27 using namespace brw;
  28
  29 /** @file brw_vec4_cse.cpp
  30  *
  31  * Support for local common subexpression elimination.
  32  *
  33  * See Muchnick's Advanced Compiler Design and Implementation, section
  34  * 13.1 (p378).
  35  */
  36
  37 namespace {
  38 struct aeb_entry : public exec_node {
  39    /** The instruction that generates the expression value. */
  40    vec4_instruction *generator;
  41
  42    /** The temporary where the value is stored. */
  43    src_reg tmp;
  44 };
  45 }
  46
  47 static bool
  48 is_expression(const vec4_instruction *const inst)
  49 {
  50    switch (inst->opcode) {
  51    case BRW_OPCODE_MOV:
  52    case BRW_OPCODE_SEL:
  53    case BRW_OPCODE_NOT:
  54    case BRW_OPCODE_AND:
  55    case BRW_OPCODE_OR:
  56    case BRW_OPCODE_XOR:
  57    case BRW_OPCODE_SHR:
  58    case BRW_OPCODE_SHL:
  59    case BRW_OPCODE_ASR:
  60    case BRW_OPCODE_CMP:
  61    case BRW_OPCODE_CMPN:
  62    case BRW_OPCODE_ADD:
  63    case BRW_OPCODE_MUL:
  64    case BRW_OPCODE_FRC:
  65    case BRW_OPCODE_RNDU:
  66    case BRW_OPCODE_RNDD:
  67    case BRW_OPCODE_RNDE:
  68    case BRW_OPCODE_RNDZ:
  69    case BRW_OPCODE_LINE:
  70    case BRW_OPCODE_PLN:
  71    case BRW_OPCODE_MAD:
  72    case BRW_OPCODE_LRP:
  73    case VEC4_OPCODE_UNPACK_UNIFORM:
  74       return true;
  75    case SHADER_OPCODE_RCP:
  76    case SHADER_OPCODE_RSQ:
  77    case SHADER_OPCODE_SQRT:
  78    case SHADER_OPCODE_EXP2:
  79    case SHADER_OPCODE_LOG2:
  80    case SHADER_OPCODE_POW:
  81    case SHADER_OPCODE_INT_QUOTIENT:
  82    case SHADER_OPCODE_INT_REMAINDER:
  83    case SHADER_OPCODE_SIN:
  84    case SHADER_OPCODE_COS:
  85       return inst->mlen == 0;
  86    default:
  87       return false;
  88    }
  89 }
  90
  91 static bool
  92 operands_match(const vec4_instruction *a, const vec4_instruction *b)
  93 {
  94    const src_reg *xs = a->src;
  95    const src_reg *ys = b->src;
  96
  97    if (a->opcode == BRW_OPCODE_MAD) {
  98       return xs[0].equals(ys[0]) &&
  99              ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
 100               (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
 101    } else if (!a->is_commutative()) {
 102       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 103    } else {
 104       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 105              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 106    }
 107 }
 108
 109 static bool
 110 instructions_match(vec4_instruction *a, vec4_instruction *b)
 111 {
 112    return a->opcode == b->opcode &&
 113           a->saturate == b->saturate &&
 114           a->conditional_mod == b->conditional_mod &&
 115           a->dst.type == b->dst.type &&
 116           a->dst.writemask == b->dst.writemask &&
 117           a->regs_written == b->regs_written &&
 118           operands_match(a, b);
 119 }
 120
 121 bool
 122 vec4_visitor::opt_cse_local(bblock_t *block)
 123 {
 124    bool progress = false;
 125    exec_list aeb;
 126
 127    void *cse_ctx = ralloc_context(NULL);
 128
 129    int ip = block->start_ip;
 130    foreach_inst_in_block (vec4_instruction, inst, block) {
 131       /* Skip some cases. */
 132       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 133           (inst->dst.file != HW_REG || inst->dst.is_null()))
 134       {
 135          bool found = false;
 136
 137          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 138             /* Match current instruction's expression against those in AEB. */
 139             if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
 140                 instructions_match(inst, entry->generator)) {
 141                found = true;
 142                progress = true;
 143                break;
 144             }
 145          }
 146
 147          if (!found) {
 148             if (inst->opcode != BRW_OPCODE_MOV ||
 149                 (inst->opcode == BRW_OPCODE_MOV &&
 150                  inst->src[0].file == IMM &&
 151                  inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
 152                /* Our first sighting of this expression.  Create an entry. */
 153                aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 154                entry->tmp = src_reg(); /* file will be BAD_FILE */
 155                entry->generator = inst;
 156                aeb.push_tail(entry);
 157             }
 158          } else {
 159             /* This is at least our second sighting of this expression.
 160              * If we don't have a temporary already, make one.
 161              */
 162             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 163             if (no_existing_temp && !entry->generator->dst.is_null()) {
 164                entry->tmp = retype(src_reg(GRF, alloc.allocate(
 165                                               entry->generator->regs_written),
 166                                            NULL), inst->dst.type);
 167
 168                for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
 169                   vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
 170                                                offset(entry->tmp, i));
 171                   entry->generator->insert_after(block, copy);
 172                }
 173
 174                entry->generator->dst = dst_reg(entry->tmp);
 175             }
 176
 177             /* dest <- temp */
 178             if (!inst->dst.is_null()) {
 179                assert(inst->dst.type == entry->tmp.type);
 180
 181                for (unsigned i = 0; i < inst->regs_written; ++i) {
 182                   vec4_instruction *copy = MOV(offset(inst->dst, i),
 183                                                offset(entry->tmp, i));
 184                   copy->force_writemask_all = inst->force_writemask_all;
 185                   inst->insert_before(block, copy);
 186                }
 187             }
 188
 189             /* Set our iterator so that next time through the loop inst->next
 190              * will get the instruction in the basic block after the one we've
 191              * removed.
 192              */
 193             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 194
 195             inst->remove(block);
 196             inst = prev;
 197          }
 198       }
 199
 200       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 201          /* Kill all AEB entries that write a different value to or read from
 202           * the flag register if we just wrote it.
 203           */
 204          if (inst->writes_flag()) {
 205             if (entry->generator->reads_flag() ||
 206                 (entry->generator->writes_flag() &&
 207                  !instructions_match(inst, entry->generator))) {
 208                entry->remove();
 209                ralloc_free(entry);
 210                continue;
 211             }
 212          }
 213
 214          for (int i = 0; i < 3; i++) {
 215             src_reg *src = &entry->generator->src[i];
 216
 217             /* Kill all AEB entries that use the destination we just
 218              * overwrote.
 219              */
 220             if (inst->dst.file == entry->generator->src[i].file &&
 221                 inst->dst.reg == entry->generator->src[i].reg) {
 222                entry->remove();
 223                ralloc_free(entry);
 224                break;
 225             }
 226
 227             /* Kill any AEB entries using registers that don't get reused any
 228              * more -- a sure sign they'll fail operands_match().
 229              */
 230             if (src->file == GRF) {
 231                assert((unsigned)(src->reg * 4 + 3) < (alloc.count * 4));
 232
 233                int last_reg_use = MAX2(MAX2(virtual_grf_end[src->reg * 4 + 0],
 234                                             virtual_grf_end[src->reg * 4 + 1]),
 235                                        MAX2(virtual_grf_end[src->reg * 4 + 2],
 236                                             virtual_grf_end[src->reg * 4 + 3]));
 237                if (last_reg_use < ip) {
 238                   entry->remove();
 239                   ralloc_free(entry);
 240                   break;
 241                }
 242             }
 243          }
 244       }
 245
 246       ip++;
 247    }
 248
 249    ralloc_free(cse_ctx);
 250
 251    return progress;
 252 }
 253
 254 bool
 255 vec4_visitor::opt_cse()
 256 {
 257    bool progress = false;
 258
 259    calculate_live_intervals();
 260
 261    foreach_block (block, cfg) {
 262       progress = opt_cse_local(block) || progress;
 263    }
 264
 265    if (progress)
 266       invalidate_live_intervals();
 267
 268    return progress;
 269 }