src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_vec4_live_variables.h"
  26 #include "brw_cfg.h"
  27
  28 using namespace brw;
  29
  30 /** @file brw_vec4_cse.cpp
  31  *
  32  * Support for local common subexpression elimination.
  33  *
  34  * See Muchnick's Advanced Compiler Design and Implementation, section
  35  * 13.1 (p378).
  36  */
  37
  38 namespace {
  39 struct aeb_entry : public exec_node {
  40    /** The instruction that generates the expression value. */
  41    vec4_instruction *generator;
  42
  43    /** The temporary where the value is stored. */
  44    src_reg tmp;
  45 };
  46 }
  47
  48 static bool
  49 is_expression(const vec4_instruction *const inst)
  50 {
  51    switch (inst->opcode) {
  52    case BRW_OPCODE_MOV:
  53    case BRW_OPCODE_SEL:
  54    case BRW_OPCODE_NOT:
  55    case BRW_OPCODE_AND:
  56    case BRW_OPCODE_OR:
  57    case BRW_OPCODE_XOR:
  58    case BRW_OPCODE_SHR:
  59    case BRW_OPCODE_SHL:
  60    case BRW_OPCODE_ASR:
  61    case BRW_OPCODE_CMP:
  62    case BRW_OPCODE_CMPN:
  63    case BRW_OPCODE_ADD:
  64    case BRW_OPCODE_MUL:
  65    case BRW_OPCODE_FRC:
  66    case BRW_OPCODE_RNDU:
  67    case BRW_OPCODE_RNDD:
  68    case BRW_OPCODE_RNDE:
  69    case BRW_OPCODE_RNDZ:
  70    case BRW_OPCODE_LINE:
  71    case BRW_OPCODE_PLN:
  72    case BRW_OPCODE_MAD:
  73    case BRW_OPCODE_LRP:
  74    case VEC4_OPCODE_UNPACK_UNIFORM:
  75       return true;
  76    case SHADER_OPCODE_RCP:
  77    case SHADER_OPCODE_RSQ:
  78    case SHADER_OPCODE_SQRT:
  79    case SHADER_OPCODE_EXP2:
  80    case SHADER_OPCODE_LOG2:
  81    case SHADER_OPCODE_POW:
  82    case SHADER_OPCODE_INT_QUOTIENT:
  83    case SHADER_OPCODE_INT_REMAINDER:
  84    case SHADER_OPCODE_SIN:
  85    case SHADER_OPCODE_COS:
  86       return inst->mlen == 0;
  87    default:
  88       return false;
  89    }
  90 }
  91
  92 static bool
  93 operands_match(const vec4_instruction *a, const vec4_instruction *b)
  94 {
  95    const src_reg *xs = a->src;
  96    const src_reg *ys = b->src;
  97
  98    if (a->opcode == BRW_OPCODE_MAD) {
  99       return xs[0].equals(ys[0]) &&
 100              ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
 101               (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
 102    } else if (!a->is_commutative()) {
 103       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 104    } else {
 105       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 106              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 107    }
 108 }
 109
 110 static bool
 111 instructions_match(vec4_instruction *a, vec4_instruction *b)
 112 {
 113    return a->opcode == b->opcode &&
 114           a->saturate == b->saturate &&
 115           a->conditional_mod == b->conditional_mod &&
 116           a->dst.type == b->dst.type &&
 117           a->dst.writemask == b->dst.writemask &&
 118           a->force_writemask_all == b->force_writemask_all &&
 119           a->regs_written == b->regs_written &&
 120           operands_match(a, b);
 121 }
 122
 123 bool
 124 vec4_visitor::opt_cse_local(bblock_t *block)
 125 {
 126    bool progress = false;
 127    exec_list aeb;
 128
 129    void *cse_ctx = ralloc_context(NULL);
 130
 131    int ip = block->start_ip;
 132    foreach_inst_in_block (vec4_instruction, inst, block) {
 133       /* Skip some cases. */
 134       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 135           (inst->dst.file != HW_REG || inst->dst.is_null()))
 136       {
 137          bool found = false;
 138
 139          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 140             /* Match current instruction's expression against those in AEB. */
 141             if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
 142                 instructions_match(inst, entry->generator)) {
 143                found = true;
 144                progress = true;
 145                break;
 146             }
 147          }
 148
 149          if (!found) {
 150             if (inst->opcode != BRW_OPCODE_MOV ||
 151                 (inst->opcode == BRW_OPCODE_MOV &&
 152                  inst->src[0].file == IMM &&
 153                  inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
 154                /* Our first sighting of this expression.  Create an entry. */
 155                aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 156                entry->tmp = src_reg(); /* file will be BAD_FILE */
 157                entry->generator = inst;
 158                aeb.push_tail(entry);
 159             }
 160          } else {
 161             /* This is at least our second sighting of this expression.
 162              * If we don't have a temporary already, make one.
 163              */
 164             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 165             if (no_existing_temp && !entry->generator->dst.is_null()) {
 166                entry->tmp = retype(src_reg(GRF, alloc.allocate(
 167                                               entry->generator->regs_written),
 168                                            NULL), inst->dst.type);
 169
 170                for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
 171                   vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
 172                                                offset(entry->tmp, i));
 173                   copy->force_writemask_all =
 174                      entry->generator->force_writemask_all;
 175                   entry->generator->insert_after(block, copy);
 176                }
 177
 178                entry->generator->dst = dst_reg(entry->tmp);
 179             }
 180
 181             /* dest <- temp */
 182             if (!inst->dst.is_null()) {
 183                assert(inst->dst.type == entry->tmp.type);
 184
 185                for (unsigned i = 0; i < inst->regs_written; ++i) {
 186                   vec4_instruction *copy = MOV(offset(inst->dst, i),
 187                                                offset(entry->tmp, i));
 188                   copy->force_writemask_all = inst->force_writemask_all;
 189                   inst->insert_before(block, copy);
 190                }
 191             }
 192
 193             /* Set our iterator so that next time through the loop inst->next
 194              * will get the instruction in the basic block after the one we've
 195              * removed.
 196              */
 197             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 198
 199             inst->remove(block);
 200             inst = prev;
 201          }
 202       }
 203
 204       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 205          /* Kill all AEB entries that write a different value to or read from
 206           * the flag register if we just wrote it.
 207           */
 208          if (inst->writes_flag()) {
 209             if (entry->generator->reads_flag() ||
 210                 (entry->generator->writes_flag() &&
 211                  !instructions_match(inst, entry->generator))) {
 212                entry->remove();
 213                ralloc_free(entry);
 214                continue;
 215             }
 216          }
 217
 218          for (int i = 0; i < 3; i++) {
 219             src_reg *src = &entry->generator->src[i];
 220
 221             /* Kill all AEB entries that use the destination we just
 222              * overwrote.
 223              */
 224             if (inst->dst.file == entry->generator->src[i].file &&
 225                 inst->dst.reg == entry->generator->src[i].reg) {
 226                entry->remove();
 227                ralloc_free(entry);
 228                break;
 229             }
 230
 231             /* Kill any AEB entries using registers that don't get reused any
 232              * more -- a sure sign they'll fail operands_match().
 233              */
 234             if (src->file == GRF) {
 235                if (var_range_end(var_from_reg(alloc, *src), 4) < ip) {
 236                   entry->remove();
 237                   ralloc_free(entry);
 238                   break;
 239                }
 240             }
 241          }
 242       }
 243
 244       ip++;
 245    }
 246
 247    ralloc_free(cse_ctx);
 248
 249    return progress;
 250 }
 251
 252 bool
 253 vec4_visitor::opt_cse()
 254 {
 255    bool progress = false;
 256
 257    calculate_live_intervals();
 258
 259    foreach_block (block, cfg) {
 260       progress = opt_cse_local(block) || progress;
 261    }
 262
 263    if (progress)
 264       invalidate_live_intervals();
 265
 266    return progress;
 267 }