src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_vec4_live_variables.h"
  26 #include "brw_cfg.h"
  27
  28 using namespace brw;
  29
  30 /** @file brw_vec4_cse.cpp
  31  *
  32  * Support for local common subexpression elimination.
  33  *
  34  * See Muchnick's Advanced Compiler Design and Implementation, section
  35  * 13.1 (p378).
  36  */
  37
  38 namespace {
  39 struct aeb_entry : public exec_node {
  40    /** The instruction that generates the expression value. */
  41    vec4_instruction *generator;
  42
  43    /** The temporary where the value is stored. */
  44    src_reg tmp;
  45 };
  46 }
  47
  48 static bool
  49 is_expression(const vec4_instruction *const inst)
  50 {
  51    switch (inst->opcode) {
  52    case BRW_OPCODE_MOV:
  53    case BRW_OPCODE_SEL:
  54    case BRW_OPCODE_NOT:
  55    case BRW_OPCODE_AND:
  56    case BRW_OPCODE_OR:
  57    case BRW_OPCODE_XOR:
  58    case BRW_OPCODE_SHR:
  59    case BRW_OPCODE_SHL:
  60    case BRW_OPCODE_ASR:
  61    case BRW_OPCODE_CMP:
  62    case BRW_OPCODE_CMPN:
  63    case BRW_OPCODE_ADD:
  64    case BRW_OPCODE_MUL:
  65    case SHADER_OPCODE_MULH:
  66    case BRW_OPCODE_FRC:
  67    case BRW_OPCODE_RNDU:
  68    case BRW_OPCODE_RNDD:
  69    case BRW_OPCODE_RNDE:
  70    case BRW_OPCODE_RNDZ:
  71    case BRW_OPCODE_LINE:
  72    case BRW_OPCODE_PLN:
  73    case BRW_OPCODE_MAD:
  74    case BRW_OPCODE_LRP:
  75    case VEC4_OPCODE_UNPACK_UNIFORM:
  76    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
  77    case SHADER_OPCODE_BROADCAST:
  78       return true;
  79    case SHADER_OPCODE_RCP:
  80    case SHADER_OPCODE_RSQ:
  81    case SHADER_OPCODE_SQRT:
  82    case SHADER_OPCODE_EXP2:
  83    case SHADER_OPCODE_LOG2:
  84    case SHADER_OPCODE_POW:
  85    case SHADER_OPCODE_INT_QUOTIENT:
  86    case SHADER_OPCODE_INT_REMAINDER:
  87    case SHADER_OPCODE_SIN:
  88    case SHADER_OPCODE_COS:
  89       return inst->mlen == 0;
  90    default:
  91       return false;
  92    }
  93 }
  94
  95 static bool
  96 operands_match(const vec4_instruction *a, const vec4_instruction *b)
  97 {
  98    const src_reg *xs = a->src;
  99    const src_reg *ys = b->src;
 100
 101    if (a->opcode == BRW_OPCODE_MAD) {
 102       return xs[0].equals(ys[0]) &&
 103              ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
 104               (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
 105    } else if (!a->is_commutative()) {
 106       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 107    } else {
 108       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 109              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 110    }
 111 }
 112
 113 static bool
 114 instructions_match(vec4_instruction *a, vec4_instruction *b)
 115 {
 116    return a->opcode == b->opcode &&
 117           a->saturate == b->saturate &&
 118           a->predicate == b->predicate &&
 119           a->predicate_inverse == b->predicate_inverse &&
 120           a->conditional_mod == b->conditional_mod &&
 121           a->flag_subreg == b->flag_subreg &&
 122           a->dst.type == b->dst.type &&
 123           a->offset == b->offset &&
 124           a->mlen == b->mlen &&
 125           a->base_mrf == b->base_mrf &&
 126           a->header_size == b->header_size &&
 127           a->shadow_compare == b->shadow_compare &&
 128           a->dst.writemask == b->dst.writemask &&
 129           a->force_writemask_all == b->force_writemask_all &&
 130           a->regs_written == b->regs_written &&
 131           operands_match(a, b);
 132 }
 133
 134 bool
 135 vec4_visitor::opt_cse_local(bblock_t *block)
 136 {
 137    bool progress = false;
 138    exec_list aeb;
 139
 140    void *cse_ctx = ralloc_context(NULL);
 141
 142    int ip = block->start_ip;
 143    foreach_inst_in_block (vec4_instruction, inst, block) {
 144       /* Skip some cases. */
 145       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 146           (inst->dst.file != HW_REG || inst->dst.is_null()))
 147       {
 148          bool found = false;
 149
 150          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 151             /* Match current instruction's expression against those in AEB. */
 152             if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
 153                 instructions_match(inst, entry->generator)) {
 154                found = true;
 155                progress = true;
 156                break;
 157             }
 158          }
 159
 160          if (!found) {
 161             if (inst->opcode != BRW_OPCODE_MOV ||
 162                 (inst->opcode == BRW_OPCODE_MOV &&
 163                  inst->src[0].file == IMM &&
 164                  inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
 165                /* Our first sighting of this expression.  Create an entry. */
 166                aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 167                entry->tmp = src_reg(); /* file will be BAD_FILE */
 168                entry->generator = inst;
 169                aeb.push_tail(entry);
 170             }
 171          } else {
 172             /* This is at least our second sighting of this expression.
 173              * If we don't have a temporary already, make one.
 174              */
 175             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 176             if (no_existing_temp && !entry->generator->dst.is_null()) {
 177                entry->tmp = retype(src_reg(GRF, alloc.allocate(
 178                                               entry->generator->regs_written),
 179                                            NULL), inst->dst.type);
 180
 181                for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
 182                   vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
 183                                                offset(entry->tmp, i));
 184                   copy->force_writemask_all =
 185                      entry->generator->force_writemask_all;
 186                   entry->generator->insert_after(block, copy);
 187                }
 188
 189                entry->generator->dst = dst_reg(entry->tmp);
 190             }
 191
 192             /* dest <- temp */
 193             if (!inst->dst.is_null()) {
 194                assert(inst->dst.type == entry->tmp.type);
 195
 196                for (unsigned i = 0; i < inst->regs_written; ++i) {
 197                   vec4_instruction *copy = MOV(offset(inst->dst, i),
 198                                                offset(entry->tmp, i));
 199                   copy->force_writemask_all = inst->force_writemask_all;
 200                   inst->insert_before(block, copy);
 201                }
 202             }
 203
 204             /* Set our iterator so that next time through the loop inst->next
 205              * will get the instruction in the basic block after the one we've
 206              * removed.
 207              */
 208             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 209
 210             inst->remove(block);
 211             inst = prev;
 212          }
 213       }
 214
 215       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 216          /* Kill all AEB entries that write a different value to or read from
 217           * the flag register if we just wrote it.
 218           */
 219          if (inst->writes_flag()) {
 220             if (entry->generator->reads_flag() ||
 221                 (entry->generator->writes_flag() &&
 222                  !instructions_match(inst, entry->generator))) {
 223                entry->remove();
 224                ralloc_free(entry);
 225                continue;
 226             }
 227          }
 228
 229          for (int i = 0; i < 3; i++) {
 230             src_reg *src = &entry->generator->src[i];
 231
 232             /* Kill all AEB entries that use the destination we just
 233              * overwrote.
 234              */
 235             if (inst->dst.file == entry->generator->src[i].file &&
 236                 inst->dst.reg == entry->generator->src[i].reg) {
 237                entry->remove();
 238                ralloc_free(entry);
 239                break;
 240             }
 241
 242             /* Kill any AEB entries using registers that don't get reused any
 243              * more -- a sure sign they'll fail operands_match().
 244              */
 245             if (src->file == GRF) {
 246                if (var_range_end(var_from_reg(alloc, *src), 4) < ip) {
 247                   entry->remove();
 248                   ralloc_free(entry);
 249                   break;
 250                }
 251             }
 252          }
 253       }
 254
 255       ip++;
 256    }
 257
 258    ralloc_free(cse_ctx);
 259
 260    return progress;
 261 }
 262
 263 bool
 264 vec4_visitor::opt_cse()
 265 {
 266    bool progress = false;
 267
 268    calculate_live_intervals();
 269
 270    foreach_block (block, cfg) {
 271       progress = opt_cse_local(block) || progress;
 272    }
 273
 274    if (progress)
 275       invalidate_live_intervals();
 276
 277    return progress;
 278 }