src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_cfg.h"
  26
  27 using namespace brw;
  28
  29 /** @file brw_vec4_cse.cpp
  30  *
  31  * Support for local common subexpression elimination.
  32  *
  33  * See Muchnick's Advanced Compiler Design and Implementation, section
  34  * 13.1 (p378).
  35  */
  36
  37 namespace {
  38 struct aeb_entry : public exec_node {
  39    /** The instruction that generates the expression value. */
  40    vec4_instruction *generator;
  41
  42    /** The temporary where the value is stored. */
  43    src_reg tmp;
  44 };
  45 }
  46
  47 static bool
  48 is_expression(const vec4_instruction *const inst)
  49 {
  50    switch (inst->opcode) {
  51    case BRW_OPCODE_MOV:
  52    case BRW_OPCODE_SEL:
  53    case BRW_OPCODE_NOT:
  54    case BRW_OPCODE_AND:
  55    case BRW_OPCODE_OR:
  56    case BRW_OPCODE_XOR:
  57    case BRW_OPCODE_SHR:
  58    case BRW_OPCODE_SHL:
  59    case BRW_OPCODE_ASR:
  60    case BRW_OPCODE_CMP:
  61    case BRW_OPCODE_CMPN:
  62    case BRW_OPCODE_ADD:
  63    case BRW_OPCODE_MUL:
  64    case BRW_OPCODE_FRC:
  65    case BRW_OPCODE_RNDU:
  66    case BRW_OPCODE_RNDD:
  67    case BRW_OPCODE_RNDE:
  68    case BRW_OPCODE_RNDZ:
  69    case BRW_OPCODE_LINE:
  70    case BRW_OPCODE_PLN:
  71    case BRW_OPCODE_MAD:
  72    case BRW_OPCODE_LRP:
  73    case VEC4_OPCODE_UNPACK_UNIFORM:
  74       return true;
  75    case SHADER_OPCODE_RCP:
  76    case SHADER_OPCODE_RSQ:
  77    case SHADER_OPCODE_SQRT:
  78    case SHADER_OPCODE_EXP2:
  79    case SHADER_OPCODE_LOG2:
  80    case SHADER_OPCODE_POW:
  81    case SHADER_OPCODE_INT_QUOTIENT:
  82    case SHADER_OPCODE_INT_REMAINDER:
  83    case SHADER_OPCODE_SIN:
  84    case SHADER_OPCODE_COS:
  85       return inst->mlen == 0;
  86    default:
  87       return false;
  88    }
  89 }
  90
  91 static bool
  92 is_expression_commutative(const vec4_instruction *inst)
  93 {
  94    switch (inst->opcode) {
  95    case BRW_OPCODE_AND:
  96    case BRW_OPCODE_OR:
  97    case BRW_OPCODE_XOR:
  98    case BRW_OPCODE_ADD:
  99    case BRW_OPCODE_MUL:
 100       return true;
 101    case BRW_OPCODE_SEL:
 102       /* MIN and MAX are commutative. */
 103       if (inst->conditional_mod == BRW_CONDITIONAL_GE ||
 104           inst->conditional_mod == BRW_CONDITIONAL_L) {
 105          return true;
 106       }
 107       /* fallthrough */
 108    default:
 109       return false;
 110    }
 111 }
 112
 113 static bool
 114 operands_match(const vec4_instruction *a, const vec4_instruction *b)
 115 {
 116    const src_reg *xs = a->src;
 117    const src_reg *ys = b->src;
 118
 119    if (a->opcode == BRW_OPCODE_MAD) {
 120       return xs[0].equals(ys[0]) &&
 121              ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
 122               (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
 123    } else if (!is_expression_commutative(a)) {
 124       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 125    } else {
 126       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 127              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 128    }
 129 }
 130
 131 static bool
 132 instructions_match(vec4_instruction *a, vec4_instruction *b)
 133 {
 134    return a->opcode == b->opcode &&
 135           a->saturate == b->saturate &&
 136           a->conditional_mod == b->conditional_mod &&
 137           a->dst.type == b->dst.type &&
 138           a->dst.writemask == b->dst.writemask &&
 139           operands_match(a, b);
 140 }
 141
 142 bool
 143 vec4_visitor::opt_cse_local(bblock_t *block)
 144 {
 145    bool progress = false;
 146    exec_list aeb;
 147
 148    void *cse_ctx = ralloc_context(NULL);
 149
 150    int ip = block->start_ip;
 151    foreach_inst_in_block (vec4_instruction, inst, block) {
 152       /* Skip some cases. */
 153       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 154           (inst->dst.file != HW_REG || inst->dst.is_null()))
 155       {
 156          bool found = false;
 157
 158          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 159             /* Match current instruction's expression against those in AEB. */
 160             if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
 161                 instructions_match(inst, entry->generator)) {
 162                found = true;
 163                progress = true;
 164                break;
 165             }
 166          }
 167
 168          if (!found) {
 169             if (inst->opcode != BRW_OPCODE_MOV ||
 170                 (inst->opcode == BRW_OPCODE_MOV &&
 171                  inst->src[0].file == IMM &&
 172                  inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
 173                /* Our first sighting of this expression.  Create an entry. */
 174                aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 175                entry->tmp = src_reg(); /* file will be BAD_FILE */
 176                entry->generator = inst;
 177                aeb.push_tail(entry);
 178             }
 179          } else {
 180             /* This is at least our second sighting of this expression.
 181              * If we don't have a temporary already, make one.
 182              */
 183             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 184             if (no_existing_temp && !entry->generator->dst.is_null()) {
 185                entry->tmp = src_reg(this, glsl_type::float_type);
 186                entry->tmp.type = inst->dst.type;
 187                entry->tmp.swizzle = BRW_SWIZZLE_XYZW;
 188
 189                vec4_instruction *copy = MOV(entry->generator->dst, entry->tmp);
 190                entry->generator->insert_after(block, copy);
 191                entry->generator->dst = dst_reg(entry->tmp);
 192             }
 193
 194             /* dest <- temp */
 195             if (!inst->dst.is_null()) {
 196                assert(inst->dst.type == entry->tmp.type);
 197                vec4_instruction *copy = MOV(inst->dst, entry->tmp);
 198                copy->force_writemask_all = inst->force_writemask_all;
 199                inst->insert_before(block, copy);
 200             }
 201
 202             /* Set our iterator so that next time through the loop inst->next
 203              * will get the instruction in the basic block after the one we've
 204              * removed.
 205              */
 206             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 207
 208             inst->remove(block);
 209             inst = prev;
 210          }
 211       }
 212
 213       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 214          /* Kill all AEB entries that write a different value to or read from
 215           * the flag register if we just wrote it.
 216           */
 217          if (inst->writes_flag()) {
 218             if (entry->generator->reads_flag() ||
 219                 (entry->generator->writes_flag() &&
 220                  !instructions_match(inst, entry->generator))) {
 221                entry->remove();
 222                ralloc_free(entry);
 223                continue;
 224             }
 225          }
 226
 227          for (int i = 0; i < 3; i++) {
 228             src_reg *src = &entry->generator->src[i];
 229
 230             /* Kill all AEB entries that use the destination we just
 231              * overwrote.
 232              */
 233             if (inst->dst.file == entry->generator->src[i].file &&
 234                 inst->dst.reg == entry->generator->src[i].reg) {
 235                entry->remove();
 236                ralloc_free(entry);
 237                break;
 238             }
 239
 240             /* Kill any AEB entries using registers that don't get reused any
 241              * more -- a sure sign they'll fail operands_match().
 242              */
 243             if (src->file == GRF) {
 244                assert((src->reg * 4 + 3) < (virtual_grf_count * 4));
 245
 246                int last_reg_use = MAX2(MAX2(virtual_grf_end[src->reg * 4 + 0],
 247                                             virtual_grf_end[src->reg * 4 + 1]),
 248                                        MAX2(virtual_grf_end[src->reg * 4 + 2],
 249                                             virtual_grf_end[src->reg * 4 + 3]));
 250                if (last_reg_use < ip) {
 251                   entry->remove();
 252                   ralloc_free(entry);
 253                   break;
 254                }
 255             }
 256          }
 257       }
 258
 259       ip++;
 260    }
 261
 262    ralloc_free(cse_ctx);
 263
 264    return progress;
 265 }
 266
 267 bool
 268 vec4_visitor::opt_cse()
 269 {
 270    bool progress = false;
 271
 272    calculate_live_intervals();
 273
 274    foreach_block (block, cfg) {
 275       progress = opt_cse_local(block) || progress;
 276    }
 277
 278    if (progress)
 279       invalidate_live_intervals();
 280
 281    return progress;
 282 }