src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_cfg.h"
  26
  27 using namespace brw;
  28
  29 /** @file brw_vec4_cse.cpp
  30  *
  31  * Support for local common subexpression elimination.
  32  *
  33  * See Muchnick's Advanced Compiler Design and Implementation, section
  34  * 13.1 (p378).
  35  */
  36
  37 namespace {
  38 struct aeb_entry : public exec_node {
  39    /** The instruction that generates the expression value. */
  40    vec4_instruction *generator;
  41
  42    /** The temporary where the value is stored. */
  43    src_reg tmp;
  44 };
  45 }
  46
  47 static bool
  48 is_expression(const vec4_instruction *const inst)
  49 {
  50    switch (inst->opcode) {
  51    case BRW_OPCODE_SEL:
  52    case BRW_OPCODE_NOT:
  53    case BRW_OPCODE_AND:
  54    case BRW_OPCODE_OR:
  55    case BRW_OPCODE_XOR:
  56    case BRW_OPCODE_SHR:
  57    case BRW_OPCODE_SHL:
  58    case BRW_OPCODE_ASR:
  59    case BRW_OPCODE_ADD:
  60    case BRW_OPCODE_MUL:
  61    case BRW_OPCODE_FRC:
  62    case BRW_OPCODE_RNDU:
  63    case BRW_OPCODE_RNDD:
  64    case BRW_OPCODE_RNDE:
  65    case BRW_OPCODE_RNDZ:
  66    case BRW_OPCODE_LINE:
  67    case BRW_OPCODE_PLN:
  68    case BRW_OPCODE_MAD:
  69    case BRW_OPCODE_LRP:
  70       return true;
  71    case SHADER_OPCODE_RCP:
  72    case SHADER_OPCODE_RSQ:
  73    case SHADER_OPCODE_SQRT:
  74    case SHADER_OPCODE_EXP2:
  75    case SHADER_OPCODE_LOG2:
  76    case SHADER_OPCODE_POW:
  77    case SHADER_OPCODE_INT_QUOTIENT:
  78    case SHADER_OPCODE_INT_REMAINDER:
  79    case SHADER_OPCODE_SIN:
  80    case SHADER_OPCODE_COS:
  81       return inst->mlen == 0;
  82    default:
  83       return false;
  84    }
  85 }
  86
  87 static bool
  88 is_expression_commutative(enum opcode op)
  89 {
  90    switch (op) {
  91    case BRW_OPCODE_AND:
  92    case BRW_OPCODE_OR:
  93    case BRW_OPCODE_XOR:
  94    case BRW_OPCODE_ADD:
  95    case BRW_OPCODE_MUL:
  96       return true;
  97    default:
  98       return false;
  99    }
 100 }
 101
 102 static bool
 103 operands_match(enum opcode op, src_reg *xs, src_reg *ys)
 104 {
 105    if (!is_expression_commutative(op)) {
 106       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 107    } else {
 108       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 109              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 110    }
 111 }
 112
 113 static bool
 114 instructions_match(vec4_instruction *a, vec4_instruction *b)
 115 {
 116    return a->opcode == b->opcode &&
 117           a->saturate == b->saturate &&
 118           a->conditional_mod == b->conditional_mod &&
 119           a->dst.type == b->dst.type &&
 120           a->dst.writemask == b->dst.writemask &&
 121           operands_match(a->opcode, a->src, b->src);
 122 }
 123
 124 bool
 125 vec4_visitor::opt_cse_local(bblock_t *block, exec_list *aeb)
 126 {
 127    bool progress = false;
 128
 129    void *cse_ctx = ralloc_context(NULL);
 130
 131    for (vec4_instruction *inst = (vec4_instruction *)block->start;
 132         inst != block->end->next;
 133         inst = (vec4_instruction *) inst->next) {
 134
 135       /* Skip some cases. */
 136       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 137           !inst->conditional_mod)
 138       {
 139          bool found = false;
 140
 141          foreach_in_list_use_after(aeb_entry, entry, aeb) {
 142             /* Match current instruction's expression against those in AEB. */
 143             if (instructions_match(inst, entry->generator)) {
 144                found = true;
 145                progress = true;
 146                break;
 147             }
 148          }
 149
 150          if (!found) {
 151             /* Our first sighting of this expression.  Create an entry. */
 152             aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 153             entry->tmp = src_reg(); /* file will be BAD_FILE */
 154             entry->generator = inst;
 155             aeb->push_tail(entry);
 156          } else {
 157             /* This is at least our second sighting of this expression.
 158              * If we don't have a temporary already, make one.
 159              */
 160             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 161             if (no_existing_temp) {
 162                entry->tmp = src_reg(this, glsl_type::float_type);
 163                entry->tmp.type = inst->dst.type;
 164                entry->tmp.swizzle = BRW_SWIZZLE_XYZW;
 165
 166                vec4_instruction *copy = MOV(entry->generator->dst, entry->tmp);
 167                entry->generator->insert_after(copy);
 168                entry->generator->dst = dst_reg(entry->tmp);
 169             }
 170
 171             /* dest <- temp */
 172             assert(inst->dst.type == entry->tmp.type);
 173             vec4_instruction *copy = MOV(inst->dst, entry->tmp);
 174             copy->force_writemask_all = inst->force_writemask_all;
 175             inst->insert_before(copy);
 176
 177             /* Set our iterator so that next time through the loop inst->next
 178              * will get the instruction in the basic block after the one we've
 179              * removed.
 180              */
 181             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 182
 183             inst->remove();
 184
 185             /* Appending an instruction may have changed our bblock end. */
 186             if (inst == block->end) {
 187                block->end = prev;
 188             }
 189
 190             inst = prev;
 191          }
 192       }
 193
 194       foreach_in_list_safe(aeb_entry, entry, aeb) {
 195          for (int i = 0; i < 3; i++) {
 196             /* Kill all AEB entries that use the destination we just
 197              * overwrote.
 198              */
 199             if (inst->dst.file == entry->generator->src[i].file &&
 200                 inst->dst.reg == entry->generator->src[i].reg) {
 201                entry->remove();
 202                ralloc_free(entry);
 203                break;
 204             }
 205          }
 206       }
 207    }
 208
 209    ralloc_free(cse_ctx);
 210
 211    if (progress)
 212       invalidate_live_intervals();
 213
 214    return progress;
 215 }
 216
 217 bool
 218 vec4_visitor::opt_cse()
 219 {
 220    bool progress = false;
 221
 222    cfg_t cfg(&instructions);
 223
 224    for (int b = 0; b < cfg.num_blocks; b++) {
 225       bblock_t *block = cfg.blocks[b];
 226       exec_list aeb;
 227
 228       progress = opt_cse_local(block, &aeb) || progress;
 229    }
 230
 231    return progress;
 232 }