src/mesa/drivers/dri/i965/brw_vec4_cse.cpp

   1 /*
   2  * Copyright © 2012, 2013, 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_cfg.h"
  26
  27 using namespace brw;
  28
  29 /** @file brw_vec4_cse.cpp
  30  *
  31  * Support for local common subexpression elimination.
  32  *
  33  * See Muchnick's Advanced Compiler Design and Implementation, section
  34  * 13.1 (p378).
  35  */
  36
  37 namespace {
  38 struct aeb_entry : public exec_node {
  39    /** The instruction that generates the expression value. */
  40    vec4_instruction *generator;
  41
  42    /** The temporary where the value is stored. */
  43    src_reg tmp;
  44 };
  45 }
  46
  47 static bool
  48 is_expression(const vec4_instruction *const inst)
  49 {
  50    switch (inst->opcode) {
  51    case BRW_OPCODE_SEL:
  52    case BRW_OPCODE_NOT:
  53    case BRW_OPCODE_AND:
  54    case BRW_OPCODE_OR:
  55    case BRW_OPCODE_XOR:
  56    case BRW_OPCODE_SHR:
  57    case BRW_OPCODE_SHL:
  58    case BRW_OPCODE_ASR:
  59    case BRW_OPCODE_CMP:
  60    case BRW_OPCODE_CMPN:
  61    case BRW_OPCODE_ADD:
  62    case BRW_OPCODE_MUL:
  63    case BRW_OPCODE_FRC:
  64    case BRW_OPCODE_RNDU:
  65    case BRW_OPCODE_RNDD:
  66    case BRW_OPCODE_RNDE:
  67    case BRW_OPCODE_RNDZ:
  68    case BRW_OPCODE_LINE:
  69    case BRW_OPCODE_PLN:
  70    case BRW_OPCODE_MAD:
  71    case BRW_OPCODE_LRP:
  72       return true;
  73    case SHADER_OPCODE_RCP:
  74    case SHADER_OPCODE_RSQ:
  75    case SHADER_OPCODE_SQRT:
  76    case SHADER_OPCODE_EXP2:
  77    case SHADER_OPCODE_LOG2:
  78    case SHADER_OPCODE_POW:
  79    case SHADER_OPCODE_INT_QUOTIENT:
  80    case SHADER_OPCODE_INT_REMAINDER:
  81    case SHADER_OPCODE_SIN:
  82    case SHADER_OPCODE_COS:
  83       return inst->mlen == 0;
  84    default:
  85       return false;
  86    }
  87 }
  88
  89 static bool
  90 is_expression_commutative(enum opcode op)
  91 {
  92    switch (op) {
  93    case BRW_OPCODE_AND:
  94    case BRW_OPCODE_OR:
  95    case BRW_OPCODE_XOR:
  96    case BRW_OPCODE_ADD:
  97    case BRW_OPCODE_MUL:
  98       return true;
  99    default:
 100       return false;
 101    }
 102 }
 103
 104 static bool
 105 operands_match(enum opcode op, src_reg *xs, src_reg *ys)
 106 {
 107    if (!is_expression_commutative(op)) {
 108       return xs[0].equals(ys[0]) && xs[1].equals(ys[1]) && xs[2].equals(ys[2]);
 109    } else {
 110       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 111              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 112    }
 113 }
 114
 115 static bool
 116 instructions_match(vec4_instruction *a, vec4_instruction *b)
 117 {
 118    return a->opcode == b->opcode &&
 119           a->saturate == b->saturate &&
 120           a->conditional_mod == b->conditional_mod &&
 121           a->dst.type == b->dst.type &&
 122           a->dst.writemask == b->dst.writemask &&
 123           operands_match(a->opcode, a->src, b->src);
 124 }
 125
 126 bool
 127 vec4_visitor::opt_cse_local(bblock_t *block)
 128 {
 129    bool progress = false;
 130    exec_list aeb;
 131
 132    void *cse_ctx = ralloc_context(NULL);
 133
 134    int ip = block->start_ip;
 135    foreach_inst_in_block (vec4_instruction, inst, block) {
 136       /* Skip some cases. */
 137       if (is_expression(inst) && !inst->predicate && inst->mlen == 0 &&
 138           (inst->dst.file != HW_REG || inst->dst.is_null()))
 139       {
 140          bool found = false;
 141
 142          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 143             /* Match current instruction's expression against those in AEB. */
 144             if (instructions_match(inst, entry->generator)) {
 145                found = true;
 146                progress = true;
 147                break;
 148             }
 149          }
 150
 151          if (!found) {
 152             /* Our first sighting of this expression.  Create an entry. */
 153             aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 154             entry->tmp = src_reg(); /* file will be BAD_FILE */
 155             entry->generator = inst;
 156             aeb.push_tail(entry);
 157          } else {
 158             /* This is at least our second sighting of this expression.
 159              * If we don't have a temporary already, make one.
 160              */
 161             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 162             if (no_existing_temp && !entry->generator->dst.is_null()) {
 163                entry->tmp = src_reg(this, glsl_type::float_type);
 164                entry->tmp.type = inst->dst.type;
 165                entry->tmp.swizzle = BRW_SWIZZLE_XYZW;
 166
 167                vec4_instruction *copy = MOV(entry->generator->dst, entry->tmp);
 168                entry->generator->insert_after(copy);
 169                entry->generator->dst = dst_reg(entry->tmp);
 170             }
 171
 172             /* dest <- temp */
 173             if (!inst->dst.is_null()) {
 174                assert(inst->dst.type == entry->tmp.type);
 175                vec4_instruction *copy = MOV(inst->dst, entry->tmp);
 176                copy->force_writemask_all = inst->force_writemask_all;
 177                inst->insert_before(copy);
 178             }
 179
 180             /* Set our iterator so that next time through the loop inst->next
 181              * will get the instruction in the basic block after the one we've
 182              * removed.
 183              */
 184             vec4_instruction *prev = (vec4_instruction *)inst->prev;
 185
 186             inst->remove();
 187
 188             /* Appending an instruction may have changed our bblock end. */
 189             if (inst == block->end) {
 190                block->end = prev;
 191             }
 192
 193             inst = prev;
 194          }
 195       }
 196
 197       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 198          /* Kill all AEB entries that write a different value to or read from
 199           * the flag register if we just wrote it.
 200           */
 201          if (inst->writes_flag()) {
 202             if (entry->generator->reads_flag() ||
 203                 (entry->generator->writes_flag() &&
 204                  !instructions_match(inst, entry->generator))) {
 205                entry->remove();
 206                ralloc_free(entry);
 207                continue;
 208             }
 209          }
 210
 211          for (int i = 0; i < 3; i++) {
 212             src_reg *src = &entry->generator->src[i];
 213
 214             /* Kill all AEB entries that use the destination we just
 215              * overwrote.
 216              */
 217             if (inst->dst.file == entry->generator->src[i].file &&
 218                 inst->dst.reg == entry->generator->src[i].reg) {
 219                entry->remove();
 220                ralloc_free(entry);
 221                break;
 222             }
 223
 224             /* Kill any AEB entries using registers that don't get reused any
 225              * more -- a sure sign they'll fail operands_match().
 226              */
 227             int last_reg_use = MAX2(MAX2(virtual_grf_end[src->reg * 4 + 0],
 228                                          virtual_grf_end[src->reg * 4 + 1]),
 229                                     MAX2(virtual_grf_end[src->reg * 4 + 2],
 230                                          virtual_grf_end[src->reg * 4 + 3]));
 231             if (src->file == GRF && last_reg_use < ip) {
 232                entry->remove();
 233                ralloc_free(entry);
 234                break;
 235             }
 236          }
 237       }
 238
 239       ip++;
 240    }
 241
 242    ralloc_free(cse_ctx);
 243
 244    return progress;
 245 }
 246
 247 bool
 248 vec4_visitor::opt_cse()
 249 {
 250    bool progress = false;
 251
 252    calculate_live_intervals();
 253
 254    for (int b = 0; b < cfg->num_blocks; b++) {
 255       bblock_t *block = cfg->blocks[b];
 256
 257       progress = opt_cse_local(block) || progress;
 258    }
 259
 260    if (progress)
 261       invalidate_live_intervals();
 262
 263    return progress;
 264 }