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25 #include "brw_vec4_live_variables.h"
30 /** @file brw_vec4_cse.cpp
32 * Support for local common subexpression elimination.
34 * See Muchnick's Advanced Compiler Design and Implementation, section
39 struct aeb_entry
: public exec_node
{
40 /** The instruction that generates the expression value. */
41 vec4_instruction
*generator
;
43 /** The temporary where the value is stored. */
49 is_expression(const vec4_instruction
*const inst
)
51 switch (inst
->opcode
) {
65 case SHADER_OPCODE_MULH
:
75 case VEC4_OPCODE_UNPACK_UNIFORM
:
76 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
77 case SHADER_OPCODE_BROADCAST
:
78 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
79 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
81 case SHADER_OPCODE_RCP
:
82 case SHADER_OPCODE_RSQ
:
83 case SHADER_OPCODE_SQRT
:
84 case SHADER_OPCODE_EXP2
:
85 case SHADER_OPCODE_LOG2
:
86 case SHADER_OPCODE_POW
:
87 case SHADER_OPCODE_INT_QUOTIENT
:
88 case SHADER_OPCODE_INT_REMAINDER
:
89 case SHADER_OPCODE_SIN
:
90 case SHADER_OPCODE_COS
:
91 return inst
->mlen
== 0;
98 operands_match(const vec4_instruction
*a
, const vec4_instruction
*b
)
100 const src_reg
*xs
= a
->src
;
101 const src_reg
*ys
= b
->src
;
103 if (a
->opcode
== BRW_OPCODE_MAD
) {
104 return xs
[0].equals(ys
[0]) &&
105 ((xs
[1].equals(ys
[1]) && xs
[2].equals(ys
[2])) ||
106 (xs
[2].equals(ys
[1]) && xs
[1].equals(ys
[2])));
107 } else if (!a
->is_commutative()) {
108 return xs
[0].equals(ys
[0]) && xs
[1].equals(ys
[1]) && xs
[2].equals(ys
[2]);
110 return (xs
[0].equals(ys
[0]) && xs
[1].equals(ys
[1])) ||
111 (xs
[1].equals(ys
[0]) && xs
[0].equals(ys
[1]));
116 instructions_match(vec4_instruction
*a
, vec4_instruction
*b
)
118 return a
->opcode
== b
->opcode
&&
119 a
->saturate
== b
->saturate
&&
120 a
->predicate
== b
->predicate
&&
121 a
->predicate_inverse
== b
->predicate_inverse
&&
122 a
->conditional_mod
== b
->conditional_mod
&&
123 a
->flag_subreg
== b
->flag_subreg
&&
124 a
->dst
.type
== b
->dst
.type
&&
125 a
->offset
== b
->offset
&&
126 a
->mlen
== b
->mlen
&&
127 a
->base_mrf
== b
->base_mrf
&&
128 a
->header_size
== b
->header_size
&&
129 a
->shadow_compare
== b
->shadow_compare
&&
130 a
->dst
.writemask
== b
->dst
.writemask
&&
131 a
->force_writemask_all
== b
->force_writemask_all
&&
132 a
->regs_written
== b
->regs_written
&&
133 operands_match(a
, b
);
137 vec4_visitor::opt_cse_local(bblock_t
*block
)
139 bool progress
= false;
142 void *cse_ctx
= ralloc_context(NULL
);
144 int ip
= block
->start_ip
;
145 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
146 /* Skip some cases. */
147 if (is_expression(inst
) && !inst
->predicate
&& inst
->mlen
== 0 &&
148 ((inst
->dst
.file
!= ARF
&& inst
->dst
.file
!= FIXED_GRF
) ||
149 inst
->dst
.is_null()))
153 foreach_in_list_use_after(aeb_entry
, entry
, &aeb
) {
154 /* Match current instruction's expression against those in AEB. */
155 if (!(entry
->generator
->dst
.is_null() && !inst
->dst
.is_null()) &&
156 instructions_match(inst
, entry
->generator
)) {
164 if (inst
->opcode
!= BRW_OPCODE_MOV
||
165 (inst
->opcode
== BRW_OPCODE_MOV
&&
166 inst
->src
[0].file
== IMM
&&
167 inst
->src
[0].type
== BRW_REGISTER_TYPE_VF
)) {
168 /* Our first sighting of this expression. Create an entry. */
169 aeb_entry
*entry
= ralloc(cse_ctx
, aeb_entry
);
170 entry
->tmp
= src_reg(); /* file will be BAD_FILE */
171 entry
->generator
= inst
;
172 aeb
.push_tail(entry
);
175 /* This is at least our second sighting of this expression.
176 * If we don't have a temporary already, make one.
178 bool no_existing_temp
= entry
->tmp
.file
== BAD_FILE
;
179 if (no_existing_temp
&& !entry
->generator
->dst
.is_null()) {
180 entry
->tmp
= retype(src_reg(VGRF
, alloc
.allocate(
181 entry
->generator
->regs_written
),
182 NULL
), inst
->dst
.type
);
184 for (unsigned i
= 0; i
< entry
->generator
->regs_written
; ++i
) {
185 vec4_instruction
*copy
= MOV(offset(entry
->generator
->dst
, i
),
186 offset(entry
->tmp
, i
));
187 copy
->force_writemask_all
=
188 entry
->generator
->force_writemask_all
;
189 entry
->generator
->insert_after(block
, copy
);
192 entry
->generator
->dst
= dst_reg(entry
->tmp
);
196 if (!inst
->dst
.is_null()) {
197 assert(inst
->dst
.type
== entry
->tmp
.type
);
199 for (unsigned i
= 0; i
< inst
->regs_written
; ++i
) {
200 vec4_instruction
*copy
= MOV(offset(inst
->dst
, i
),
201 offset(entry
->tmp
, i
));
202 copy
->force_writemask_all
= inst
->force_writemask_all
;
203 inst
->insert_before(block
, copy
);
207 /* Set our iterator so that next time through the loop inst->next
208 * will get the instruction in the basic block after the one we've
211 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
218 foreach_in_list_safe(aeb_entry
, entry
, &aeb
) {
219 /* Kill all AEB entries that write a different value to or read from
220 * the flag register if we just wrote it.
222 if (inst
->writes_flag()) {
223 if (entry
->generator
->reads_flag() ||
224 (entry
->generator
->writes_flag() &&
225 !instructions_match(inst
, entry
->generator
))) {
232 for (int i
= 0; i
< 3; i
++) {
233 src_reg
*src
= &entry
->generator
->src
[i
];
235 /* Kill all AEB entries that use the destination we just
238 if (inst
->dst
.file
== entry
->generator
->src
[i
].file
&&
239 inst
->dst
.nr
== entry
->generator
->src
[i
].nr
) {
245 /* Kill any AEB entries using registers that don't get reused any
246 * more -- a sure sign they'll fail operands_match().
248 if (src
->file
== VGRF
) {
249 if (var_range_end(var_from_reg(alloc
, dst_reg(*src
)), 4) < ip
) {
261 ralloc_free(cse_ctx
);
267 vec4_visitor::opt_cse()
269 bool progress
= false;
271 calculate_live_intervals();
273 foreach_block (block
, cfg
) {
274 progress
= opt_cse_local(block
) || progress
;
278 invalidate_live_intervals();