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25 #include "brw_vec4_live_variables.h"
30 /** @file brw_vec4_cse.cpp
32 * Support for local common subexpression elimination.
34 * See Muchnick's Advanced Compiler Design and Implementation, section
39 struct aeb_entry
: public exec_node
{
40 /** The instruction that generates the expression value. */
41 vec4_instruction
*generator
;
43 /** The temporary where the value is stored. */
49 is_expression(const vec4_instruction
*const inst
)
51 switch (inst
->opcode
) {
74 case VEC4_OPCODE_UNPACK_UNIFORM
:
75 case SHADER_OPCODE_BROADCAST
:
77 case SHADER_OPCODE_RCP
:
78 case SHADER_OPCODE_RSQ
:
79 case SHADER_OPCODE_SQRT
:
80 case SHADER_OPCODE_EXP2
:
81 case SHADER_OPCODE_LOG2
:
82 case SHADER_OPCODE_POW
:
83 case SHADER_OPCODE_INT_QUOTIENT
:
84 case SHADER_OPCODE_INT_REMAINDER
:
85 case SHADER_OPCODE_SIN
:
86 case SHADER_OPCODE_COS
:
87 return inst
->mlen
== 0;
94 operands_match(const vec4_instruction
*a
, const vec4_instruction
*b
)
96 const src_reg
*xs
= a
->src
;
97 const src_reg
*ys
= b
->src
;
99 if (a
->opcode
== BRW_OPCODE_MAD
) {
100 return xs
[0].equals(ys
[0]) &&
101 ((xs
[1].equals(ys
[1]) && xs
[2].equals(ys
[2])) ||
102 (xs
[2].equals(ys
[1]) && xs
[1].equals(ys
[2])));
103 } else if (!a
->is_commutative()) {
104 return xs
[0].equals(ys
[0]) && xs
[1].equals(ys
[1]) && xs
[2].equals(ys
[2]);
106 return (xs
[0].equals(ys
[0]) && xs
[1].equals(ys
[1])) ||
107 (xs
[1].equals(ys
[0]) && xs
[0].equals(ys
[1]));
112 instructions_match(vec4_instruction
*a
, vec4_instruction
*b
)
114 return a
->opcode
== b
->opcode
&&
115 a
->saturate
== b
->saturate
&&
116 a
->conditional_mod
== b
->conditional_mod
&&
117 a
->dst
.type
== b
->dst
.type
&&
118 a
->dst
.writemask
== b
->dst
.writemask
&&
119 a
->force_writemask_all
== b
->force_writemask_all
&&
120 a
->regs_written
== b
->regs_written
&&
121 operands_match(a
, b
);
125 vec4_visitor::opt_cse_local(bblock_t
*block
)
127 bool progress
= false;
130 void *cse_ctx
= ralloc_context(NULL
);
132 int ip
= block
->start_ip
;
133 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
134 /* Skip some cases. */
135 if (is_expression(inst
) && !inst
->predicate
&& inst
->mlen
== 0 &&
136 (inst
->dst
.file
!= HW_REG
|| inst
->dst
.is_null()))
140 foreach_in_list_use_after(aeb_entry
, entry
, &aeb
) {
141 /* Match current instruction's expression against those in AEB. */
142 if (!(entry
->generator
->dst
.is_null() && !inst
->dst
.is_null()) &&
143 instructions_match(inst
, entry
->generator
)) {
151 if (inst
->opcode
!= BRW_OPCODE_MOV
||
152 (inst
->opcode
== BRW_OPCODE_MOV
&&
153 inst
->src
[0].file
== IMM
&&
154 inst
->src
[0].type
== BRW_REGISTER_TYPE_VF
)) {
155 /* Our first sighting of this expression. Create an entry. */
156 aeb_entry
*entry
= ralloc(cse_ctx
, aeb_entry
);
157 entry
->tmp
= src_reg(); /* file will be BAD_FILE */
158 entry
->generator
= inst
;
159 aeb
.push_tail(entry
);
162 /* This is at least our second sighting of this expression.
163 * If we don't have a temporary already, make one.
165 bool no_existing_temp
= entry
->tmp
.file
== BAD_FILE
;
166 if (no_existing_temp
&& !entry
->generator
->dst
.is_null()) {
167 entry
->tmp
= retype(src_reg(GRF
, alloc
.allocate(
168 entry
->generator
->regs_written
),
169 NULL
), inst
->dst
.type
);
171 for (unsigned i
= 0; i
< entry
->generator
->regs_written
; ++i
) {
172 vec4_instruction
*copy
= MOV(offset(entry
->generator
->dst
, i
),
173 offset(entry
->tmp
, i
));
174 copy
->force_writemask_all
=
175 entry
->generator
->force_writemask_all
;
176 entry
->generator
->insert_after(block
, copy
);
179 entry
->generator
->dst
= dst_reg(entry
->tmp
);
183 if (!inst
->dst
.is_null()) {
184 assert(inst
->dst
.type
== entry
->tmp
.type
);
186 for (unsigned i
= 0; i
< inst
->regs_written
; ++i
) {
187 vec4_instruction
*copy
= MOV(offset(inst
->dst
, i
),
188 offset(entry
->tmp
, i
));
189 copy
->force_writemask_all
= inst
->force_writemask_all
;
190 inst
->insert_before(block
, copy
);
194 /* Set our iterator so that next time through the loop inst->next
195 * will get the instruction in the basic block after the one we've
198 vec4_instruction
*prev
= (vec4_instruction
*)inst
->prev
;
205 foreach_in_list_safe(aeb_entry
, entry
, &aeb
) {
206 /* Kill all AEB entries that write a different value to or read from
207 * the flag register if we just wrote it.
209 if (inst
->writes_flag()) {
210 if (entry
->generator
->reads_flag() ||
211 (entry
->generator
->writes_flag() &&
212 !instructions_match(inst
, entry
->generator
))) {
219 for (int i
= 0; i
< 3; i
++) {
220 src_reg
*src
= &entry
->generator
->src
[i
];
222 /* Kill all AEB entries that use the destination we just
225 if (inst
->dst
.file
== entry
->generator
->src
[i
].file
&&
226 inst
->dst
.reg
== entry
->generator
->src
[i
].reg
) {
232 /* Kill any AEB entries using registers that don't get reused any
233 * more -- a sure sign they'll fail operands_match().
235 if (src
->file
== GRF
) {
236 if (var_range_end(var_from_reg(alloc
, *src
), 4) < ip
) {
248 ralloc_free(cse_ctx
);
254 vec4_visitor::opt_cse()
256 bool progress
= false;
258 calculate_live_intervals();
260 foreach_block (block
, cfg
) {
261 progress
= opt_cse_local(block
) || progress
;
265 invalidate_live_intervals();