2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "brw_vec4_live_variables.h"
28 /** @file brw_vec4_dead_code_eliminate.cpp
30 * Dataflow-aware dead code elimination.
32 * Walks the instruction list from the bottom, removing instructions that
33 * have results that both aren't used in later blocks and haven't been read
34 * yet in the tail end of this block.
40 can_do_writemask(const struct brw_context
*brw
,
41 const vec4_instruction
*inst
)
43 switch (inst
->opcode
) {
44 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
45 case VS_OPCODE_PULL_CONSTANT_LOAD
:
46 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
49 /* The MATH instruction on Gen6 only executes in align1 mode, which does
50 * not support writemasking.
52 if (brw
->gen
== 6 && inst
->is_math())
63 vec4_visitor::dead_code_eliminate()
65 bool progress
= false;
67 calculate_live_intervals();
69 int num_vars
= live_intervals
->num_vars
;
70 BITSET_WORD
*live
= ralloc_array(NULL
, BITSET_WORD
, BITSET_WORDS(num_vars
));
71 BITSET_WORD
*flag_live
= ralloc_array(NULL
, BITSET_WORD
, 1);
73 foreach_block(block
, cfg
) {
74 memcpy(live
, live_intervals
->block_data
[block
->num
].liveout
,
75 sizeof(BITSET_WORD
) * BITSET_WORDS(num_vars
));
76 memcpy(flag_live
, live_intervals
->block_data
[block
->num
].flag_liveout
,
79 foreach_inst_in_block_reverse(vec4_instruction
, inst
, block
) {
80 if (inst
->dst
.file
== GRF
&& !inst
->has_side_effects()) {
81 bool result_live
[4] = { false };
83 for (int c
= 0; c
< 4; c
++) {
84 int var
= inst
->dst
.reg
* 4 + c
;
85 result_live
[c
] = BITSET_TEST(live
, var
);
88 /* If the instruction can't do writemasking, then it's all or
91 if (!can_do_writemask(brw
, inst
)) {
92 bool result
= result_live
[0] | result_live
[1] |
93 result_live
[2] | result_live
[3];
94 result_live
[0] = result
;
95 result_live
[1] = result
;
96 result_live
[2] = result
;
97 result_live
[3] = result
;
100 for (int c
= 0; c
< 4; c
++) {
101 if (!result_live
[c
] && inst
->dst
.writemask
& (1 << c
)) {
102 inst
->dst
.writemask
&= ~(1 << c
);
105 if (inst
->dst
.writemask
== 0) {
106 if (inst
->writes_accumulator
|| inst
->writes_flag()) {
107 inst
->dst
= dst_reg(retype(brw_null_reg(), inst
->dst
.type
));
109 inst
->opcode
= BRW_OPCODE_NOP
;
117 if (inst
->dst
.is_null() && inst
->writes_flag()) {
118 if (!BITSET_TEST(flag_live
, 0)) {
119 inst
->opcode
= BRW_OPCODE_NOP
;
125 if (inst
->dst
.file
== GRF
&& !inst
->predicate
) {
126 for (int c
= 0; c
< 4; c
++) {
127 if (inst
->dst
.writemask
& (1 << c
)) {
128 int var
= inst
->dst
.reg
* 4 + c
;
129 BITSET_CLEAR(live
, var
);
134 if (inst
->writes_flag()) {
135 BITSET_CLEAR(flag_live
, 0);
138 for (int i
= 0; i
< 3; i
++) {
139 if (inst
->src
[i
].file
== GRF
) {
140 for (int c
= 0; c
< 4; c
++) {
141 int swiz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
);
142 int var
= inst
->src
[i
].reg
* 4 + swiz
;
144 BITSET_SET(live
, var
);
149 if (inst
->reads_flag()) {
150 BITSET_SET(flag_live
, 0);
156 ralloc_free(flag_live
);
159 foreach_block_and_inst_safe(block
, backend_instruction
, inst
, cfg
) {
160 if (inst
->opcode
== BRW_OPCODE_NOP
) {
165 invalidate_live_intervals();