src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_vec4.h"
  25 #include "brw_vec4_live_variables.h"
  26 #include "brw_cfg.h"
  27
  28 /** @file brw_vec4_dead_code_eliminate.cpp
  29  *
  30  * Dataflow-aware dead code elimination.
  31  *
  32  * Walks the instruction list from the bottom, removing instructions that
  33  * have results that both aren't used in later blocks and haven't been read
  34  * yet in the tail end of this block.
  35  */
  36
  37 using namespace brw;
  38
  39 static bool
  40 can_do_writemask(const struct brw_device_info *devinfo,
  41                  const vec4_instruction *inst)
  42 {
  43    switch (inst->opcode) {
  44    case SHADER_OPCODE_GEN4_SCRATCH_READ:
  45    case VS_OPCODE_PULL_CONSTANT_LOAD:
  46    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
  47    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
  48       return false;
  49    default:
  50       /* The MATH instruction on Gen6 only executes in align1 mode, which does
  51        * not support writemasking.
  52        */
  53       if (devinfo->gen == 6 && inst->is_math())
  54          return false;
  55
  56       if (inst->is_tex())
  57          return false;
  58
  59       return true;
  60    }
  61 }
  62
  63 bool
  64 vec4_visitor::dead_code_eliminate()
  65 {
  66    bool progress = false;
  67
  68    calculate_live_intervals();
  69
  70    int num_vars = live_intervals->num_vars;
  71    BITSET_WORD *live = ralloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
  72    BITSET_WORD *flag_live = ralloc_array(NULL, BITSET_WORD, 1);
  73
  74    foreach_block(block, cfg) {
  75       memcpy(live, live_intervals->block_data[block->num].liveout,
  76              sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));
  77       memcpy(flag_live, live_intervals->block_data[block->num].flag_liveout,
  78              sizeof(BITSET_WORD));
  79
  80       foreach_inst_in_block_reverse(vec4_instruction, inst, block) {
  81          if ((inst->dst.file == GRF && !inst->has_side_effects()) ||
  82              (inst->dst.is_null() && inst->writes_flag())){
  83             bool result_live[4] = { false };
  84
  85             if (inst->dst.file == GRF) {
  86                for (unsigned i = 0; i < inst->regs_written; i++) {
  87                   for (int c = 0; c < 4; c++)
  88                      result_live[c] |= BITSET_TEST(
  89                         live, var_from_reg(alloc, offset(inst->dst, i), c));
  90                }
  91             } else {
  92                for (unsigned c = 0; c < 4; c++)
  93                   result_live[c] = BITSET_TEST(flag_live, c);
  94             }
  95
  96             /* If the instruction can't do writemasking, then it's all or
  97              * nothing.
  98              */
  99             if (!can_do_writemask(devinfo, inst)) {
 100                bool result = result_live[0] | result_live[1] |
 101                              result_live[2] | result_live[3];
 102                result_live[0] = result;
 103                result_live[1] = result;
 104                result_live[2] = result;
 105                result_live[3] = result;
 106             }
 107
 108             for (int c = 0; c < 4; c++) {
 109                if (!result_live[c] && inst->dst.writemask & (1 << c)) {
 110                   inst->dst.writemask &= ~(1 << c);
 111                   progress = true;
 112
 113                   if (inst->dst.writemask == 0) {
 114                      if (inst->writes_accumulator || inst->writes_flag()) {
 115                         inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
 116                      } else {
 117                         inst->opcode = BRW_OPCODE_NOP;
 118                         continue;
 119                      }
 120                   }
 121                }
 122             }
 123          }
 124
 125          if (inst->dst.is_null() && inst->writes_flag()) {
 126             bool combined_live = false;
 127             for (unsigned c = 0; c < 4; c++)
 128                combined_live |= BITSET_TEST(flag_live, c);
 129
 130             if (!combined_live) {
 131                inst->opcode = BRW_OPCODE_NOP;
 132                progress = true;
 133                continue;
 134             }
 135          }
 136
 137          if (inst->dst.file == GRF && !inst->predicate) {
 138             for (unsigned i = 0; i < inst->regs_written; i++) {
 139                for (int c = 0; c < 4; c++) {
 140                   if (inst->dst.writemask & (1 << c)) {
 141                      BITSET_CLEAR(live, var_from_reg(alloc,
 142                                                      offset(inst->dst, i), c));
 143                   }
 144                }
 145             }
 146          }
 147
 148          if (inst->writes_flag() && !inst->predicate) {
 149             for (unsigned c = 0; c < 4; c++)
 150                BITSET_CLEAR(flag_live, c);
 151          }
 152
 153          for (int i = 0; i < 3; i++) {
 154             if (inst->src[i].file == GRF) {
 155                for (unsigned j = 0; j < inst->regs_read(i); j++) {
 156                   for (int c = 0; c < 4; c++) {
 157                      BITSET_SET(live, var_from_reg(alloc,
 158                                                    offset(inst->src[i], j), c));
 159                   }
 160                }
 161             }
 162          }
 163
 164          for (unsigned c = 0; c < 4; c++) {
 165             if (inst->reads_flag(c)) {
 166                BITSET_SET(flag_live, c);
 167             }
 168          }
 169       }
 170    }
 171
 172    ralloc_free(live);
 173    ralloc_free(flag_live);
 174
 175    if (progress) {
 176       foreach_block_and_inst_safe(block, backend_instruction, inst, cfg) {
 177          if (inst->opcode == BRW_OPCODE_NOP) {
 178             inst->remove(block);
 179          }
 180       }
 181
 182       invalidate_live_intervals();
 183    }
 184
 185    return progress;
 186 }