1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "glsl/ir_print_visitor.h"
28 #include "main/macros.h"
36 vec4_visitor::setup_attributes(int payload_reg
)
39 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
42 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
43 if (prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
44 attribute_map
[i
] = payload_reg
+ nr_attributes
;
49 /* VertexID is stored by the VF as the last vertex element, but we
50 * don't represent it with a flag in inputs_read, so we call it
53 if (prog_data
->uses_vertexid
) {
54 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
58 foreach_list(node
, &this->instructions
) {
59 vec4_instruction
*inst
= (vec4_instruction
*)node
;
61 /* We have to support ATTR as a destination for GL_FIXED fixup. */
62 if (inst
->dst
.file
== ATTR
) {
63 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
65 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
66 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
68 inst
->dst
.file
= HW_REG
;
69 inst
->dst
.fixed_hw_reg
= reg
;
72 for (int i
= 0; i
< 3; i
++) {
73 if (inst
->src
[i
].file
!= ATTR
)
76 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
78 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
79 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
80 reg
.type
= inst
->src
[i
].type
;
83 if (inst
->src
[i
].negate
)
86 inst
->src
[i
].file
= HW_REG
;
87 inst
->src
[i
].fixed_hw_reg
= reg
;
91 /* The BSpec says we always have to read at least one thing from
92 * the VF, and it appears that the hardware wedges otherwise.
94 if (nr_attributes
== 0)
97 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
99 unsigned vue_entries
= MAX2(nr_attributes
, c
->prog_data
.vue_map
.num_slots
);
102 c
->prog_data
.urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
104 c
->prog_data
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
106 return payload_reg
+ nr_attributes
;
110 vec4_visitor::setup_uniforms(int reg
)
112 /* The pre-gen6 VS requires that some push constants get loaded no
113 * matter what, or the GPU would hang.
115 if (intel
->gen
< 6 && this->uniforms
== 0) {
116 this->uniform_vector_size
[this->uniforms
] = 1;
118 for (unsigned int i
= 0; i
< 4; i
++) {
119 unsigned int slot
= this->uniforms
* 4 + i
;
120 static float zero
= 0.0;
121 c
->prog_data
.param
[slot
] = &zero
;
127 reg
+= ALIGN(uniforms
, 2) / 2;
130 c
->prog_data
.nr_params
= this->uniforms
* 4;
132 c
->prog_data
.curb_read_length
= reg
- 1;
133 c
->prog_data
.uses_new_param_layout
= true;
139 vec4_visitor::setup_payload(void)
143 /* The payload always contains important data in g0, which contains
144 * the URB handles that are passed on to the URB write at the end
145 * of the thread. So, we always start push constants at g1.
149 reg
= setup_uniforms(reg
);
151 reg
= setup_attributes(reg
);
153 this->first_non_payload_grf
= reg
;
157 vec4_instruction::get_dst(void)
159 struct brw_reg brw_reg
;
163 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
164 brw_reg
= retype(brw_reg
, dst
.type
);
165 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
169 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
170 brw_reg
= retype(brw_reg
, dst
.type
);
171 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
175 brw_reg
= dst
.fixed_hw_reg
;
179 brw_reg
= brw_null_reg();
183 assert(!"not reached");
184 brw_reg
= brw_null_reg();
191 vec4_instruction::get_src(int i
)
193 struct brw_reg brw_reg
;
195 switch (src
[i
].file
) {
197 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
198 brw_reg
= retype(brw_reg
, src
[i
].type
);
199 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
201 brw_reg
= brw_abs(brw_reg
);
203 brw_reg
= negate(brw_reg
);
207 switch (src
[i
].type
) {
208 case BRW_REGISTER_TYPE_F
:
209 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
211 case BRW_REGISTER_TYPE_D
:
212 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
214 case BRW_REGISTER_TYPE_UD
:
215 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
218 assert(!"not reached");
219 brw_reg
= brw_null_reg();
225 brw_reg
= stride(brw_vec4_grf(1 + (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
226 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
228 brw_reg
= retype(brw_reg
, src
[i
].type
);
229 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
231 brw_reg
= brw_abs(brw_reg
);
233 brw_reg
= negate(brw_reg
);
235 /* This should have been moved to pull constants. */
236 assert(!src
[i
].reladdr
);
240 brw_reg
= src
[i
].fixed_hw_reg
;
244 /* Probably unused. */
245 brw_reg
= brw_null_reg();
249 assert(!"not reached");
250 brw_reg
= brw_null_reg();
258 vec4_visitor::generate_math1_gen4(vec4_instruction
*inst
,
264 brw_math_function(inst
->opcode
),
267 BRW_MATH_DATA_VECTOR
,
268 BRW_MATH_PRECISION_FULL
);
272 check_gen6_math_src_arg(struct brw_reg src
)
274 /* Source swizzles are ignored. */
277 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
281 vec4_visitor::generate_math1_gen6(vec4_instruction
*inst
,
285 /* Can't do writemask because math can't be align16. */
286 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
287 check_gen6_math_src_arg(src
);
289 brw_set_access_mode(p
, BRW_ALIGN_1
);
292 brw_math_function(inst
->opcode
),
295 BRW_MATH_DATA_SCALAR
,
296 BRW_MATH_PRECISION_FULL
);
297 brw_set_access_mode(p
, BRW_ALIGN_16
);
301 vec4_visitor::generate_math2_gen7(vec4_instruction
*inst
,
308 brw_math_function(inst
->opcode
),
313 vec4_visitor::generate_math2_gen6(vec4_instruction
*inst
,
318 /* Can't do writemask because math can't be align16. */
319 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
320 /* Source swizzles are ignored. */
321 check_gen6_math_src_arg(src0
);
322 check_gen6_math_src_arg(src1
);
324 brw_set_access_mode(p
, BRW_ALIGN_1
);
327 brw_math_function(inst
->opcode
),
329 brw_set_access_mode(p
, BRW_ALIGN_16
);
333 vec4_visitor::generate_math2_gen4(vec4_instruction
*inst
,
338 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
341 * "Operand0[7]. For the INT DIV functions, this operand is the
344 * "Operand1[7]. For the INT DIV functions, this operand is the
347 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
348 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
349 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
351 brw_push_insn_state(p
);
352 brw_set_saturate(p
, false);
353 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
354 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
355 brw_pop_insn_state(p
);
359 brw_math_function(inst
->opcode
),
362 BRW_MATH_DATA_VECTOR
,
363 BRW_MATH_PRECISION_FULL
);
367 vec4_visitor::generate_tex(vec4_instruction
*inst
,
373 if (intel
->gen
>= 5) {
374 switch (inst
->opcode
) {
375 case SHADER_OPCODE_TEX
:
376 case SHADER_OPCODE_TXL
:
377 if (inst
->shadow_compare
) {
378 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
380 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
383 case SHADER_OPCODE_TXD
:
384 /* There is no sample_d_c message; comparisons are done manually. */
385 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
387 case SHADER_OPCODE_TXF
:
388 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
390 case SHADER_OPCODE_TXS
:
391 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
394 assert(!"should not get here: invalid VS texture opcode");
398 switch (inst
->opcode
) {
399 case SHADER_OPCODE_TEX
:
400 case SHADER_OPCODE_TXL
:
401 if (inst
->shadow_compare
) {
402 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
403 assert(inst
->mlen
== 3);
405 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
406 assert(inst
->mlen
== 2);
409 case SHADER_OPCODE_TXD
:
410 /* There is no sample_d_c message; comparisons are done manually. */
411 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
412 assert(inst
->mlen
== 4);
414 case SHADER_OPCODE_TXF
:
415 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
416 assert(inst
->mlen
== 2);
418 case SHADER_OPCODE_TXS
:
419 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
420 assert(inst
->mlen
== 2);
423 assert(!"should not get here: invalid VS texture opcode");
428 assert(msg_type
!= -1);
430 /* Load the message header if present. If there's a texture offset, we need
431 * to set it up explicitly and load the offset bitfield. Otherwise, we can
432 * use an implied move from g0 to the first message register.
434 if (inst
->texture_offset
) {
435 /* Explicitly set up the message header by copying g0 to the MRF. */
436 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
437 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
439 /* Then set the offset bits in DWord 2. */
440 brw_set_access_mode(p
, BRW_ALIGN_1
);
442 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, inst
->base_mrf
, 2),
443 BRW_REGISTER_TYPE_UD
),
444 brw_imm_uw(inst
->texture_offset
));
445 brw_set_access_mode(p
, BRW_ALIGN_16
);
446 } else if (inst
->header_present
) {
447 /* Set up an implied move from g0 to the MRF. */
448 src
= brw_vec8_grf(0, 0);
451 uint32_t return_format
;
454 case BRW_REGISTER_TYPE_D
:
455 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
457 case BRW_REGISTER_TYPE_UD
:
458 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
461 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
469 SURF_INDEX_VS_TEXTURE(inst
->sampler
),
473 1, /* response length */
475 inst
->header_present
,
476 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
481 vec4_visitor::generate_urb_write(vec4_instruction
*inst
)
484 brw_null_reg(), /* dest */
485 inst
->base_mrf
, /* starting mrf reg nr */
486 brw_vec8_grf(0, 0), /* src */
487 false, /* allocate */
490 0, /* response len */
492 inst
->eot
, /* writes complete */
493 inst
->offset
, /* urb destination offset */
494 BRW_URB_SWIZZLE_INTERLEAVE
);
498 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1
,
499 struct brw_reg index
)
501 int second_vertex_offset
;
504 second_vertex_offset
= 1;
506 second_vertex_offset
= 16;
508 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
510 /* Set up M1 (message payload). Only the block offsets in M1.0 and
511 * M1.4 are used, and the rest are ignored.
513 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
514 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
515 struct brw_reg index_0
= suboffset(vec1(index
), 0);
516 struct brw_reg index_4
= suboffset(vec1(index
), 4);
518 brw_push_insn_state(p
);
519 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
520 brw_set_access_mode(p
, BRW_ALIGN_1
);
522 brw_MOV(p
, m1_0
, index_0
);
524 brw_set_predicate_inverse(p
, true);
525 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
526 index_4
.dw1
.ud
+= second_vertex_offset
;
527 brw_MOV(p
, m1_4
, index_4
);
529 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
532 brw_pop_insn_state(p
);
536 vec4_visitor::generate_scratch_read(vec4_instruction
*inst
,
538 struct brw_reg index
)
540 struct brw_reg header
= brw_vec8_grf(0, 0);
542 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
544 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
550 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
551 else if (intel
->gen
== 5 || intel
->is_g4x
)
552 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
554 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
556 /* Each of the 8 channel enables is considered for whether each
559 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
560 brw_set_dest(p
, send
, dst
);
561 brw_set_src0(p
, send
, header
);
563 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
564 brw_set_dp_read_message(p
, send
,
565 255, /* binding table index: stateless access */
566 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
568 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
574 vec4_visitor::generate_scratch_write(vec4_instruction
*inst
,
577 struct brw_reg index
)
579 struct brw_reg header
= brw_vec8_grf(0, 0);
582 /* If the instruction is predicated, we'll predicate the send, not
585 brw_set_predicate_control(p
, false);
587 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
589 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
593 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
594 retype(src
, BRW_REGISTER_TYPE_D
));
599 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
600 else if (intel
->gen
== 6)
601 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
603 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
605 brw_set_predicate_control(p
, inst
->predicate
);
607 /* Pre-gen6, we have to specify write commits to ensure ordering
608 * between reads and writes within a thread. Afterwards, that's
609 * guaranteed and write commits only matter for inter-thread
612 if (intel
->gen
>= 6) {
613 write_commit
= false;
615 /* The visitor set up our destination register to be g0. This
616 * means that when the next read comes along, we will end up
617 * reading from g0 and causing a block on the write commit. For
618 * write-after-read, we are relying on the value of the previous
619 * read being used (and thus blocking on completion) before our
620 * write is executed. This means we have to be careful in
621 * instruction scheduling to not violate this assumption.
626 /* Each of the 8 channel enables is considered for whether each
629 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
630 brw_set_dest(p
, send
, dst
);
631 brw_set_src0(p
, send
, header
);
633 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
634 brw_set_dp_write_message(p
, send
,
635 255, /* binding table index: stateless access */
636 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
639 true, /* header present */
640 false, /* not a render target write */
641 write_commit
, /* rlen */
647 vec4_visitor::generate_pull_constant_load(vec4_instruction
*inst
,
649 struct brw_reg index
,
650 struct brw_reg offset
)
652 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
653 index
.type
== BRW_REGISTER_TYPE_UD
);
654 uint32_t surf_index
= index
.dw1
.ud
;
656 if (intel
->gen
== 7) {
657 gen6_resolve_implied_move(p
, &offset
, inst
->base_mrf
);
658 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
659 brw_set_dest(p
, insn
, dst
);
660 brw_set_src0(p
, insn
, offset
);
661 brw_set_sampler_message(p
, insn
,
663 0, /* LD message ignores sampler unit */
664 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
667 false, /* no header */
668 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
673 struct brw_reg header
= brw_vec8_grf(0, 0);
675 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
677 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
683 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
684 else if (intel
->gen
== 5 || intel
->is_g4x
)
685 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
687 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
689 /* Each of the 8 channel enables is considered for whether each
692 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
693 brw_set_dest(p
, send
, dst
);
694 brw_set_src0(p
, send
, header
);
696 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
697 brw_set_dp_read_message(p
, send
,
699 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
701 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
707 vec4_visitor::generate_vs_instruction(vec4_instruction
*instruction
,
711 vec4_instruction
*inst
= (vec4_instruction
*)instruction
;
713 switch (inst
->opcode
) {
714 case SHADER_OPCODE_RCP
:
715 case SHADER_OPCODE_RSQ
:
716 case SHADER_OPCODE_SQRT
:
717 case SHADER_OPCODE_EXP2
:
718 case SHADER_OPCODE_LOG2
:
719 case SHADER_OPCODE_SIN
:
720 case SHADER_OPCODE_COS
:
721 if (intel
->gen
== 6) {
722 generate_math1_gen6(inst
, dst
, src
[0]);
724 /* Also works for Gen7. */
725 generate_math1_gen4(inst
, dst
, src
[0]);
729 case SHADER_OPCODE_POW
:
730 case SHADER_OPCODE_INT_QUOTIENT
:
731 case SHADER_OPCODE_INT_REMAINDER
:
732 if (intel
->gen
>= 7) {
733 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
734 } else if (intel
->gen
== 6) {
735 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
737 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
741 case SHADER_OPCODE_TEX
:
742 case SHADER_OPCODE_TXD
:
743 case SHADER_OPCODE_TXF
:
744 case SHADER_OPCODE_TXL
:
745 case SHADER_OPCODE_TXS
:
746 generate_tex(inst
, dst
, src
[0]);
749 case VS_OPCODE_URB_WRITE
:
750 generate_urb_write(inst
);
753 case VS_OPCODE_SCRATCH_READ
:
754 generate_scratch_read(inst
, dst
, src
[0]);
757 case VS_OPCODE_SCRATCH_WRITE
:
758 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
761 case VS_OPCODE_PULL_CONSTANT_LOAD
:
762 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
766 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
767 fail("unsupported opcode in `%s' in VS\n",
768 brw_opcodes
[inst
->opcode
].name
);
770 fail("Unsupported opcode %d in VS", inst
->opcode
);
778 if (c
->key
.userclip_active
&& !c
->key
.uses_clip_distance
)
779 setup_uniform_clipplane_values();
781 /* Generate VS IR for main(). (the visitor only descends into
782 * functions called "main").
784 visit_instructions(shader
->ir
);
788 /* Before any optimization, push array accesses out to scratch
789 * space where we need them to be. This pass may allocate new
790 * virtual GRFs, so we want to do it early. It also makes sure
791 * that we have reladdr computations available for CSE, since we'll
792 * often do repeated subexpressions for those.
794 move_grf_array_access_to_scratch();
795 move_uniform_array_access_to_pull_constants();
796 pack_uniform_registers();
797 move_push_constants_to_pull_constants();
802 progress
= dead_code_eliminate() || progress
;
803 progress
= opt_copy_propagation() || progress
;
804 progress
= opt_algebraic() || progress
;
805 progress
= opt_compute_to_mrf() || progress
;
818 brw_set_access_mode(p
, BRW_ALIGN_16
);
826 vec4_visitor::generate_code()
828 int last_native_inst
= 0;
829 const char *last_annotation_string
= NULL
;
830 ir_instruction
*last_annotation_ir
= NULL
;
832 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
833 printf("Native code for vertex shader %d:\n", prog
->Name
);
836 foreach_list(node
, &this->instructions
) {
837 vec4_instruction
*inst
= (vec4_instruction
*)node
;
838 struct brw_reg src
[3], dst
;
840 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
841 if (last_annotation_ir
!= inst
->ir
) {
842 last_annotation_ir
= inst
->ir
;
843 if (last_annotation_ir
) {
845 last_annotation_ir
->print();
849 if (last_annotation_string
!= inst
->annotation
) {
850 last_annotation_string
= inst
->annotation
;
851 if (last_annotation_string
)
852 printf(" %s\n", last_annotation_string
);
856 for (unsigned int i
= 0; i
< 3; i
++) {
857 src
[i
] = inst
->get_src(i
);
859 dst
= inst
->get_dst();
861 brw_set_conditionalmod(p
, inst
->conditional_mod
);
862 brw_set_predicate_control(p
, inst
->predicate
);
863 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
864 brw_set_saturate(p
, inst
->saturate
);
866 switch (inst
->opcode
) {
868 brw_MOV(p
, dst
, src
[0]);
871 brw_ADD(p
, dst
, src
[0], src
[1]);
874 brw_MUL(p
, dst
, src
[0], src
[1]);
876 case BRW_OPCODE_MACH
:
877 brw_set_acc_write_control(p
, 1);
878 brw_MACH(p
, dst
, src
[0], src
[1]);
879 brw_set_acc_write_control(p
, 0);
883 brw_FRC(p
, dst
, src
[0]);
885 case BRW_OPCODE_RNDD
:
886 brw_RNDD(p
, dst
, src
[0]);
888 case BRW_OPCODE_RNDE
:
889 brw_RNDE(p
, dst
, src
[0]);
891 case BRW_OPCODE_RNDZ
:
892 brw_RNDZ(p
, dst
, src
[0]);
896 brw_AND(p
, dst
, src
[0], src
[1]);
899 brw_OR(p
, dst
, src
[0], src
[1]);
902 brw_XOR(p
, dst
, src
[0], src
[1]);
905 brw_NOT(p
, dst
, src
[0]);
908 brw_ASR(p
, dst
, src
[0], src
[1]);
911 brw_SHR(p
, dst
, src
[0], src
[1]);
914 brw_SHL(p
, dst
, src
[0], src
[1]);
918 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
921 brw_SEL(p
, dst
, src
[0], src
[1]);
925 brw_DP4(p
, dst
, src
[0], src
[1]);
929 brw_DP3(p
, dst
, src
[0], src
[1]);
933 brw_DP2(p
, dst
, src
[0], src
[1]);
937 if (inst
->src
[0].file
!= BAD_FILE
) {
938 /* The instruction has an embedded compare (only allowed on gen6) */
939 assert(intel
->gen
== 6);
940 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
942 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
943 brw_inst
->header
.predicate_control
= inst
->predicate
;
947 case BRW_OPCODE_ELSE
:
950 case BRW_OPCODE_ENDIF
:
955 brw_DO(p
, BRW_EXECUTE_8
);
958 case BRW_OPCODE_BREAK
:
960 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
962 case BRW_OPCODE_CONTINUE
:
963 /* FINISHME: We need to write the loop instruction support still. */
968 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
971 case BRW_OPCODE_WHILE
:
976 generate_vs_instruction(inst
, dst
, src
);
980 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
981 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
983 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
984 ((uint32_t *)&p
->store
[i
])[3],
985 ((uint32_t *)&p
->store
[i
])[2],
986 ((uint32_t *)&p
->store
[i
])[1],
987 ((uint32_t *)&p
->store
[i
])[0]);
989 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
993 last_native_inst
= p
->nr_insn
;
996 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1002 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1003 * emit issues, it doesn't get the jump distances into the output,
1004 * which is often something we want to debug. So this is here in
1005 * case you're doing that.
1008 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1009 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1010 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
1011 ((uint32_t *)&p
->store
[i
])[3],
1012 ((uint32_t *)&p
->store
[i
])[2],
1013 ((uint32_t *)&p
->store
[i
])[1],
1014 ((uint32_t *)&p
->store
[i
])[0]);
1015 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1024 brw_vs_emit(struct gl_shader_program
*prog
, struct brw_vs_compile
*c
)
1026 struct brw_context
*brw
= c
->func
.brw
;
1027 struct intel_context
*intel
= &c
->func
.brw
->intel
;
1028 bool start_busy
= false;
1029 float start_time
= 0;
1034 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1035 start_busy
= (intel
->batch
.last_bo
&&
1036 drm_intel_bo_busy(intel
->batch
.last_bo
));
1037 start_time
= get_time();
1040 struct brw_shader
*shader
=
1041 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1045 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1046 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1047 _mesa_print_ir(shader
->ir
, NULL
);
1051 if (unlikely(INTEL_DEBUG
& DEBUG_PERF
)) {
1052 if (shader
->compiled_once
) {
1053 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1055 if (start_busy
&& !drm_intel_bo_busy(intel
->batch
.last_bo
)) {
1056 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1057 (get_time() - start_time
) * 1000);
1061 vec4_visitor
v(c
, prog
, shader
);
1063 prog
->LinkStatus
= false;
1064 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1068 shader
->compiled_once
= true;
1075 } /* namespace brw */