1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "glsl/ir_print_visitor.h"
35 vec4_visitor::setup_attributes(int payload_reg
)
38 int attribute_map
[VERT_ATTRIB_MAX
];
41 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
42 if (prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
43 attribute_map
[i
] = payload_reg
+ nr_attributes
;
48 foreach_list(node
, &this->instructions
) {
49 vec4_instruction
*inst
= (vec4_instruction
*)node
;
51 /* We have to support ATTR as a destination for GL_FIXED fixup. */
52 if (inst
->dst
.file
== ATTR
) {
53 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
55 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
56 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
58 inst
->dst
.file
= HW_REG
;
59 inst
->dst
.fixed_hw_reg
= reg
;
62 for (int i
= 0; i
< 3; i
++) {
63 if (inst
->src
[i
].file
!= ATTR
)
66 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
68 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
69 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
72 if (inst
->src
[i
].negate
)
75 inst
->src
[i
].file
= HW_REG
;
76 inst
->src
[i
].fixed_hw_reg
= reg
;
80 /* The BSpec says we always have to read at least one thing from
81 * the VF, and it appears that the hardware wedges otherwise.
83 if (nr_attributes
== 0)
86 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
88 return payload_reg
+ nr_attributes
;
92 vec4_visitor::setup_uniforms(int reg
)
94 /* User clip planes from curbe:
96 if (c
->key
.nr_userclip
) {
97 if (intel
->gen
>= 6) {
98 for (int i
= 0; i
< c
->key
.nr_userclip
; i
++) {
99 c
->userplane
[i
] = stride(brw_vec4_grf(reg
+ i
/ 2,
100 (i
% 2) * 4), 0, 4, 1);
102 reg
+= ALIGN(c
->key
.nr_userclip
, 2) / 2;
104 for (int i
= 0; i
< c
->key
.nr_userclip
; i
++) {
105 c
->userplane
[i
] = stride(brw_vec4_grf(reg
+ (6 + i
) / 2,
106 (i
% 2) * 4), 0, 4, 1);
108 reg
+= (ALIGN(6 + c
->key
.nr_userclip
, 4) / 4) * 2;
112 /* The pre-gen6 VS requires that some push constants get loaded no
113 * matter what, or the GPU would hang.
115 if (intel
->gen
< 6 && this->uniforms
== 0) {
116 this->uniform_vector_size
[this->uniforms
] = 1;
118 for (unsigned int i
= 0; i
< 4; i
++) {
119 unsigned int slot
= this->uniforms
* 4 + i
;
120 static float zero
= 0.0;
121 c
->prog_data
.param
[slot
] = &zero
;
127 reg
+= ALIGN(uniforms
, 2) / 2;
130 c
->prog_data
.nr_params
= this->uniforms
* 4;
132 c
->prog_data
.curb_read_length
= reg
- 1;
133 c
->prog_data
.uses_new_param_layout
= true;
139 vec4_visitor::setup_payload(void)
143 /* The payload always contains important data in g0, which contains
144 * the URB handles that are passed on to the URB write at the end
145 * of the thread. So, we always start push constants at g1.
149 reg
= setup_uniforms(reg
);
151 reg
= setup_attributes(reg
);
153 this->first_non_payload_grf
= reg
;
157 vec4_instruction::get_dst(void)
159 struct brw_reg brw_reg
;
163 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
164 brw_reg
= retype(brw_reg
, dst
.type
);
165 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
169 brw_reg
= dst
.fixed_hw_reg
;
173 brw_reg
= brw_null_reg();
177 assert(!"not reached");
178 brw_reg
= brw_null_reg();
185 vec4_instruction::get_src(int i
)
187 struct brw_reg brw_reg
;
189 switch (src
[i
].file
) {
191 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
192 brw_reg
= retype(brw_reg
, src
[i
].type
);
193 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
195 brw_reg
= brw_abs(brw_reg
);
197 brw_reg
= negate(brw_reg
);
201 switch (src
[i
].type
) {
202 case BRW_REGISTER_TYPE_F
:
203 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
205 case BRW_REGISTER_TYPE_D
:
206 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
208 case BRW_REGISTER_TYPE_UD
:
209 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
212 assert(!"not reached");
213 brw_reg
= brw_null_reg();
219 brw_reg
= stride(brw_vec4_grf(1 + (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
220 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
222 brw_reg
= retype(brw_reg
, src
[i
].type
);
223 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
225 brw_reg
= brw_abs(brw_reg
);
227 brw_reg
= negate(brw_reg
);
229 /* This should have been moved to pull constants. */
230 assert(!src
[i
].reladdr
);
234 brw_reg
= src
[i
].fixed_hw_reg
;
238 /* Probably unused. */
239 brw_reg
= brw_null_reg();
243 assert(!"not reached");
244 brw_reg
= brw_null_reg();
252 vec4_visitor::generate_math1_gen4(vec4_instruction
*inst
,
258 brw_math_function(inst
->opcode
),
259 BRW_MATH_SATURATE_NONE
,
262 BRW_MATH_DATA_SCALAR
,
263 BRW_MATH_PRECISION_FULL
);
267 check_gen6_math_src_arg(struct brw_reg src
)
269 /* Source swizzles are ignored. */
272 assert(src
.dw1
.bits
.swizzle
= BRW_SWIZZLE_XYZW
);
276 vec4_visitor::generate_math1_gen6(vec4_instruction
*inst
,
280 /* Can't do writemask because math can't be align16. */
281 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
282 check_gen6_math_src_arg(src
);
284 brw_set_access_mode(p
, BRW_ALIGN_1
);
287 brw_math_function(inst
->opcode
),
288 BRW_MATH_SATURATE_NONE
,
291 BRW_MATH_DATA_SCALAR
,
292 BRW_MATH_PRECISION_FULL
);
293 brw_set_access_mode(p
, BRW_ALIGN_16
);
297 vec4_visitor::generate_math2_gen6(vec4_instruction
*inst
,
302 /* Can't do writemask because math can't be align16. */
303 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
304 /* Source swizzles are ignored. */
305 check_gen6_math_src_arg(src0
);
306 check_gen6_math_src_arg(src1
);
308 brw_set_access_mode(p
, BRW_ALIGN_1
);
311 brw_math_function(inst
->opcode
),
313 brw_set_access_mode(p
, BRW_ALIGN_16
);
317 vec4_visitor::generate_math2_gen4(vec4_instruction
*inst
,
322 /* Can't do writemask because math can't be align16. */
323 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
325 brw_MOV(p
, brw_message_reg(inst
->base_mrf
+ 1), src1
);
327 brw_set_access_mode(p
, BRW_ALIGN_1
);
330 brw_math_function(inst
->opcode
),
331 BRW_MATH_SATURATE_NONE
,
334 BRW_MATH_DATA_VECTOR
,
335 BRW_MATH_PRECISION_FULL
);
336 brw_set_access_mode(p
, BRW_ALIGN_16
);
340 vec4_visitor::generate_urb_write(vec4_instruction
*inst
)
343 brw_null_reg(), /* dest */
344 inst
->base_mrf
, /* starting mrf reg nr */
345 brw_vec8_grf(0, 0), /* src */
346 false, /* allocate */
349 0, /* response len */
351 inst
->eot
, /* writes complete */
352 inst
->offset
, /* urb destination offset */
353 BRW_URB_SWIZZLE_INTERLEAVE
);
357 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1
,
358 struct brw_reg index
)
360 int second_vertex_offset
;
363 second_vertex_offset
= 1;
365 second_vertex_offset
= 16;
367 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
369 /* Set up M1 (message payload). Only the block offsets in M1.0 and
370 * M1.4 are used, and the rest are ignored.
372 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
373 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
374 struct brw_reg index_0
= suboffset(vec1(index
), 0);
375 struct brw_reg index_4
= suboffset(vec1(index
), 4);
377 brw_push_insn_state(p
);
378 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
379 brw_set_access_mode(p
, BRW_ALIGN_1
);
381 brw_MOV(p
, m1_0
, index_0
);
383 brw_set_predicate_inverse(p
, true);
384 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
386 brw_MOV(p
, m1_4
, index_4
);
388 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
391 brw_pop_insn_state(p
);
395 vec4_visitor::generate_scratch_read(vec4_instruction
*inst
,
397 struct brw_reg index
)
399 if (intel
->gen
>= 6) {
400 brw_push_insn_state(p
);
401 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
403 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_D
),
404 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D
));
405 brw_pop_insn_state(p
);
408 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
414 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
415 else if (intel
->gen
== 5 || intel
->is_g4x
)
416 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
418 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
420 /* Each of the 8 channel enables is considered for whether each
423 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
424 brw_set_dest(p
, send
, dst
);
425 brw_set_src0(p
, send
, brw_message_reg(inst
->base_mrf
));
426 brw_set_dp_read_message(p
, send
,
427 255, /* binding table index: stateless access */
428 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
430 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
436 vec4_visitor::generate_scratch_write(vec4_instruction
*inst
,
439 struct brw_reg index
)
441 /* If the instruction is predicated, we'll predicate the send, not
444 brw_set_predicate_control(p
, false);
446 if (intel
->gen
>= 6) {
447 brw_push_insn_state(p
);
448 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
450 retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_D
),
451 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D
));
452 brw_pop_insn_state(p
);
455 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
459 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
460 retype(src
, BRW_REGISTER_TYPE_D
));
465 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
467 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
469 brw_set_predicate_control(p
, inst
->predicate
);
471 /* Each of the 8 channel enables is considered for whether each
474 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
475 brw_set_dest(p
, send
, dst
);
476 brw_set_src0(p
, send
, brw_message_reg(inst
->base_mrf
));
477 brw_set_dp_write_message(p
, send
,
478 255, /* binding table index: stateless access */
479 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
482 true, /* header present */
483 false, /* pixel scoreboard */
490 vec4_visitor::generate_pull_constant_load(vec4_instruction
*inst
,
492 struct brw_reg index
)
494 struct brw_reg header
= brw_vec8_grf(0, 0);
496 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
498 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
504 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
505 else if (intel
->gen
== 5 || intel
->is_g4x
)
506 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
508 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
510 /* Each of the 8 channel enables is considered for whether each
513 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
514 brw_set_dest(p
, send
, dst
);
515 brw_set_src0(p
, send
, header
);
516 brw_set_dp_read_message(p
, send
,
517 SURF_INDEX_VERT_CONST_BUFFER
,
518 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
520 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
526 vec4_visitor::generate_vs_instruction(vec4_instruction
*instruction
,
530 vec4_instruction
*inst
= (vec4_instruction
*)instruction
;
532 switch (inst
->opcode
) {
533 case SHADER_OPCODE_RCP
:
534 case SHADER_OPCODE_RSQ
:
535 case SHADER_OPCODE_SQRT
:
536 case SHADER_OPCODE_EXP2
:
537 case SHADER_OPCODE_LOG2
:
538 case SHADER_OPCODE_SIN
:
539 case SHADER_OPCODE_COS
:
540 if (intel
->gen
>= 6) {
541 generate_math1_gen6(inst
, dst
, src
[0]);
543 generate_math1_gen4(inst
, dst
, src
[0]);
547 case SHADER_OPCODE_POW
:
548 if (intel
->gen
>= 6) {
549 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
551 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
555 case VS_OPCODE_URB_WRITE
:
556 generate_urb_write(inst
);
559 case VS_OPCODE_SCRATCH_READ
:
560 generate_scratch_read(inst
, dst
, src
[0]);
563 case VS_OPCODE_SCRATCH_WRITE
:
564 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
567 case VS_OPCODE_PULL_CONSTANT_LOAD
:
568 generate_pull_constant_load(inst
, dst
, src
[0]);
572 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
573 fail("unsupported opcode in `%s' in VS\n",
574 brw_opcodes
[inst
->opcode
].name
);
576 fail("Unsupported opcode %d in VS", inst
->opcode
);
584 /* Generate VS IR for main(). (the visitor only descends into
585 * functions called "main").
587 visit_instructions(shader
->ir
);
591 /* Before any optimization, push array accesses out to scratch
592 * space where we need them to be. This pass may allocate new
593 * virtual GRFs, so we want to do it early. It also makes sure
594 * that we have reladdr computations available for CSE, since we'll
595 * often do repeated subexpressions for those.
597 move_grf_array_access_to_scratch();
598 move_uniform_array_access_to_pull_constants();
603 progress
= dead_code_eliminate() || progress
;
606 pack_uniform_registers();
617 brw_set_access_mode(p
, BRW_ALIGN_16
);
625 vec4_visitor::generate_code()
627 int last_native_inst
= 0;
628 const char *last_annotation_string
= NULL
;
629 ir_instruction
*last_annotation_ir
= NULL
;
631 int loop_stack_array_size
= 16;
632 int loop_stack_depth
= 0;
633 brw_instruction
**loop_stack
=
634 rzalloc_array(this->mem_ctx
, brw_instruction
*, loop_stack_array_size
);
635 int *if_depth_in_loop
=
636 rzalloc_array(this->mem_ctx
, int, loop_stack_array_size
);
639 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
640 printf("Native code for vertex shader %d:\n", prog
->Name
);
643 foreach_list(node
, &this->instructions
) {
644 vec4_instruction
*inst
= (vec4_instruction
*)node
;
645 struct brw_reg src
[3], dst
;
647 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
648 if (last_annotation_ir
!= inst
->ir
) {
649 last_annotation_ir
= inst
->ir
;
650 if (last_annotation_ir
) {
652 last_annotation_ir
->print();
656 if (last_annotation_string
!= inst
->annotation
) {
657 last_annotation_string
= inst
->annotation
;
658 if (last_annotation_string
)
659 printf(" %s\n", last_annotation_string
);
663 for (unsigned int i
= 0; i
< 3; i
++) {
664 src
[i
] = inst
->get_src(i
);
666 dst
= inst
->get_dst();
668 brw_set_conditionalmod(p
, inst
->conditional_mod
);
669 brw_set_predicate_control(p
, inst
->predicate
);
670 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
671 brw_set_saturate(p
, inst
->saturate
);
673 switch (inst
->opcode
) {
675 brw_MOV(p
, dst
, src
[0]);
678 brw_ADD(p
, dst
, src
[0], src
[1]);
681 brw_MUL(p
, dst
, src
[0], src
[1]);
683 case BRW_OPCODE_MACH
:
684 brw_set_acc_write_control(p
, 1);
685 brw_MACH(p
, dst
, src
[0], src
[1]);
686 brw_set_acc_write_control(p
, 0);
690 brw_FRC(p
, dst
, src
[0]);
692 case BRW_OPCODE_RNDD
:
693 brw_RNDD(p
, dst
, src
[0]);
695 case BRW_OPCODE_RNDE
:
696 brw_RNDE(p
, dst
, src
[0]);
698 case BRW_OPCODE_RNDZ
:
699 brw_RNDZ(p
, dst
, src
[0]);
703 brw_AND(p
, dst
, src
[0], src
[1]);
706 brw_OR(p
, dst
, src
[0], src
[1]);
709 brw_XOR(p
, dst
, src
[0], src
[1]);
712 brw_NOT(p
, dst
, src
[0]);
715 brw_ASR(p
, dst
, src
[0], src
[1]);
718 brw_SHR(p
, dst
, src
[0], src
[1]);
721 brw_SHL(p
, dst
, src
[0], src
[1]);
725 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
728 brw_SEL(p
, dst
, src
[0], src
[1]);
732 brw_DP4(p
, dst
, src
[0], src
[1]);
736 brw_DP3(p
, dst
, src
[0], src
[1]);
740 brw_DP2(p
, dst
, src
[0], src
[1]);
744 if (inst
->src
[0].file
!= BAD_FILE
) {
745 /* The instruction has an embedded compare (only allowed on gen6) */
746 assert(intel
->gen
== 6);
747 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
749 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
750 brw_inst
->header
.predicate_control
= inst
->predicate
;
752 if_depth_in_loop
[loop_stack_depth
]++;
755 case BRW_OPCODE_ELSE
:
758 case BRW_OPCODE_ENDIF
:
760 if_depth_in_loop
[loop_stack_depth
]--;
764 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
765 if (loop_stack_array_size
<= loop_stack_depth
) {
766 loop_stack_array_size
*= 2;
767 loop_stack
= reralloc(this->mem_ctx
, loop_stack
, brw_instruction
*,
768 loop_stack_array_size
);
769 if_depth_in_loop
= reralloc(this->mem_ctx
, if_depth_in_loop
, int,
770 loop_stack_array_size
);
772 if_depth_in_loop
[loop_stack_depth
] = 0;
775 case BRW_OPCODE_BREAK
:
776 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
777 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
779 case BRW_OPCODE_CONTINUE
:
780 /* FINISHME: We need to write the loop instruction support still. */
782 gen6_CONT(p
, loop_stack
[loop_stack_depth
- 1]);
784 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
785 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
788 case BRW_OPCODE_WHILE
: {
789 struct brw_instruction
*inst0
, *inst1
;
795 assert(loop_stack_depth
> 0);
797 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
798 if (intel
->gen
< 6) {
799 /* patch all the BREAK/CONT instructions from last BGNLOOP */
800 while (inst0
> loop_stack
[loop_stack_depth
]) {
802 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
803 inst0
->bits3
.if_else
.jump_count
== 0) {
804 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
806 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
807 inst0
->bits3
.if_else
.jump_count
== 0) {
808 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
816 generate_vs_instruction(inst
, dst
, src
);
820 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
821 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
823 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
824 ((uint32_t *)&p
->store
[i
])[3],
825 ((uint32_t *)&p
->store
[i
])[2],
826 ((uint32_t *)&p
->store
[i
])[1],
827 ((uint32_t *)&p
->store
[i
])[0]);
829 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
833 last_native_inst
= p
->nr_insn
;
836 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
840 ralloc_free(loop_stack
);
841 ralloc_free(if_depth_in_loop
);
845 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
846 * emit issues, it doesn't get the jump distances into the output,
847 * which is often something we want to debug. So this is here in
848 * case you're doing that.
851 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
852 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
853 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
854 ((uint32_t *)&p
->store
[i
])[3],
855 ((uint32_t *)&p
->store
[i
])[2],
856 ((uint32_t *)&p
->store
[i
])[1],
857 ((uint32_t *)&p
->store
[i
])[0]);
858 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
867 brw_vs_emit(struct gl_shader_program
*prog
, struct brw_vs_compile
*c
)
872 struct brw_shader
*shader
=
873 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
877 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
878 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
879 _mesa_print_ir(shader
->ir
, NULL
);
883 vec4_visitor
v(c
, prog
, shader
);
885 prog
->LinkStatus
= GL_FALSE
;
886 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
895 } /* namespace brw */