projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965/gs: Add a case to brwNewProgram() for geometry shaders.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
104 (src[i].reg + src[i].reg_offset) / 2,
105 ((src[i].reg + src[i].reg_offset) % 2) * 4),
106 0, 4, 1);
107 brw_reg = retype(brw_reg, src[i].type);
108 brw_reg.dw1.bits.swizzle = src[i].swizzle;
109 if (src[i].abs)
110 brw_reg = brw_abs(brw_reg);
111 if (src[i].negate)
112 brw_reg = negate(brw_reg);
113
114 /* This should have been moved to pull constants. */
115 assert(!src[i].reladdr);
116 break;
117
118 case HW_REG:
119 brw_reg = src[i].fixed_hw_reg;
120 break;
121
122 case BAD_FILE:
123 /* Probably unused. */
124 brw_reg = brw_null_reg();
125 break;
126 case ATTR:
127 default:
128 assert(!"not reached");
129 brw_reg = brw_null_reg();
130 break;
131 }
132
133 return brw_reg;
134 }
135
136 vec4_generator::vec4_generator(struct brw_context *brw,
137 struct gl_shader_program *shader_prog,
138 struct gl_program *prog,
139 struct brw_vec4_prog_data *prog_data,
140 void *mem_ctx,
141 bool debug_flag)
142 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
143 mem_ctx(mem_ctx), debug_flag(debug_flag)
144 {
145 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
146
147 p = rzalloc(mem_ctx, struct brw_compile);
148 brw_init_compile(brw, p, mem_ctx);
149 }
150
151 vec4_generator::~vec4_generator()
152 {
153 }
154
155 void
156 vec4_generator::mark_surface_used(unsigned surf_index)
157 {
158 assert(surf_index < BRW_MAX_VS_SURFACES);
159
160 prog_data->binding_table_size = MAX2(prog_data->binding_table_size,
161 surf_index + 1);
162 }
163
164 void
165 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
166 struct brw_reg dst,
167 struct brw_reg src)
168 {
169 brw_math(p,
170 dst,
171 brw_math_function(inst->opcode),
172 inst->base_mrf,
173 src,
174 BRW_MATH_DATA_VECTOR,
175 BRW_MATH_PRECISION_FULL);
176 }
177
178 static void
179 check_gen6_math_src_arg(struct brw_reg src)
180 {
181 /* Source swizzles are ignored. */
182 assert(!src.abs);
183 assert(!src.negate);
184 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
185 }
186
187 void
188 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
189 struct brw_reg dst,
190 struct brw_reg src)
191 {
192 /* Can't do writemask because math can't be align16. */
193 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
194 check_gen6_math_src_arg(src);
195
196 brw_set_access_mode(p, BRW_ALIGN_1);
197 brw_math(p,
198 dst,
199 brw_math_function(inst->opcode),
200 inst->base_mrf,
201 src,
202 BRW_MATH_DATA_SCALAR,
203 BRW_MATH_PRECISION_FULL);
204 brw_set_access_mode(p, BRW_ALIGN_16);
205 }
206
207 void
208 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
209 struct brw_reg dst,
210 struct brw_reg src0,
211 struct brw_reg src1)
212 {
213 brw_math2(p,
214 dst,
215 brw_math_function(inst->opcode),
216 src0, src1);
217 }
218
219 void
220 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
221 struct brw_reg dst,
222 struct brw_reg src0,
223 struct brw_reg src1)
224 {
225 /* Can't do writemask because math can't be align16. */
226 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
227 /* Source swizzles are ignored. */
228 check_gen6_math_src_arg(src0);
229 check_gen6_math_src_arg(src1);
230
231 brw_set_access_mode(p, BRW_ALIGN_1);
232 brw_math2(p,
233 dst,
234 brw_math_function(inst->opcode),
235 src0, src1);
236 brw_set_access_mode(p, BRW_ALIGN_16);
237 }
238
239 void
240 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
241 struct brw_reg dst,
242 struct brw_reg src0,
243 struct brw_reg src1)
244 {
245 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
246 * "Message Payload":
247 *
248 * "Operand0[7]. For the INT DIV functions, this operand is the
249 * denominator."
250 * ...
251 * "Operand1[7]. For the INT DIV functions, this operand is the
252 * numerator."
253 */
254 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
255 struct brw_reg &op0 = is_int_div ? src1 : src0;
256 struct brw_reg &op1 = is_int_div ? src0 : src1;
257
258 brw_push_insn_state(p);
259 brw_set_saturate(p, false);
260 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
262 brw_pop_insn_state(p);
263
264 brw_math(p,
265 dst,
266 brw_math_function(inst->opcode),
267 inst->base_mrf,
268 op0,
269 BRW_MATH_DATA_VECTOR,
270 BRW_MATH_PRECISION_FULL);
271 }
272
273 void
274 vec4_generator::generate_tex(vec4_instruction *inst,
275 struct brw_reg dst,
276 struct brw_reg src)
277 {
278 int msg_type = -1;
279
280 if (brw->gen >= 5) {
281 switch (inst->opcode) {
282 case SHADER_OPCODE_TEX:
283 case SHADER_OPCODE_TXL:
284 if (inst->shadow_compare) {
285 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
286 } else {
287 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
288 }
289 break;
290 case SHADER_OPCODE_TXD:
291 if (inst->shadow_compare) {
292 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
293 assert(brw->is_haswell);
294 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
295 } else {
296 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
297 }
298 break;
299 case SHADER_OPCODE_TXF:
300 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
301 break;
302 case SHADER_OPCODE_TXF_MS:
303 if (brw->gen >= 7)
304 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
305 else
306 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
307 break;
308 case SHADER_OPCODE_TXS:
309 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
310 break;
311 default:
312 assert(!"should not get here: invalid VS texture opcode");
313 break;
314 }
315 } else {
316 switch (inst->opcode) {
317 case SHADER_OPCODE_TEX:
318 case SHADER_OPCODE_TXL:
319 if (inst->shadow_compare) {
320 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
321 assert(inst->mlen == 3);
322 } else {
323 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
324 assert(inst->mlen == 2);
325 }
326 break;
327 case SHADER_OPCODE_TXD:
328 /* There is no sample_d_c message; comparisons are done manually. */
329 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
330 assert(inst->mlen == 4);
331 break;
332 case SHADER_OPCODE_TXF:
333 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
334 assert(inst->mlen == 2);
335 break;
336 case SHADER_OPCODE_TXS:
337 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
338 assert(inst->mlen == 2);
339 break;
340 default:
341 assert(!"should not get here: invalid VS texture opcode");
342 break;
343 }
344 }
345
346 assert(msg_type != -1);
347
348 /* Load the message header if present. If there's a texture offset, we need
349 * to set it up explicitly and load the offset bitfield. Otherwise, we can
350 * use an implied move from g0 to the first message register.
351 */
352 if (inst->texture_offset) {
353 /* Explicitly set up the message header by copying g0 to the MRF. */
354 brw_push_insn_state(p);
355 brw_set_mask_control(p, BRW_MASK_DISABLE);
356 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
357 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
358
359 /* Then set the offset bits in DWord 2. */
360 brw_set_access_mode(p, BRW_ALIGN_1);
361 brw_MOV(p,
362 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
363 BRW_REGISTER_TYPE_UD),
364 brw_imm_uw(inst->texture_offset));
365 brw_pop_insn_state(p);
366 } else if (inst->header_present) {
367 /* Set up an implied move from g0 to the MRF. */
368 src = brw_vec8_grf(0, 0);
369 }
370
371 uint32_t return_format;
372
373 switch (dst.type) {
374 case BRW_REGISTER_TYPE_D:
375 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
376 break;
377 case BRW_REGISTER_TYPE_UD:
378 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
379 break;
380 default:
381 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
382 break;
383 }
384
385 brw_SAMPLE(p,
386 dst,
387 inst->base_mrf,
388 src,
389 SURF_INDEX_VS_TEXTURE(inst->sampler),
390 inst->sampler,
391 msg_type,
392 1, /* response length */
393 inst->mlen,
394 inst->header_present,
395 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
396 return_format);
397
398 mark_surface_used(SURF_INDEX_VS_TEXTURE(inst->sampler));
399 }
400
401 void
402 vec4_generator::generate_urb_write(vec4_instruction *inst)
403 {
404 brw_urb_WRITE(p,
405 brw_null_reg(), /* dest */
406 inst->base_mrf, /* starting mrf reg nr */
407 brw_vec8_grf(0, 0), /* src */
408 false, /* allocate */
409 true, /* used */
410 inst->mlen,
411 0, /* response len */
412 inst->eot, /* eot */
413 inst->eot, /* writes complete */
414 inst->offset, /* urb destination offset */
415 BRW_URB_SWIZZLE_INTERLEAVE);
416 }
417
418 void
419 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
420 struct brw_reg index)
421 {
422 int second_vertex_offset;
423
424 if (brw->gen >= 6)
425 second_vertex_offset = 1;
426 else
427 second_vertex_offset = 16;
428
429 m1 = retype(m1, BRW_REGISTER_TYPE_D);
430
431 /* Set up M1 (message payload). Only the block offsets in M1.0 and
432 * M1.4 are used, and the rest are ignored.
433 */
434 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
435 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
436 struct brw_reg index_0 = suboffset(vec1(index), 0);
437 struct brw_reg index_4 = suboffset(vec1(index), 4);
438
439 brw_push_insn_state(p);
440 brw_set_mask_control(p, BRW_MASK_DISABLE);
441 brw_set_access_mode(p, BRW_ALIGN_1);
442
443 brw_MOV(p, m1_0, index_0);
444
445 if (index.file == BRW_IMMEDIATE_VALUE) {
446 index_4.dw1.ud += second_vertex_offset;
447 brw_MOV(p, m1_4, index_4);
448 } else {
449 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
450 }
451
452 brw_pop_insn_state(p);
453 }
454
455 void
456 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
457 struct brw_reg dst)
458 {
459 brw_push_insn_state(p);
460 brw_set_mask_control(p, BRW_MASK_DISABLE);
461 brw_set_access_mode(p, BRW_ALIGN_1);
462
463 struct brw_reg flags = brw_flag_reg(0, 0);
464 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
465 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
466
467 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
468 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
469 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
470
471 brw_pop_insn_state(p);
472 }
473
474 void
475 vec4_generator::generate_scratch_read(vec4_instruction *inst,
476 struct brw_reg dst,
477 struct brw_reg index)
478 {
479 struct brw_reg header = brw_vec8_grf(0, 0);
480
481 gen6_resolve_implied_move(p, &header, inst->base_mrf);
482
483 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
484 index);
485
486 uint32_t msg_type;
487
488 if (brw->gen >= 6)
489 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
490 else if (brw->gen == 5 || brw->is_g4x)
491 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
492 else
493 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
494
495 /* Each of the 8 channel enables is considered for whether each
496 * dword is written.
497 */
498 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
499 brw_set_dest(p, send, dst);
500 brw_set_src0(p, send, header);
501 if (brw->gen < 6)
502 send->header.destreg__conditionalmod = inst->base_mrf;
503 brw_set_dp_read_message(p, send,
504 255, /* binding table index: stateless access */
505 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
506 msg_type,
507 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
508 2, /* mlen */
509 true, /* header_present */
510 1 /* rlen */);
511 }
512
513 void
514 vec4_generator::generate_scratch_write(vec4_instruction *inst,
515 struct brw_reg dst,
516 struct brw_reg src,
517 struct brw_reg index)
518 {
519 struct brw_reg header = brw_vec8_grf(0, 0);
520 bool write_commit;
521
522 /* If the instruction is predicated, we'll predicate the send, not
523 * the header setup.
524 */
525 brw_set_predicate_control(p, false);
526
527 gen6_resolve_implied_move(p, &header, inst->base_mrf);
528
529 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
530 index);
531
532 brw_MOV(p,
533 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
534 retype(src, BRW_REGISTER_TYPE_D));
535
536 uint32_t msg_type;
537
538 if (brw->gen >= 7)
539 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
540 else if (brw->gen == 6)
541 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
542 else
543 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
544
545 brw_set_predicate_control(p, inst->predicate);
546
547 /* Pre-gen6, we have to specify write commits to ensure ordering
548 * between reads and writes within a thread. Afterwards, that's
549 * guaranteed and write commits only matter for inter-thread
550 * synchronization.
551 */
552 if (brw->gen >= 6) {
553 write_commit = false;
554 } else {
555 /* The visitor set up our destination register to be g0. This
556 * means that when the next read comes along, we will end up
557 * reading from g0 and causing a block on the write commit. For
558 * write-after-read, we are relying on the value of the previous
559 * read being used (and thus blocking on completion) before our
560 * write is executed. This means we have to be careful in
561 * instruction scheduling to not violate this assumption.
562 */
563 write_commit = true;
564 }
565
566 /* Each of the 8 channel enables is considered for whether each
567 * dword is written.
568 */
569 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
570 brw_set_dest(p, send, dst);
571 brw_set_src0(p, send, header);
572 if (brw->gen < 6)
573 send->header.destreg__conditionalmod = inst->base_mrf;
574 brw_set_dp_write_message(p, send,
575 255, /* binding table index: stateless access */
576 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
577 msg_type,
578 3, /* mlen */
579 true, /* header present */
580 false, /* not a render target write */
581 write_commit, /* rlen */
582 false, /* eot */
583 write_commit);
584 }
585
586 void
587 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
588 struct brw_reg dst,
589 struct brw_reg index,
590 struct brw_reg offset)
591 {
592 assert(brw->gen <= 7);
593 assert(index.file == BRW_IMMEDIATE_VALUE &&
594 index.type == BRW_REGISTER_TYPE_UD);
595 uint32_t surf_index = index.dw1.ud;
596
597 struct brw_reg header = brw_vec8_grf(0, 0);
598
599 gen6_resolve_implied_move(p, &header, inst->base_mrf);
600
601 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
602 offset);
603
604 uint32_t msg_type;
605
606 if (brw->gen >= 6)
607 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
608 else if (brw->gen == 5 || brw->is_g4x)
609 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
610 else
611 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
612
613 /* Each of the 8 channel enables is considered for whether each
614 * dword is written.
615 */
616 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
617 brw_set_dest(p, send, dst);
618 brw_set_src0(p, send, header);
619 if (brw->gen < 6)
620 send->header.destreg__conditionalmod = inst->base_mrf;
621 brw_set_dp_read_message(p, send,
622 surf_index,
623 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
624 msg_type,
625 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
626 2, /* mlen */
627 true, /* header_present */
628 1 /* rlen */);
629
630 mark_surface_used(surf_index);
631 }
632
633 void
634 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
635 struct brw_reg dst,
636 struct brw_reg surf_index,
637 struct brw_reg offset)
638 {
639 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
640 surf_index.type == BRW_REGISTER_TYPE_UD);
641
642 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
643 brw_set_dest(p, insn, dst);
644 brw_set_src0(p, insn, offset);
645 brw_set_sampler_message(p, insn,
646 surf_index.dw1.ud,
647 0, /* LD message ignores sampler unit */
648 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
649 1, /* rlen */
650 1, /* mlen */
651 false, /* no header */
652 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
653 0);
654
655 mark_surface_used(surf_index.dw1.ud);
656 }
657
658 /**
659 * Generate assembly for a Vec4 IR instruction.
660 *
661 * \param instruction The Vec4 IR instruction to generate code for.
662 * \param dst The destination register.
663 * \param src An array of up to three source registers.
664 */
665 void
666 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
667 struct brw_reg dst,
668 struct brw_reg *src)
669 {
670 vec4_instruction *inst = (vec4_instruction *) instruction;
671
672 switch (inst->opcode) {
673 case BRW_OPCODE_MOV:
674 brw_MOV(p, dst, src[0]);
675 break;
676 case BRW_OPCODE_ADD:
677 brw_ADD(p, dst, src[0], src[1]);
678 break;
679 case BRW_OPCODE_MUL:
680 brw_MUL(p, dst, src[0], src[1]);
681 break;
682 case BRW_OPCODE_MACH:
683 brw_set_acc_write_control(p, 1);
684 brw_MACH(p, dst, src[0], src[1]);
685 brw_set_acc_write_control(p, 0);
686 break;
687
688 case BRW_OPCODE_MAD:
689 brw_MAD(p, dst, src[0], src[1], src[2]);
690 break;
691
692 case BRW_OPCODE_FRC:
693 brw_FRC(p, dst, src[0]);
694 break;
695 case BRW_OPCODE_RNDD:
696 brw_RNDD(p, dst, src[0]);
697 break;
698 case BRW_OPCODE_RNDE:
699 brw_RNDE(p, dst, src[0]);
700 break;
701 case BRW_OPCODE_RNDZ:
702 brw_RNDZ(p, dst, src[0]);
703 break;
704
705 case BRW_OPCODE_AND:
706 brw_AND(p, dst, src[0], src[1]);
707 break;
708 case BRW_OPCODE_OR:
709 brw_OR(p, dst, src[0], src[1]);
710 break;
711 case BRW_OPCODE_XOR:
712 brw_XOR(p, dst, src[0], src[1]);
713 break;
714 case BRW_OPCODE_NOT:
715 brw_NOT(p, dst, src[0]);
716 break;
717 case BRW_OPCODE_ASR:
718 brw_ASR(p, dst, src[0], src[1]);
719 break;
720 case BRW_OPCODE_SHR:
721 brw_SHR(p, dst, src[0], src[1]);
722 break;
723 case BRW_OPCODE_SHL:
724 brw_SHL(p, dst, src[0], src[1]);
725 break;
726
727 case BRW_OPCODE_CMP:
728 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
729 break;
730 case BRW_OPCODE_SEL:
731 brw_SEL(p, dst, src[0], src[1]);
732 break;
733
734 case BRW_OPCODE_DPH:
735 brw_DPH(p, dst, src[0], src[1]);
736 break;
737
738 case BRW_OPCODE_DP4:
739 brw_DP4(p, dst, src[0], src[1]);
740 break;
741
742 case BRW_OPCODE_DP3:
743 brw_DP3(p, dst, src[0], src[1]);
744 break;
745
746 case BRW_OPCODE_DP2:
747 brw_DP2(p, dst, src[0], src[1]);
748 break;
749
750 case BRW_OPCODE_F32TO16:
751 brw_F32TO16(p, dst, src[0]);
752 break;
753
754 case BRW_OPCODE_F16TO32:
755 brw_F16TO32(p, dst, src[0]);
756 break;
757
758 case BRW_OPCODE_LRP:
759 brw_LRP(p, dst, src[0], src[1], src[2]);
760 break;
761
762 case BRW_OPCODE_BFREV:
763 /* BFREV only supports UD type for src and dst. */
764 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
765 retype(src[0], BRW_REGISTER_TYPE_UD));
766 break;
767 case BRW_OPCODE_FBH:
768 /* FBH only supports UD type for dst. */
769 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
770 break;
771 case BRW_OPCODE_FBL:
772 /* FBL only supports UD type for dst. */
773 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
774 break;
775 case BRW_OPCODE_CBIT:
776 /* CBIT only supports UD type for dst. */
777 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
778 break;
779
780 case BRW_OPCODE_BFE:
781 brw_BFE(p, dst, src[0], src[1], src[2]);
782 break;
783
784 case BRW_OPCODE_BFI1:
785 brw_BFI1(p, dst, src[0], src[1]);
786 break;
787 case BRW_OPCODE_BFI2:
788 brw_BFI2(p, dst, src[0], src[1], src[2]);
789 break;
790
791 case BRW_OPCODE_IF:
792 if (inst->src[0].file != BAD_FILE) {
793 /* The instruction has an embedded compare (only allowed on gen6) */
794 assert(brw->gen == 6);
795 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
796 } else {
797 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
798 brw_inst->header.predicate_control = inst->predicate;
799 }
800 break;
801
802 case BRW_OPCODE_ELSE:
803 brw_ELSE(p);
804 break;
805 case BRW_OPCODE_ENDIF:
806 brw_ENDIF(p);
807 break;
808
809 case BRW_OPCODE_DO:
810 brw_DO(p, BRW_EXECUTE_8);
811 break;
812
813 case BRW_OPCODE_BREAK:
814 brw_BREAK(p);
815 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
816 break;
817 case BRW_OPCODE_CONTINUE:
818 /* FINISHME: We need to write the loop instruction support still. */
819 if (brw->gen >= 6)
820 gen6_CONT(p);
821 else
822 brw_CONT(p);
823 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
824 break;
825
826 case BRW_OPCODE_WHILE:
827 brw_WHILE(p);
828 break;
829
830 case SHADER_OPCODE_RCP:
831 case SHADER_OPCODE_RSQ:
832 case SHADER_OPCODE_SQRT:
833 case SHADER_OPCODE_EXP2:
834 case SHADER_OPCODE_LOG2:
835 case SHADER_OPCODE_SIN:
836 case SHADER_OPCODE_COS:
837 if (brw->gen == 6) {
838 generate_math1_gen6(inst, dst, src[0]);
839 } else {
840 /* Also works for Gen7. */
841 generate_math1_gen4(inst, dst, src[0]);
842 }
843 break;
844
845 case SHADER_OPCODE_POW:
846 case SHADER_OPCODE_INT_QUOTIENT:
847 case SHADER_OPCODE_INT_REMAINDER:
848 if (brw->gen >= 7) {
849 generate_math2_gen7(inst, dst, src[0], src[1]);
850 } else if (brw->gen == 6) {
851 generate_math2_gen6(inst, dst, src[0], src[1]);
852 } else {
853 generate_math2_gen4(inst, dst, src[0], src[1]);
854 }
855 break;
856
857 case SHADER_OPCODE_TEX:
858 case SHADER_OPCODE_TXD:
859 case SHADER_OPCODE_TXF:
860 case SHADER_OPCODE_TXF_MS:
861 case SHADER_OPCODE_TXL:
862 case SHADER_OPCODE_TXS:
863 generate_tex(inst, dst, src[0]);
864 break;
865
866 case VS_OPCODE_URB_WRITE:
867 generate_urb_write(inst);
868 break;
869
870 case VS_OPCODE_SCRATCH_READ:
871 generate_scratch_read(inst, dst, src[0]);
872 break;
873
874 case VS_OPCODE_SCRATCH_WRITE:
875 generate_scratch_write(inst, dst, src[0], src[1]);
876 break;
877
878 case VS_OPCODE_PULL_CONSTANT_LOAD:
879 generate_pull_constant_load(inst, dst, src[0], src[1]);
880 break;
881
882 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
883 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
884 break;
885
886 case SHADER_OPCODE_SHADER_TIME_ADD:
887 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
888 mark_surface_used(SURF_INDEX_VS_SHADER_TIME);
889 break;
890
891 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
892 generate_unpack_flags(inst, dst);
893 break;
894
895 default:
896 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
897 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
898 opcode_descs[inst->opcode].name);
899 } else {
900 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
901 }
902 abort();
903 }
904 }
905
906 void
907 vec4_generator::generate_code(exec_list *instructions)
908 {
909 int last_native_insn_offset = 0;
910 const char *last_annotation_string = NULL;
911 const void *last_annotation_ir = NULL;
912
913 if (unlikely(debug_flag)) {
914 if (shader) {
915 printf("Native code for vertex shader %d:\n", shader_prog->Name);
916 } else {
917 printf("Native code for vertex program %d:\n", prog->Id);
918 }
919 }
920
921 foreach_list(node, instructions) {
922 vec4_instruction *inst = (vec4_instruction *)node;
923 struct brw_reg src[3], dst;
924
925 if (unlikely(debug_flag)) {
926 if (last_annotation_ir != inst->ir) {
927 last_annotation_ir = inst->ir;
928 if (last_annotation_ir) {
929 printf(" ");
930 if (shader) {
931 ((ir_instruction *) last_annotation_ir)->print();
932 } else {
933 const prog_instruction *vpi;
934 vpi = (const prog_instruction *) inst->ir;
935 printf("%d: ", (int)(vpi - prog->Instructions));
936 _mesa_fprint_instruction_opt(stdout, vpi, 0,
937 PROG_PRINT_DEBUG, NULL);
938 }
939 printf("\n");
940 }
941 }
942 if (last_annotation_string != inst->annotation) {
943 last_annotation_string = inst->annotation;
944 if (last_annotation_string)
945 printf(" %s\n", last_annotation_string);
946 }
947 }
948
949 for (unsigned int i = 0; i < 3; i++) {
950 src[i] = inst->get_src(this->prog_data, i);
951 }
952 dst = inst->get_dst();
953
954 brw_set_conditionalmod(p, inst->conditional_mod);
955 brw_set_predicate_control(p, inst->predicate);
956 brw_set_predicate_inverse(p, inst->predicate_inverse);
957 brw_set_saturate(p, inst->saturate);
958 brw_set_mask_control(p, inst->force_writemask_all);
959
960 unsigned pre_emit_nr_insn = p->nr_insn;
961
962 generate_vec4_instruction(inst, dst, src);
963
964 if (inst->no_dd_clear || inst->no_dd_check) {
965 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
966 !"no_dd_check or no_dd_clear set for IR emitting more "
967 "than 1 instruction");
968
969 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
970
971 if (inst->no_dd_clear)
972 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
973 if (inst->no_dd_check)
974 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
975 }
976
977 if (unlikely(debug_flag)) {
978 brw_dump_compile(p, stdout,
979 last_native_insn_offset, p->next_insn_offset);
980 }
981
982 last_native_insn_offset = p->next_insn_offset;
983 }
984
985 if (unlikely(debug_flag)) {
986 printf("\n");
987 }
988
989 brw_set_uip_jip(p);
990
991 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
992 * emit issues, it doesn't get the jump distances into the output,
993 * which is often something we want to debug. So this is here in
994 * case you're doing that.
995 */
996 if (0 && unlikely(debug_flag)) {
997 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
998 }
999 }
1000
1001 const unsigned *
1002 vec4_generator::generate_assembly(exec_list *instructions,
1003 unsigned *assembly_size)
1004 {
1005 brw_set_access_mode(p, BRW_ALIGN_16);
1006 generate_code(instructions);
1007 return brw_get_program(p, assembly_size);
1008 }
1009
1010 } /* namespace brw */