src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45       }
  46    }
  47
  48    foreach_list(node, &this->instructions) {
  49       vec4_instruction *inst = (vec4_instruction *)node;
  50
  51       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  52       if (inst->dst.file == ATTR) {
  53          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  54
  55          struct brw_reg reg = brw_vec8_grf(grf, 0);
  56          reg.dw1.bits.writemask = inst->dst.writemask;
  57
  58          inst->dst.file = HW_REG;
  59          inst->dst.fixed_hw_reg = reg;
  60       }
  61
  62       for (int i = 0; i < 3; i++) {
  63          if (inst->src[i].file != ATTR)
  64             continue;
  65
  66          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  67
  68          struct brw_reg reg = brw_vec8_grf(grf, 0);
  69          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  70          if (inst->src[i].abs)
  71             reg = brw_abs(reg);
  72          if (inst->src[i].negate)
  73             reg = negate(reg);
  74
  75          inst->src[i].file = HW_REG;
  76          inst->src[i].fixed_hw_reg = reg;
  77       }
  78    }
  79
  80    /* The BSpec says we always have to read at least one thing from
  81     * the VF, and it appears that the hardware wedges otherwise.
  82     */
  83    if (nr_attributes == 0)
  84       nr_attributes = 1;
  85
  86    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  87
  88    return payload_reg + nr_attributes;
  89 }
  90
  91 int
  92 vec4_visitor::setup_uniforms(int reg)
  93 {
  94    /* User clip planes from curbe:
  95     */
  96    if (c->key.nr_userclip) {
  97       if (intel->gen >= 6) {
  98          for (int i = 0; i < c->key.nr_userclip; i++) {
  99             c->userplane[i] = stride(brw_vec4_grf(reg + i / 2,
 100                                                   (i % 2) * 4), 0, 4, 1);
 101          }
 102          reg += ALIGN(c->key.nr_userclip, 2) / 2;
 103       } else {
 104          for (int i = 0; i < c->key.nr_userclip; i++) {
 105             c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2,
 106                                                   (i % 2) * 4), 0, 4, 1);
 107          }
 108          reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2;
 109       }
 110    }
 111
 112    /* The pre-gen6 VS requires that some push constants get loaded no
 113     * matter what, or the GPU would hang.
 114     */
 115    if (intel->gen < 6 && this->uniforms == 0) {
 116       this->uniform_vector_size[this->uniforms] = 1;
 117
 118       for (unsigned int i = 0; i < 4; i++) {
 119          unsigned int slot = this->uniforms * 4 + i;
 120          static float zero = 0.0;
 121          c->prog_data.param[slot] = &zero;
 122       }
 123
 124       this->uniforms++;
 125       reg++;
 126    } else {
 127       reg += ALIGN(uniforms, 2) / 2;
 128    }
 129
 130    c->prog_data.nr_params = this->uniforms * 4;
 131
 132    c->prog_data.curb_read_length = reg - 1;
 133    c->prog_data.uses_new_param_layout = true;
 134
 135    return reg;
 136 }
 137
 138 void
 139 vec4_visitor::setup_payload(void)
 140 {
 141    int reg = 0;
 142
 143    /* The payload always contains important data in g0, which contains
 144     * the URB handles that are passed on to the URB write at the end
 145     * of the thread.  So, we always start push constants at g1.
 146     */
 147    reg++;
 148
 149    reg = setup_uniforms(reg);
 150
 151    reg = setup_attributes(reg);
 152
 153    this->first_non_payload_grf = reg;
 154 }
 155
 156 struct brw_reg
 157 vec4_instruction::get_dst(void)
 158 {
 159    struct brw_reg brw_reg;
 160
 161    switch (dst.file) {
 162    case GRF:
 163       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 164       brw_reg = retype(brw_reg, dst.type);
 165       brw_reg.dw1.bits.writemask = dst.writemask;
 166       break;
 167
 168    case HW_REG:
 169       brw_reg = dst.fixed_hw_reg;
 170       break;
 171
 172    case BAD_FILE:
 173       brw_reg = brw_null_reg();
 174       break;
 175
 176    default:
 177       assert(!"not reached");
 178       brw_reg = brw_null_reg();
 179       break;
 180    }
 181    return brw_reg;
 182 }
 183
 184 struct brw_reg
 185 vec4_instruction::get_src(int i)
 186 {
 187    struct brw_reg brw_reg;
 188
 189    switch (src[i].file) {
 190    case GRF:
 191       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 192       brw_reg = retype(brw_reg, src[i].type);
 193       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 194       if (src[i].abs)
 195          brw_reg = brw_abs(brw_reg);
 196       if (src[i].negate)
 197          brw_reg = negate(brw_reg);
 198       break;
 199
 200    case IMM:
 201       switch (src[i].type) {
 202       case BRW_REGISTER_TYPE_F:
 203          brw_reg = brw_imm_f(src[i].imm.f);
 204          break;
 205       case BRW_REGISTER_TYPE_D:
 206          brw_reg = brw_imm_d(src[i].imm.i);
 207          break;
 208       case BRW_REGISTER_TYPE_UD:
 209          brw_reg = brw_imm_ud(src[i].imm.u);
 210          break;
 211       default:
 212          assert(!"not reached");
 213          brw_reg = brw_null_reg();
 214          break;
 215       }
 216       break;
 217
 218    case UNIFORM:
 219       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 220                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 221                        0, 4, 1);
 222       brw_reg = retype(brw_reg, src[i].type);
 223       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 224       if (src[i].abs)
 225          brw_reg = brw_abs(brw_reg);
 226       if (src[i].negate)
 227          brw_reg = negate(brw_reg);
 228
 229       /* This should have been moved to pull constants. */
 230       assert(!src[i].reladdr);
 231       break;
 232
 233    case HW_REG:
 234       brw_reg = src[i].fixed_hw_reg;
 235       break;
 236
 237    case BAD_FILE:
 238       /* Probably unused. */
 239       brw_reg = brw_null_reg();
 240       break;
 241    case ATTR:
 242    default:
 243       assert(!"not reached");
 244       brw_reg = brw_null_reg();
 245       break;
 246    }
 247
 248    return brw_reg;
 249 }
 250
 251 void
 252 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 253                                   struct brw_reg dst,
 254                                   struct brw_reg src)
 255 {
 256    brw_math(p,
 257             dst,
 258             brw_math_function(inst->opcode),
 259             BRW_MATH_SATURATE_NONE,
 260             inst->base_mrf,
 261             src,
 262             BRW_MATH_DATA_VECTOR,
 263             BRW_MATH_PRECISION_FULL);
 264 }
 265
 266 static void
 267 check_gen6_math_src_arg(struct brw_reg src)
 268 {
 269    /* Source swizzles are ignored. */
 270    assert(!src.abs);
 271    assert(!src.negate);
 272    assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
 273 }
 274
 275 void
 276 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 277                                   struct brw_reg dst,
 278                                   struct brw_reg src)
 279 {
 280    /* Can't do writemask because math can't be align16. */
 281    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 282    check_gen6_math_src_arg(src);
 283
 284    brw_set_access_mode(p, BRW_ALIGN_1);
 285    brw_math(p,
 286             dst,
 287             brw_math_function(inst->opcode),
 288             BRW_MATH_SATURATE_NONE,
 289             inst->base_mrf,
 290             src,
 291             BRW_MATH_DATA_SCALAR,
 292             BRW_MATH_PRECISION_FULL);
 293    brw_set_access_mode(p, BRW_ALIGN_16);
 294 }
 295
 296 void
 297 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 298                                   struct brw_reg dst,
 299                                   struct brw_reg src0,
 300                                   struct brw_reg src1)
 301 {
 302    /* Can't do writemask because math can't be align16. */
 303    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 304    /* Source swizzles are ignored. */
 305    check_gen6_math_src_arg(src0);
 306    check_gen6_math_src_arg(src1);
 307
 308    brw_set_access_mode(p, BRW_ALIGN_1);
 309    brw_math2(p,
 310              dst,
 311              brw_math_function(inst->opcode),
 312              src0, src1);
 313    brw_set_access_mode(p, BRW_ALIGN_16);
 314 }
 315
 316 void
 317 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 318                                   struct brw_reg dst,
 319                                   struct brw_reg src0,
 320                                   struct brw_reg src1)
 321 {
 322    brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
 323
 324    brw_math(p,
 325             dst,
 326             brw_math_function(inst->opcode),
 327             BRW_MATH_SATURATE_NONE,
 328             inst->base_mrf,
 329             src0,
 330             BRW_MATH_DATA_VECTOR,
 331             BRW_MATH_PRECISION_FULL);
 332 }
 333
 334 void
 335 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 336 {
 337    brw_urb_WRITE(p,
 338                  brw_null_reg(), /* dest */
 339                  inst->base_mrf, /* starting mrf reg nr */
 340                  brw_vec8_grf(0, 0), /* src */
 341                  false,         /* allocate */
 342                  true,          /* used */
 343                  inst->mlen,
 344                  0,             /* response len */
 345                  inst->eot,     /* eot */
 346                  inst->eot,     /* writes complete */
 347                  inst->offset,  /* urb destination offset */
 348                  BRW_URB_SWIZZLE_INTERLEAVE);
 349 }
 350
 351 void
 352 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 353                                                 struct brw_reg index)
 354 {
 355    int second_vertex_offset;
 356
 357    if (intel->gen >= 6)
 358       second_vertex_offset = 1;
 359    else
 360       second_vertex_offset = 16;
 361
 362    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 363
 364    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 365     * M1.4 are used, and the rest are ignored.
 366     */
 367    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 368    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 369    struct brw_reg index_0 = suboffset(vec1(index), 0);
 370    struct brw_reg index_4 = suboffset(vec1(index), 4);
 371
 372    brw_push_insn_state(p);
 373    brw_set_mask_control(p, BRW_MASK_DISABLE);
 374    brw_set_access_mode(p, BRW_ALIGN_1);
 375
 376    brw_MOV(p, m1_0, index_0);
 377
 378    brw_set_predicate_inverse(p, true);
 379    if (index.file == BRW_IMMEDIATE_VALUE) {
 380       index_4.dw1.ud += second_vertex_offset;
 381       brw_MOV(p, m1_4, index_4);
 382    } else {
 383       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 384    }
 385
 386    brw_pop_insn_state(p);
 387 }
 388
 389 void
 390 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 391                                     struct brw_reg dst,
 392                                     struct brw_reg index)
 393 {
 394    struct brw_reg header = brw_vec8_grf(0, 0);
 395
 396    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 397
 398    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 399                                      index);
 400
 401    uint32_t msg_type;
 402
 403    if (intel->gen >= 6)
 404       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 405    else if (intel->gen == 5 || intel->is_g4x)
 406       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 407    else
 408       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 409
 410    /* Each of the 8 channel enables is considered for whether each
 411     * dword is written.
 412     */
 413    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 414    brw_set_dest(p, send, dst);
 415    brw_set_src0(p, send, header);
 416    if (intel->gen < 6)
 417       send->header.destreg__conditionalmod = inst->base_mrf;
 418    brw_set_dp_read_message(p, send,
 419                            255, /* binding table index: stateless access */
 420                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 421                            msg_type,
 422                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 423                            2, /* mlen */
 424                            1 /* rlen */);
 425 }
 426
 427 void
 428 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 429                                      struct brw_reg dst,
 430                                      struct brw_reg src,
 431                                      struct brw_reg index)
 432 {
 433    struct brw_reg header = brw_vec8_grf(0, 0);
 434    bool write_commit;
 435
 436    /* If the instruction is predicated, we'll predicate the send, not
 437     * the header setup.
 438     */
 439    brw_set_predicate_control(p, false);
 440
 441    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 442
 443    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 444                                      index);
 445
 446    brw_MOV(p,
 447            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 448            retype(src, BRW_REGISTER_TYPE_D));
 449
 450    uint32_t msg_type;
 451
 452    if (intel->gen >= 6)
 453       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 454    else
 455       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 456
 457    brw_set_predicate_control(p, inst->predicate);
 458
 459    /* Pre-gen6, we have to specify write commits to ensure ordering
 460     * between reads and writes within a thread.  Afterwards, that's
 461     * guaranteed and write commits only matter for inter-thread
 462     * synchronization.
 463     */
 464    if (intel->gen >= 6) {
 465       write_commit = false;
 466    } else {
 467       /* The visitor set up our destination register to be g0.  This
 468        * means that when the next read comes along, we will end up
 469        * reading from g0 and causing a block on the write commit.  For
 470        * write-after-read, we are relying on the value of the previous
 471        * read being used (and thus blocking on completion) before our
 472        * write is executed.  This means we have to be careful in
 473        * instruction scheduling to not violate this assumption.
 474        */
 475       write_commit = true;
 476    }
 477
 478    /* Each of the 8 channel enables is considered for whether each
 479     * dword is written.
 480     */
 481    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 482    brw_set_dest(p, send, dst);
 483    brw_set_src0(p, send, header);
 484    if (intel->gen < 6)
 485       send->header.destreg__conditionalmod = inst->base_mrf;
 486    brw_set_dp_write_message(p, send,
 487                             255, /* binding table index: stateless access */
 488                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 489                             msg_type,
 490                             3, /* mlen */
 491                             true, /* header present */
 492                             false, /* pixel scoreboard */
 493                             write_commit, /* rlen */
 494                             false, /* eot */
 495                             write_commit);
 496 }
 497
 498 void
 499 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 500                                           struct brw_reg dst,
 501                                           struct brw_reg index)
 502 {
 503    struct brw_reg header = brw_vec8_grf(0, 0);
 504
 505    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 506
 507    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 508            index);
 509
 510    uint32_t msg_type;
 511
 512    if (intel->gen >= 6)
 513       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 514    else if (intel->gen == 5 || intel->is_g4x)
 515       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 516    else
 517       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 518
 519    /* Each of the 8 channel enables is considered for whether each
 520     * dword is written.
 521     */
 522    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 523    brw_set_dest(p, send, dst);
 524    brw_set_src0(p, send, header);
 525    if (intel->gen < 6)
 526       send->header.destreg__conditionalmod = inst->base_mrf;
 527    brw_set_dp_read_message(p, send,
 528                            SURF_INDEX_VERT_CONST_BUFFER,
 529                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 530                            msg_type,
 531                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 532                            2, /* mlen */
 533                            1 /* rlen */);
 534 }
 535
 536 void
 537 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 538                                       struct brw_reg dst,
 539                                       struct brw_reg *src)
 540 {
 541    vec4_instruction *inst = (vec4_instruction *)instruction;
 542
 543    switch (inst->opcode) {
 544    case SHADER_OPCODE_RCP:
 545    case SHADER_OPCODE_RSQ:
 546    case SHADER_OPCODE_SQRT:
 547    case SHADER_OPCODE_EXP2:
 548    case SHADER_OPCODE_LOG2:
 549    case SHADER_OPCODE_SIN:
 550    case SHADER_OPCODE_COS:
 551       if (intel->gen >= 6) {
 552          generate_math1_gen6(inst, dst, src[0]);
 553       } else {
 554          generate_math1_gen4(inst, dst, src[0]);
 555       }
 556       break;
 557
 558    case SHADER_OPCODE_POW:
 559       if (intel->gen >= 6) {
 560          generate_math2_gen6(inst, dst, src[0], src[1]);
 561       } else {
 562          generate_math2_gen4(inst, dst, src[0], src[1]);
 563       }
 564       break;
 565
 566    case VS_OPCODE_URB_WRITE:
 567       generate_urb_write(inst);
 568       break;
 569
 570    case VS_OPCODE_SCRATCH_READ:
 571       generate_scratch_read(inst, dst, src[0]);
 572       break;
 573
 574    case VS_OPCODE_SCRATCH_WRITE:
 575       generate_scratch_write(inst, dst, src[0], src[1]);
 576       break;
 577
 578    case VS_OPCODE_PULL_CONSTANT_LOAD:
 579       generate_pull_constant_load(inst, dst, src[0]);
 580       break;
 581
 582    default:
 583       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 584          fail("unsupported opcode in `%s' in VS\n",
 585               brw_opcodes[inst->opcode].name);
 586       } else {
 587          fail("Unsupported opcode %d in VS", inst->opcode);
 588       }
 589    }
 590 }
 591
 592 bool
 593 vec4_visitor::run()
 594 {
 595    /* Generate VS IR for main().  (the visitor only descends into
 596     * functions called "main").
 597     */
 598    visit_instructions(shader->ir);
 599
 600    emit_urb_writes();
 601
 602    /* Before any optimization, push array accesses out to scratch
 603     * space where we need them to be.  This pass may allocate new
 604     * virtual GRFs, so we want to do it early.  It also makes sure
 605     * that we have reladdr computations available for CSE, since we'll
 606     * often do repeated subexpressions for those.
 607     */
 608    move_grf_array_access_to_scratch();
 609    move_uniform_array_access_to_pull_constants();
 610    pack_uniform_registers();
 611    move_push_constants_to_pull_constants();
 612
 613    bool progress;
 614    do {
 615       progress = false;
 616       progress = dead_code_eliminate() || progress;
 617       progress = opt_copy_propagation() || progress;
 618       progress = opt_algebraic() || progress;
 619    } while (progress);
 620
 621
 622    if (failed)
 623       return false;
 624
 625    setup_payload();
 626    reg_allocate();
 627
 628    if (failed)
 629       return false;
 630
 631    brw_set_access_mode(p, BRW_ALIGN_16);
 632
 633    generate_code();
 634
 635    return !failed;
 636 }
 637
 638 void
 639 vec4_visitor::generate_code()
 640 {
 641    int last_native_inst = 0;
 642    const char *last_annotation_string = NULL;
 643    ir_instruction *last_annotation_ir = NULL;
 644
 645    int loop_stack_array_size = 16;
 646    int loop_stack_depth = 0;
 647    brw_instruction **loop_stack =
 648       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 649    int *if_depth_in_loop =
 650       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 651
 652
 653    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 654       printf("Native code for vertex shader %d:\n", prog->Name);
 655    }
 656
 657    foreach_list(node, &this->instructions) {
 658       vec4_instruction *inst = (vec4_instruction *)node;
 659       struct brw_reg src[3], dst;
 660
 661       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 662          if (last_annotation_ir != inst->ir) {
 663             last_annotation_ir = inst->ir;
 664             if (last_annotation_ir) {
 665                printf("   ");
 666                last_annotation_ir->print();
 667                printf("\n");
 668             }
 669          }
 670          if (last_annotation_string != inst->annotation) {
 671             last_annotation_string = inst->annotation;
 672             if (last_annotation_string)
 673                printf("   %s\n", last_annotation_string);
 674          }
 675       }
 676
 677       for (unsigned int i = 0; i < 3; i++) {
 678          src[i] = inst->get_src(i);
 679       }
 680       dst = inst->get_dst();
 681
 682       brw_set_conditionalmod(p, inst->conditional_mod);
 683       brw_set_predicate_control(p, inst->predicate);
 684       brw_set_predicate_inverse(p, inst->predicate_inverse);
 685       brw_set_saturate(p, inst->saturate);
 686
 687       switch (inst->opcode) {
 688       case BRW_OPCODE_MOV:
 689          brw_MOV(p, dst, src[0]);
 690          break;
 691       case BRW_OPCODE_ADD:
 692          brw_ADD(p, dst, src[0], src[1]);
 693          break;
 694       case BRW_OPCODE_MUL:
 695          brw_MUL(p, dst, src[0], src[1]);
 696          break;
 697       case BRW_OPCODE_MACH:
 698          brw_set_acc_write_control(p, 1);
 699          brw_MACH(p, dst, src[0], src[1]);
 700          brw_set_acc_write_control(p, 0);
 701          break;
 702
 703       case BRW_OPCODE_FRC:
 704          brw_FRC(p, dst, src[0]);
 705          break;
 706       case BRW_OPCODE_RNDD:
 707          brw_RNDD(p, dst, src[0]);
 708          break;
 709       case BRW_OPCODE_RNDE:
 710          brw_RNDE(p, dst, src[0]);
 711          break;
 712       case BRW_OPCODE_RNDZ:
 713          brw_RNDZ(p, dst, src[0]);
 714          break;
 715
 716       case BRW_OPCODE_AND:
 717          brw_AND(p, dst, src[0], src[1]);
 718          break;
 719       case BRW_OPCODE_OR:
 720          brw_OR(p, dst, src[0], src[1]);
 721          break;
 722       case BRW_OPCODE_XOR:
 723          brw_XOR(p, dst, src[0], src[1]);
 724          break;
 725       case BRW_OPCODE_NOT:
 726          brw_NOT(p, dst, src[0]);
 727          break;
 728       case BRW_OPCODE_ASR:
 729          brw_ASR(p, dst, src[0], src[1]);
 730          break;
 731       case BRW_OPCODE_SHR:
 732          brw_SHR(p, dst, src[0], src[1]);
 733          break;
 734       case BRW_OPCODE_SHL:
 735          brw_SHL(p, dst, src[0], src[1]);
 736          break;
 737
 738       case BRW_OPCODE_CMP:
 739          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 740          break;
 741       case BRW_OPCODE_SEL:
 742          brw_SEL(p, dst, src[0], src[1]);
 743          break;
 744
 745       case BRW_OPCODE_DP4:
 746          brw_DP4(p, dst, src[0], src[1]);
 747          break;
 748
 749       case BRW_OPCODE_DP3:
 750          brw_DP3(p, dst, src[0], src[1]);
 751          break;
 752
 753       case BRW_OPCODE_DP2:
 754          brw_DP2(p, dst, src[0], src[1]);
 755          break;
 756
 757       case BRW_OPCODE_IF:
 758          if (inst->src[0].file != BAD_FILE) {
 759             /* The instruction has an embedded compare (only allowed on gen6) */
 760             assert(intel->gen == 6);
 761             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 762          } else {
 763             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 764             brw_inst->header.predicate_control = inst->predicate;
 765          }
 766          if_depth_in_loop[loop_stack_depth]++;
 767          break;
 768
 769       case BRW_OPCODE_ELSE:
 770          brw_ELSE(p);
 771          break;
 772       case BRW_OPCODE_ENDIF:
 773          brw_ENDIF(p);
 774          if_depth_in_loop[loop_stack_depth]--;
 775          break;
 776
 777       case BRW_OPCODE_DO:
 778          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 779          if (loop_stack_array_size <= loop_stack_depth) {
 780             loop_stack_array_size *= 2;
 781             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 782                                   loop_stack_array_size);
 783             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 784                                         loop_stack_array_size);
 785          }
 786          if_depth_in_loop[loop_stack_depth] = 0;
 787          break;
 788
 789       case BRW_OPCODE_BREAK:
 790          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 791          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 792          break;
 793       case BRW_OPCODE_CONTINUE:
 794          /* FINISHME: We need to write the loop instruction support still. */
 795          if (intel->gen >= 6)
 796             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 797          else
 798             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 799          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 800          break;
 801
 802       case BRW_OPCODE_WHILE: {
 803          struct brw_instruction *inst0, *inst1;
 804          GLuint br = 1;
 805
 806          if (intel->gen >= 5)
 807             br = 2;
 808
 809          assert(loop_stack_depth > 0);
 810          loop_stack_depth--;
 811          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 812          if (intel->gen < 6) {
 813             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 814             while (inst0 > loop_stack[loop_stack_depth]) {
 815                inst0--;
 816                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 817                    inst0->bits3.if_else.jump_count == 0) {
 818                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 819             }
 820                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 821                         inst0->bits3.if_else.jump_count == 0) {
 822                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 823                }
 824             }
 825          }
 826       }
 827          break;
 828
 829       default:
 830          generate_vs_instruction(inst, dst, src);
 831          break;
 832       }
 833
 834       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 835          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 836             if (0) {
 837                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 838                       ((uint32_t *)&p->store[i])[3],
 839                       ((uint32_t *)&p->store[i])[2],
 840                       ((uint32_t *)&p->store[i])[1],
 841                       ((uint32_t *)&p->store[i])[0]);
 842             }
 843             brw_disasm(stdout, &p->store[i], intel->gen);
 844          }
 845       }
 846
 847       last_native_inst = p->nr_insn;
 848    }
 849
 850    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 851       printf("\n");
 852    }
 853
 854    ralloc_free(loop_stack);
 855    ralloc_free(if_depth_in_loop);
 856
 857    brw_set_uip_jip(p);
 858
 859    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 860     * emit issues, it doesn't get the jump distances into the output,
 861     * which is often something we want to debug.  So this is here in
 862     * case you're doing that.
 863     */
 864    if (0) {
 865       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 866          for (unsigned int i = 0; i < p->nr_insn; i++) {
 867             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 868                    ((uint32_t *)&p->store[i])[3],
 869                    ((uint32_t *)&p->store[i])[2],
 870                    ((uint32_t *)&p->store[i])[1],
 871                    ((uint32_t *)&p->store[i])[0]);
 872             brw_disasm(stdout, &p->store[i], intel->gen);
 873          }
 874       }
 875    }
 876 }
 877
 878 extern "C" {
 879
 880 bool
 881 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
 882 {
 883    if (!prog)
 884       return false;
 885
 886    struct brw_shader *shader =
 887      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
 888    if (!shader)
 889       return false;
 890
 891    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 892       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
 893       _mesa_print_ir(shader->ir, NULL);
 894       printf("\n\n");
 895    }
 896
 897    vec4_visitor v(c, prog, shader);
 898    if (!v.run()) {
 899       prog->LinkStatus = GL_FALSE;
 900       ralloc_strcat(&prog->InfoLog, v.fail_msg);
 901       return false;
 902    }
 903
 904    return true;
 905 }
 906
 907 } /* extern "C" */
 908
 909 } /* namespace brw */