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747edc29a13496ea253482f532b7d90ec3fa1a27
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct brw_vs_compile *c,
137 struct gl_shader_program *prog,
138 void *mem_ctx)
139 : brw(brw), c(c), prog(prog), mem_ctx(mem_ctx)
140 {
141 intel = &brw->intel;
142 vp = &c->vp->program;
143
144 shader = prog ? prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
145
146 p = rzalloc(mem_ctx, struct brw_compile);
147 brw_init_compile(brw, p, mem_ctx);
148 }
149
150 vec4_generator::~vec4_generator()
151 {
152 }
153
154 void
155 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
156 struct brw_reg dst,
157 struct brw_reg src)
158 {
159 brw_math(p,
160 dst,
161 brw_math_function(inst->opcode),
162 inst->base_mrf,
163 src,
164 BRW_MATH_DATA_VECTOR,
165 BRW_MATH_PRECISION_FULL);
166 }
167
168 static void
169 check_gen6_math_src_arg(struct brw_reg src)
170 {
171 /* Source swizzles are ignored. */
172 assert(!src.abs);
173 assert(!src.negate);
174 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
175 }
176
177 void
178 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
179 struct brw_reg dst,
180 struct brw_reg src)
181 {
182 /* Can't do writemask because math can't be align16. */
183 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
184 check_gen6_math_src_arg(src);
185
186 brw_set_access_mode(p, BRW_ALIGN_1);
187 brw_math(p,
188 dst,
189 brw_math_function(inst->opcode),
190 inst->base_mrf,
191 src,
192 BRW_MATH_DATA_SCALAR,
193 BRW_MATH_PRECISION_FULL);
194 brw_set_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 brw_math2(p,
204 dst,
205 brw_math_function(inst->opcode),
206 src0, src1);
207 }
208
209 void
210 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
211 struct brw_reg dst,
212 struct brw_reg src0,
213 struct brw_reg src1)
214 {
215 /* Can't do writemask because math can't be align16. */
216 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
217 /* Source swizzles are ignored. */
218 check_gen6_math_src_arg(src0);
219 check_gen6_math_src_arg(src1);
220
221 brw_set_access_mode(p, BRW_ALIGN_1);
222 brw_math2(p,
223 dst,
224 brw_math_function(inst->opcode),
225 src0, src1);
226 brw_set_access_mode(p, BRW_ALIGN_16);
227 }
228
229 void
230 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
231 struct brw_reg dst,
232 struct brw_reg src0,
233 struct brw_reg src1)
234 {
235 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
236 * "Message Payload":
237 *
238 * "Operand0[7]. For the INT DIV functions, this operand is the
239 * denominator."
240 * ...
241 * "Operand1[7]. For the INT DIV functions, this operand is the
242 * numerator."
243 */
244 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
245 struct brw_reg &op0 = is_int_div ? src1 : src0;
246 struct brw_reg &op1 = is_int_div ? src0 : src1;
247
248 brw_push_insn_state(p);
249 brw_set_saturate(p, false);
250 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
251 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
252 brw_pop_insn_state(p);
253
254 brw_math(p,
255 dst,
256 brw_math_function(inst->opcode),
257 inst->base_mrf,
258 op0,
259 BRW_MATH_DATA_VECTOR,
260 BRW_MATH_PRECISION_FULL);
261 }
262
263 void
264 vec4_generator::generate_tex(vec4_instruction *inst,
265 struct brw_reg dst,
266 struct brw_reg src)
267 {
268 int msg_type = -1;
269
270 if (intel->gen >= 5) {
271 switch (inst->opcode) {
272 case SHADER_OPCODE_TEX:
273 case SHADER_OPCODE_TXL:
274 if (inst->shadow_compare) {
275 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
276 } else {
277 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
278 }
279 break;
280 case SHADER_OPCODE_TXD:
281 if (inst->shadow_compare) {
282 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
283 assert(intel->is_haswell);
284 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
285 } else {
286 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
287 }
288 break;
289 case SHADER_OPCODE_TXF:
290 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
291 break;
292 case SHADER_OPCODE_TXS:
293 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
294 break;
295 default:
296 assert(!"should not get here: invalid VS texture opcode");
297 break;
298 }
299 } else {
300 switch (inst->opcode) {
301 case SHADER_OPCODE_TEX:
302 case SHADER_OPCODE_TXL:
303 if (inst->shadow_compare) {
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
305 assert(inst->mlen == 3);
306 } else {
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
308 assert(inst->mlen == 2);
309 }
310 break;
311 case SHADER_OPCODE_TXD:
312 /* There is no sample_d_c message; comparisons are done manually. */
313 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
314 assert(inst->mlen == 4);
315 break;
316 case SHADER_OPCODE_TXF:
317 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
318 assert(inst->mlen == 2);
319 break;
320 case SHADER_OPCODE_TXS:
321 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
322 assert(inst->mlen == 2);
323 break;
324 default:
325 assert(!"should not get here: invalid VS texture opcode");
326 break;
327 }
328 }
329
330 assert(msg_type != -1);
331
332 /* Load the message header if present. If there's a texture offset, we need
333 * to set it up explicitly and load the offset bitfield. Otherwise, we can
334 * use an implied move from g0 to the first message register.
335 */
336 if (inst->texture_offset) {
337 /* Explicitly set up the message header by copying g0 to the MRF. */
338 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
339 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
340
341 /* Then set the offset bits in DWord 2. */
342 brw_set_access_mode(p, BRW_ALIGN_1);
343 brw_MOV(p,
344 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
345 BRW_REGISTER_TYPE_UD),
346 brw_imm_uw(inst->texture_offset));
347 brw_set_access_mode(p, BRW_ALIGN_16);
348 } else if (inst->header_present) {
349 /* Set up an implied move from g0 to the MRF. */
350 src = brw_vec8_grf(0, 0);
351 }
352
353 uint32_t return_format;
354
355 switch (dst.type) {
356 case BRW_REGISTER_TYPE_D:
357 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
358 break;
359 case BRW_REGISTER_TYPE_UD:
360 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
361 break;
362 default:
363 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
364 break;
365 }
366
367 brw_SAMPLE(p,
368 dst,
369 inst->base_mrf,
370 src,
371 SURF_INDEX_VS_TEXTURE(inst->sampler),
372 inst->sampler,
373 WRITEMASK_XYZW,
374 msg_type,
375 1, /* response length */
376 inst->mlen,
377 inst->header_present,
378 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
379 return_format);
380 }
381
382 void
383 vec4_generator::generate_urb_write(vec4_instruction *inst)
384 {
385 brw_urb_WRITE(p,
386 brw_null_reg(), /* dest */
387 inst->base_mrf, /* starting mrf reg nr */
388 brw_vec8_grf(0, 0), /* src */
389 false, /* allocate */
390 true, /* used */
391 inst->mlen,
392 0, /* response len */
393 inst->eot, /* eot */
394 inst->eot, /* writes complete */
395 inst->offset, /* urb destination offset */
396 BRW_URB_SWIZZLE_INTERLEAVE);
397 }
398
399 void
400 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
401 struct brw_reg index)
402 {
403 int second_vertex_offset;
404
405 if (intel->gen >= 6)
406 second_vertex_offset = 1;
407 else
408 second_vertex_offset = 16;
409
410 m1 = retype(m1, BRW_REGISTER_TYPE_D);
411
412 /* Set up M1 (message payload). Only the block offsets in M1.0 and
413 * M1.4 are used, and the rest are ignored.
414 */
415 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
416 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
417 struct brw_reg index_0 = suboffset(vec1(index), 0);
418 struct brw_reg index_4 = suboffset(vec1(index), 4);
419
420 brw_push_insn_state(p);
421 brw_set_mask_control(p, BRW_MASK_DISABLE);
422 brw_set_access_mode(p, BRW_ALIGN_1);
423
424 brw_MOV(p, m1_0, index_0);
425
426 if (index.file == BRW_IMMEDIATE_VALUE) {
427 index_4.dw1.ud += second_vertex_offset;
428 brw_MOV(p, m1_4, index_4);
429 } else {
430 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
431 }
432
433 brw_pop_insn_state(p);
434 }
435
436 void
437 vec4_generator::generate_scratch_read(vec4_instruction *inst,
438 struct brw_reg dst,
439 struct brw_reg index)
440 {
441 struct brw_reg header = brw_vec8_grf(0, 0);
442
443 gen6_resolve_implied_move(p, &header, inst->base_mrf);
444
445 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
446 index);
447
448 uint32_t msg_type;
449
450 if (intel->gen >= 6)
451 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
452 else if (intel->gen == 5 || intel->is_g4x)
453 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
454 else
455 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
456
457 /* Each of the 8 channel enables is considered for whether each
458 * dword is written.
459 */
460 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
461 brw_set_dest(p, send, dst);
462 brw_set_src0(p, send, header);
463 if (intel->gen < 6)
464 send->header.destreg__conditionalmod = inst->base_mrf;
465 brw_set_dp_read_message(p, send,
466 255, /* binding table index: stateless access */
467 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
468 msg_type,
469 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
470 2, /* mlen */
471 true, /* header_present */
472 1 /* rlen */);
473 }
474
475 void
476 vec4_generator::generate_scratch_write(vec4_instruction *inst,
477 struct brw_reg dst,
478 struct brw_reg src,
479 struct brw_reg index)
480 {
481 struct brw_reg header = brw_vec8_grf(0, 0);
482 bool write_commit;
483
484 /* If the instruction is predicated, we'll predicate the send, not
485 * the header setup.
486 */
487 brw_set_predicate_control(p, false);
488
489 gen6_resolve_implied_move(p, &header, inst->base_mrf);
490
491 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
492 index);
493
494 brw_MOV(p,
495 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
496 retype(src, BRW_REGISTER_TYPE_D));
497
498 uint32_t msg_type;
499
500 if (intel->gen >= 7)
501 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
502 else if (intel->gen == 6)
503 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
504 else
505 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
506
507 brw_set_predicate_control(p, inst->predicate);
508
509 /* Pre-gen6, we have to specify write commits to ensure ordering
510 * between reads and writes within a thread. Afterwards, that's
511 * guaranteed and write commits only matter for inter-thread
512 * synchronization.
513 */
514 if (intel->gen >= 6) {
515 write_commit = false;
516 } else {
517 /* The visitor set up our destination register to be g0. This
518 * means that when the next read comes along, we will end up
519 * reading from g0 and causing a block on the write commit. For
520 * write-after-read, we are relying on the value of the previous
521 * read being used (and thus blocking on completion) before our
522 * write is executed. This means we have to be careful in
523 * instruction scheduling to not violate this assumption.
524 */
525 write_commit = true;
526 }
527
528 /* Each of the 8 channel enables is considered for whether each
529 * dword is written.
530 */
531 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
532 brw_set_dest(p, send, dst);
533 brw_set_src0(p, send, header);
534 if (intel->gen < 6)
535 send->header.destreg__conditionalmod = inst->base_mrf;
536 brw_set_dp_write_message(p, send,
537 255, /* binding table index: stateless access */
538 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
539 msg_type,
540 3, /* mlen */
541 true, /* header present */
542 false, /* not a render target write */
543 write_commit, /* rlen */
544 false, /* eot */
545 write_commit);
546 }
547
548 void
549 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
550 struct brw_reg dst,
551 struct brw_reg index,
552 struct brw_reg offset)
553 {
554 assert(index.file == BRW_IMMEDIATE_VALUE &&
555 index.type == BRW_REGISTER_TYPE_UD);
556 uint32_t surf_index = index.dw1.ud;
557
558 if (intel->gen == 7) {
559 gen6_resolve_implied_move(p, &offset, inst->base_mrf);
560 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
561 brw_set_dest(p, insn, dst);
562 brw_set_src0(p, insn, offset);
563 brw_set_sampler_message(p, insn,
564 surf_index,
565 0, /* LD message ignores sampler unit */
566 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
567 1, /* rlen */
568 1, /* mlen */
569 false, /* no header */
570 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
571 0);
572 return;
573 }
574
575 struct brw_reg header = brw_vec8_grf(0, 0);
576
577 gen6_resolve_implied_move(p, &header, inst->base_mrf);
578
579 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
580 offset);
581
582 uint32_t msg_type;
583
584 if (intel->gen >= 6)
585 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
586 else if (intel->gen == 5 || intel->is_g4x)
587 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
588 else
589 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
590
591 /* Each of the 8 channel enables is considered for whether each
592 * dword is written.
593 */
594 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
595 brw_set_dest(p, send, dst);
596 brw_set_src0(p, send, header);
597 if (intel->gen < 6)
598 send->header.destreg__conditionalmod = inst->base_mrf;
599 brw_set_dp_read_message(p, send,
600 surf_index,
601 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
602 msg_type,
603 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
604 2, /* mlen */
605 true, /* header_present */
606 1 /* rlen */);
607 }
608
609 void
610 vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
611 struct brw_reg dst,
612 struct brw_reg *src)
613 {
614 vec4_instruction *inst = (vec4_instruction *)instruction;
615
616 switch (inst->opcode) {
617 case SHADER_OPCODE_RCP:
618 case SHADER_OPCODE_RSQ:
619 case SHADER_OPCODE_SQRT:
620 case SHADER_OPCODE_EXP2:
621 case SHADER_OPCODE_LOG2:
622 case SHADER_OPCODE_SIN:
623 case SHADER_OPCODE_COS:
624 if (intel->gen == 6) {
625 generate_math1_gen6(inst, dst, src[0]);
626 } else {
627 /* Also works for Gen7. */
628 generate_math1_gen4(inst, dst, src[0]);
629 }
630 break;
631
632 case SHADER_OPCODE_POW:
633 case SHADER_OPCODE_INT_QUOTIENT:
634 case SHADER_OPCODE_INT_REMAINDER:
635 if (intel->gen >= 7) {
636 generate_math2_gen7(inst, dst, src[0], src[1]);
637 } else if (intel->gen == 6) {
638 generate_math2_gen6(inst, dst, src[0], src[1]);
639 } else {
640 generate_math2_gen4(inst, dst, src[0], src[1]);
641 }
642 break;
643
644 case SHADER_OPCODE_TEX:
645 case SHADER_OPCODE_TXD:
646 case SHADER_OPCODE_TXF:
647 case SHADER_OPCODE_TXL:
648 case SHADER_OPCODE_TXS:
649 generate_tex(inst, dst, src[0]);
650 break;
651
652 case VS_OPCODE_URB_WRITE:
653 generate_urb_write(inst);
654 break;
655
656 case VS_OPCODE_SCRATCH_READ:
657 generate_scratch_read(inst, dst, src[0]);
658 break;
659
660 case VS_OPCODE_SCRATCH_WRITE:
661 generate_scratch_write(inst, dst, src[0], src[1]);
662 break;
663
664 case VS_OPCODE_PULL_CONSTANT_LOAD:
665 generate_pull_constant_load(inst, dst, src[0], src[1]);
666 break;
667
668 case SHADER_OPCODE_SHADER_TIME_ADD:
669 brw_shader_time_add(p, inst->base_mrf, SURF_INDEX_VS_SHADER_TIME);
670 break;
671
672 default:
673 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
674 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
675 opcode_descs[inst->opcode].name);
676 } else {
677 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
678 }
679 abort();
680 }
681 }
682
683 void
684 vec4_generator::generate_code(exec_list *instructions)
685 {
686 int last_native_insn_offset = 0;
687 const char *last_annotation_string = NULL;
688 const void *last_annotation_ir = NULL;
689
690 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
691 if (shader) {
692 printf("Native code for vertex shader %d:\n", prog->Name);
693 } else {
694 printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
695 }
696 }
697
698 foreach_list(node, instructions) {
699 vec4_instruction *inst = (vec4_instruction *)node;
700 struct brw_reg src[3], dst;
701
702 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
703 if (last_annotation_ir != inst->ir) {
704 last_annotation_ir = inst->ir;
705 if (last_annotation_ir) {
706 printf(" ");
707 if (shader) {
708 ((ir_instruction *) last_annotation_ir)->print();
709 } else {
710 const prog_instruction *vpi;
711 vpi = (const prog_instruction *) inst->ir;
712 printf("%d: ", (int)(vpi - vp->Base.Instructions));
713 _mesa_fprint_instruction_opt(stdout, vpi, 0,
714 PROG_PRINT_DEBUG, NULL);
715 }
716 printf("\n");
717 }
718 }
719 if (last_annotation_string != inst->annotation) {
720 last_annotation_string = inst->annotation;
721 if (last_annotation_string)
722 printf(" %s\n", last_annotation_string);
723 }
724 }
725
726 for (unsigned int i = 0; i < 3; i++) {
727 src[i] = inst->get_src(i);
728 }
729 dst = inst->get_dst();
730
731 brw_set_conditionalmod(p, inst->conditional_mod);
732 brw_set_predicate_control(p, inst->predicate);
733 brw_set_predicate_inverse(p, inst->predicate_inverse);
734 brw_set_saturate(p, inst->saturate);
735 brw_set_mask_control(p, inst->force_writemask_all);
736
737 switch (inst->opcode) {
738 case BRW_OPCODE_MOV:
739 brw_MOV(p, dst, src[0]);
740 break;
741 case BRW_OPCODE_ADD:
742 brw_ADD(p, dst, src[0], src[1]);
743 break;
744 case BRW_OPCODE_MUL:
745 brw_MUL(p, dst, src[0], src[1]);
746 break;
747 case BRW_OPCODE_MACH:
748 brw_set_acc_write_control(p, 1);
749 brw_MACH(p, dst, src[0], src[1]);
750 brw_set_acc_write_control(p, 0);
751 break;
752
753 case BRW_OPCODE_FRC:
754 brw_FRC(p, dst, src[0]);
755 break;
756 case BRW_OPCODE_RNDD:
757 brw_RNDD(p, dst, src[0]);
758 break;
759 case BRW_OPCODE_RNDE:
760 brw_RNDE(p, dst, src[0]);
761 break;
762 case BRW_OPCODE_RNDZ:
763 brw_RNDZ(p, dst, src[0]);
764 break;
765
766 case BRW_OPCODE_AND:
767 brw_AND(p, dst, src[0], src[1]);
768 break;
769 case BRW_OPCODE_OR:
770 brw_OR(p, dst, src[0], src[1]);
771 break;
772 case BRW_OPCODE_XOR:
773 brw_XOR(p, dst, src[0], src[1]);
774 break;
775 case BRW_OPCODE_NOT:
776 brw_NOT(p, dst, src[0]);
777 break;
778 case BRW_OPCODE_ASR:
779 brw_ASR(p, dst, src[0], src[1]);
780 break;
781 case BRW_OPCODE_SHR:
782 brw_SHR(p, dst, src[0], src[1]);
783 break;
784 case BRW_OPCODE_SHL:
785 brw_SHL(p, dst, src[0], src[1]);
786 break;
787
788 case BRW_OPCODE_CMP:
789 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
790 break;
791 case BRW_OPCODE_SEL:
792 brw_SEL(p, dst, src[0], src[1]);
793 break;
794
795 case BRW_OPCODE_DPH:
796 brw_DPH(p, dst, src[0], src[1]);
797 break;
798
799 case BRW_OPCODE_DP4:
800 brw_DP4(p, dst, src[0], src[1]);
801 break;
802
803 case BRW_OPCODE_DP3:
804 brw_DP3(p, dst, src[0], src[1]);
805 break;
806
807 case BRW_OPCODE_DP2:
808 brw_DP2(p, dst, src[0], src[1]);
809 break;
810
811 case BRW_OPCODE_IF:
812 if (inst->src[0].file != BAD_FILE) {
813 /* The instruction has an embedded compare (only allowed on gen6) */
814 assert(intel->gen == 6);
815 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
816 } else {
817 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
818 brw_inst->header.predicate_control = inst->predicate;
819 }
820 break;
821
822 case BRW_OPCODE_ELSE:
823 brw_ELSE(p);
824 break;
825 case BRW_OPCODE_ENDIF:
826 brw_ENDIF(p);
827 break;
828
829 case BRW_OPCODE_DO:
830 brw_DO(p, BRW_EXECUTE_8);
831 break;
832
833 case BRW_OPCODE_BREAK:
834 brw_BREAK(p);
835 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
836 break;
837 case BRW_OPCODE_CONTINUE:
838 /* FINISHME: We need to write the loop instruction support still. */
839 if (intel->gen >= 6)
840 gen6_CONT(p);
841 else
842 brw_CONT(p);
843 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
844 break;
845
846 case BRW_OPCODE_WHILE:
847 brw_WHILE(p);
848 break;
849
850 default:
851 generate_vs_instruction(inst, dst, src);
852 break;
853 }
854
855 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
856 brw_dump_compile(p, stdout,
857 last_native_insn_offset, p->next_insn_offset);
858 }
859
860 last_native_insn_offset = p->next_insn_offset;
861 }
862
863 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
864 printf("\n");
865 }
866
867 brw_set_uip_jip(p);
868
869 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
870 * emit issues, it doesn't get the jump distances into the output,
871 * which is often something we want to debug. So this is here in
872 * case you're doing that.
873 */
874 if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
875 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
876 }
877 }
878
879 const unsigned *
880 vec4_generator::generate_assembly(exec_list *instructions,
881 unsigned *assembly_size)
882 {
883 brw_set_access_mode(p, BRW_ALIGN_16);
884 generate_code(instructions);
885 return brw_get_program(p, assembly_size);
886 }
887
888 } /* namespace brw */