1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
35 vec4_instruction::get_dst(void)
37 struct brw_reg brw_reg
;
41 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
42 brw_reg
= retype(brw_reg
, dst
.type
);
43 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
47 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
48 brw_reg
= retype(brw_reg
, dst
.type
);
49 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
53 brw_reg
= dst
.fixed_hw_reg
;
57 brw_reg
= brw_null_reg();
61 assert(!"not reached");
62 brw_reg
= brw_null_reg();
69 vec4_instruction::get_src(int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
96 assert(!"not reached");
97 brw_reg
= brw_null_reg();
103 brw_reg
= stride(brw_vec4_grf(1 + (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
104 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
106 brw_reg
= retype(brw_reg
, src
[i
].type
);
107 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
109 brw_reg
= brw_abs(brw_reg
);
111 brw_reg
= negate(brw_reg
);
113 /* This should have been moved to pull constants. */
114 assert(!src
[i
].reladdr
);
118 brw_reg
= src
[i
].fixed_hw_reg
;
122 /* Probably unused. */
123 brw_reg
= brw_null_reg();
127 assert(!"not reached");
128 brw_reg
= brw_null_reg();
136 vec4_visitor::generate_math1_gen4(vec4_instruction
*inst
,
142 brw_math_function(inst
->opcode
),
145 BRW_MATH_DATA_VECTOR
,
146 BRW_MATH_PRECISION_FULL
);
150 check_gen6_math_src_arg(struct brw_reg src
)
152 /* Source swizzles are ignored. */
155 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
159 vec4_visitor::generate_math1_gen6(vec4_instruction
*inst
,
163 /* Can't do writemask because math can't be align16. */
164 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
165 check_gen6_math_src_arg(src
);
167 brw_set_access_mode(p
, BRW_ALIGN_1
);
170 brw_math_function(inst
->opcode
),
173 BRW_MATH_DATA_SCALAR
,
174 BRW_MATH_PRECISION_FULL
);
175 brw_set_access_mode(p
, BRW_ALIGN_16
);
179 vec4_visitor::generate_math2_gen7(vec4_instruction
*inst
,
186 brw_math_function(inst
->opcode
),
191 vec4_visitor::generate_math2_gen6(vec4_instruction
*inst
,
196 /* Can't do writemask because math can't be align16. */
197 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
198 /* Source swizzles are ignored. */
199 check_gen6_math_src_arg(src0
);
200 check_gen6_math_src_arg(src1
);
202 brw_set_access_mode(p
, BRW_ALIGN_1
);
205 brw_math_function(inst
->opcode
),
207 brw_set_access_mode(p
, BRW_ALIGN_16
);
211 vec4_visitor::generate_math2_gen4(vec4_instruction
*inst
,
216 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
219 * "Operand0[7]. For the INT DIV functions, this operand is the
222 * "Operand1[7]. For the INT DIV functions, this operand is the
225 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
226 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
227 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
229 brw_push_insn_state(p
);
230 brw_set_saturate(p
, false);
231 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
232 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
233 brw_pop_insn_state(p
);
237 brw_math_function(inst
->opcode
),
240 BRW_MATH_DATA_VECTOR
,
241 BRW_MATH_PRECISION_FULL
);
245 vec4_visitor::generate_tex(vec4_instruction
*inst
,
251 if (intel
->gen
>= 5) {
252 switch (inst
->opcode
) {
253 case SHADER_OPCODE_TEX
:
254 case SHADER_OPCODE_TXL
:
255 if (inst
->shadow_compare
) {
256 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
258 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
261 case SHADER_OPCODE_TXD
:
262 /* There is no sample_d_c message; comparisons are done manually. */
263 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
265 case SHADER_OPCODE_TXF
:
266 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
268 case SHADER_OPCODE_TXS
:
269 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
272 assert(!"should not get here: invalid VS texture opcode");
276 switch (inst
->opcode
) {
277 case SHADER_OPCODE_TEX
:
278 case SHADER_OPCODE_TXL
:
279 if (inst
->shadow_compare
) {
280 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
281 assert(inst
->mlen
== 3);
283 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
284 assert(inst
->mlen
== 2);
287 case SHADER_OPCODE_TXD
:
288 /* There is no sample_d_c message; comparisons are done manually. */
289 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
290 assert(inst
->mlen
== 4);
292 case SHADER_OPCODE_TXF
:
293 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
294 assert(inst
->mlen
== 2);
296 case SHADER_OPCODE_TXS
:
297 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
298 assert(inst
->mlen
== 2);
301 assert(!"should not get here: invalid VS texture opcode");
306 assert(msg_type
!= -1);
308 /* Load the message header if present. If there's a texture offset, we need
309 * to set it up explicitly and load the offset bitfield. Otherwise, we can
310 * use an implied move from g0 to the first message register.
312 if (inst
->texture_offset
) {
313 /* Explicitly set up the message header by copying g0 to the MRF. */
314 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
315 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
317 /* Then set the offset bits in DWord 2. */
318 brw_set_access_mode(p
, BRW_ALIGN_1
);
320 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, inst
->base_mrf
, 2),
321 BRW_REGISTER_TYPE_UD
),
322 brw_imm_uw(inst
->texture_offset
));
323 brw_set_access_mode(p
, BRW_ALIGN_16
);
324 } else if (inst
->header_present
) {
325 /* Set up an implied move from g0 to the MRF. */
326 src
= brw_vec8_grf(0, 0);
329 uint32_t return_format
;
332 case BRW_REGISTER_TYPE_D
:
333 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
335 case BRW_REGISTER_TYPE_UD
:
336 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
339 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
347 SURF_INDEX_VS_TEXTURE(inst
->sampler
),
351 1, /* response length */
353 inst
->header_present
,
354 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
359 vec4_visitor::generate_urb_write(vec4_instruction
*inst
)
362 brw_null_reg(), /* dest */
363 inst
->base_mrf
, /* starting mrf reg nr */
364 brw_vec8_grf(0, 0), /* src */
365 false, /* allocate */
368 0, /* response len */
370 inst
->eot
, /* writes complete */
371 inst
->offset
, /* urb destination offset */
372 BRW_URB_SWIZZLE_INTERLEAVE
);
376 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1
,
377 struct brw_reg index
)
379 int second_vertex_offset
;
382 second_vertex_offset
= 1;
384 second_vertex_offset
= 16;
386 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
388 /* Set up M1 (message payload). Only the block offsets in M1.0 and
389 * M1.4 are used, and the rest are ignored.
391 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
392 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
393 struct brw_reg index_0
= suboffset(vec1(index
), 0);
394 struct brw_reg index_4
= suboffset(vec1(index
), 4);
396 brw_push_insn_state(p
);
397 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
398 brw_set_access_mode(p
, BRW_ALIGN_1
);
400 brw_MOV(p
, m1_0
, index_0
);
402 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
403 index_4
.dw1
.ud
+= second_vertex_offset
;
404 brw_MOV(p
, m1_4
, index_4
);
406 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
409 brw_pop_insn_state(p
);
413 vec4_visitor::generate_scratch_read(vec4_instruction
*inst
,
415 struct brw_reg index
)
417 struct brw_reg header
= brw_vec8_grf(0, 0);
419 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
421 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
427 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
428 else if (intel
->gen
== 5 || intel
->is_g4x
)
429 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
431 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
433 /* Each of the 8 channel enables is considered for whether each
436 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
437 brw_set_dest(p
, send
, dst
);
438 brw_set_src0(p
, send
, header
);
440 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
441 brw_set_dp_read_message(p
, send
,
442 255, /* binding table index: stateless access */
443 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
445 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
451 vec4_visitor::generate_scratch_write(vec4_instruction
*inst
,
454 struct brw_reg index
)
456 struct brw_reg header
= brw_vec8_grf(0, 0);
459 /* If the instruction is predicated, we'll predicate the send, not
462 brw_set_predicate_control(p
, false);
464 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
466 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
470 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
471 retype(src
, BRW_REGISTER_TYPE_D
));
476 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
477 else if (intel
->gen
== 6)
478 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
480 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
482 brw_set_predicate_control(p
, inst
->predicate
);
484 /* Pre-gen6, we have to specify write commits to ensure ordering
485 * between reads and writes within a thread. Afterwards, that's
486 * guaranteed and write commits only matter for inter-thread
489 if (intel
->gen
>= 6) {
490 write_commit
= false;
492 /* The visitor set up our destination register to be g0. This
493 * means that when the next read comes along, we will end up
494 * reading from g0 and causing a block on the write commit. For
495 * write-after-read, we are relying on the value of the previous
496 * read being used (and thus blocking on completion) before our
497 * write is executed. This means we have to be careful in
498 * instruction scheduling to not violate this assumption.
503 /* Each of the 8 channel enables is considered for whether each
506 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
507 brw_set_dest(p
, send
, dst
);
508 brw_set_src0(p
, send
, header
);
510 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
511 brw_set_dp_write_message(p
, send
,
512 255, /* binding table index: stateless access */
513 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
516 true, /* header present */
517 false, /* not a render target write */
518 write_commit
, /* rlen */
524 vec4_visitor::generate_pull_constant_load(vec4_instruction
*inst
,
526 struct brw_reg index
,
527 struct brw_reg offset
)
529 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
530 index
.type
== BRW_REGISTER_TYPE_UD
);
531 uint32_t surf_index
= index
.dw1
.ud
;
533 if (intel
->gen
== 7) {
534 gen6_resolve_implied_move(p
, &offset
, inst
->base_mrf
);
535 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
536 brw_set_dest(p
, insn
, dst
);
537 brw_set_src0(p
, insn
, offset
);
538 brw_set_sampler_message(p
, insn
,
540 0, /* LD message ignores sampler unit */
541 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
544 false, /* no header */
545 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
550 struct brw_reg header
= brw_vec8_grf(0, 0);
552 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
554 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
560 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
561 else if (intel
->gen
== 5 || intel
->is_g4x
)
562 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
564 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
566 /* Each of the 8 channel enables is considered for whether each
569 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
570 brw_set_dest(p
, send
, dst
);
571 brw_set_src0(p
, send
, header
);
573 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
574 brw_set_dp_read_message(p
, send
,
576 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
578 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
584 vec4_visitor::generate_vs_instruction(vec4_instruction
*instruction
,
588 vec4_instruction
*inst
= (vec4_instruction
*)instruction
;
590 switch (inst
->opcode
) {
591 case SHADER_OPCODE_RCP
:
592 case SHADER_OPCODE_RSQ
:
593 case SHADER_OPCODE_SQRT
:
594 case SHADER_OPCODE_EXP2
:
595 case SHADER_OPCODE_LOG2
:
596 case SHADER_OPCODE_SIN
:
597 case SHADER_OPCODE_COS
:
598 if (intel
->gen
== 6) {
599 generate_math1_gen6(inst
, dst
, src
[0]);
601 /* Also works for Gen7. */
602 generate_math1_gen4(inst
, dst
, src
[0]);
606 case SHADER_OPCODE_POW
:
607 case SHADER_OPCODE_INT_QUOTIENT
:
608 case SHADER_OPCODE_INT_REMAINDER
:
609 if (intel
->gen
>= 7) {
610 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
611 } else if (intel
->gen
== 6) {
612 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
614 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
618 case SHADER_OPCODE_TEX
:
619 case SHADER_OPCODE_TXD
:
620 case SHADER_OPCODE_TXF
:
621 case SHADER_OPCODE_TXL
:
622 case SHADER_OPCODE_TXS
:
623 generate_tex(inst
, dst
, src
[0]);
626 case VS_OPCODE_URB_WRITE
:
627 generate_urb_write(inst
);
630 case VS_OPCODE_SCRATCH_READ
:
631 generate_scratch_read(inst
, dst
, src
[0]);
634 case VS_OPCODE_SCRATCH_WRITE
:
635 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
638 case VS_OPCODE_PULL_CONSTANT_LOAD
:
639 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
643 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
644 fail("unsupported opcode in `%s' in VS\n",
645 opcode_descs
[inst
->opcode
].name
);
647 fail("Unsupported opcode %d in VS", inst
->opcode
);
653 vec4_visitor::generate_code()
655 int last_native_insn_offset
= 0;
656 const char *last_annotation_string
= NULL
;
657 const void *last_annotation_ir
= NULL
;
659 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
661 printf("Native code for vertex shader %d:\n", prog
->Name
);
663 printf("Native code for vertex program %d:\n", c
->vp
->program
.Base
.Id
);
667 foreach_list(node
, &this->instructions
) {
668 vec4_instruction
*inst
= (vec4_instruction
*)node
;
669 struct brw_reg src
[3], dst
;
671 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
672 if (last_annotation_ir
!= inst
->ir
) {
673 last_annotation_ir
= inst
->ir
;
674 if (last_annotation_ir
) {
677 ((ir_instruction
*) last_annotation_ir
)->print();
679 const prog_instruction
*vpi
;
680 vpi
= (const prog_instruction
*) inst
->ir
;
681 printf("%d: ", (int)(vpi
- vp
->Base
.Instructions
));
682 _mesa_fprint_instruction_opt(stdout
, vpi
, 0,
683 PROG_PRINT_DEBUG
, NULL
);
688 if (last_annotation_string
!= inst
->annotation
) {
689 last_annotation_string
= inst
->annotation
;
690 if (last_annotation_string
)
691 printf(" %s\n", last_annotation_string
);
695 for (unsigned int i
= 0; i
< 3; i
++) {
696 src
[i
] = inst
->get_src(i
);
698 dst
= inst
->get_dst();
700 brw_set_conditionalmod(p
, inst
->conditional_mod
);
701 brw_set_predicate_control(p
, inst
->predicate
);
702 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
703 brw_set_saturate(p
, inst
->saturate
);
705 switch (inst
->opcode
) {
707 brw_MOV(p
, dst
, src
[0]);
710 brw_ADD(p
, dst
, src
[0], src
[1]);
713 brw_MUL(p
, dst
, src
[0], src
[1]);
715 case BRW_OPCODE_MACH
:
716 brw_set_acc_write_control(p
, 1);
717 brw_MACH(p
, dst
, src
[0], src
[1]);
718 brw_set_acc_write_control(p
, 0);
722 brw_FRC(p
, dst
, src
[0]);
724 case BRW_OPCODE_RNDD
:
725 brw_RNDD(p
, dst
, src
[0]);
727 case BRW_OPCODE_RNDE
:
728 brw_RNDE(p
, dst
, src
[0]);
730 case BRW_OPCODE_RNDZ
:
731 brw_RNDZ(p
, dst
, src
[0]);
735 brw_AND(p
, dst
, src
[0], src
[1]);
738 brw_OR(p
, dst
, src
[0], src
[1]);
741 brw_XOR(p
, dst
, src
[0], src
[1]);
744 brw_NOT(p
, dst
, src
[0]);
747 brw_ASR(p
, dst
, src
[0], src
[1]);
750 brw_SHR(p
, dst
, src
[0], src
[1]);
753 brw_SHL(p
, dst
, src
[0], src
[1]);
757 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
760 brw_SEL(p
, dst
, src
[0], src
[1]);
764 brw_DPH(p
, dst
, src
[0], src
[1]);
768 brw_DP4(p
, dst
, src
[0], src
[1]);
772 brw_DP3(p
, dst
, src
[0], src
[1]);
776 brw_DP2(p
, dst
, src
[0], src
[1]);
780 if (inst
->src
[0].file
!= BAD_FILE
) {
781 /* The instruction has an embedded compare (only allowed on gen6) */
782 assert(intel
->gen
== 6);
783 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
785 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
786 brw_inst
->header
.predicate_control
= inst
->predicate
;
790 case BRW_OPCODE_ELSE
:
793 case BRW_OPCODE_ENDIF
:
798 brw_DO(p
, BRW_EXECUTE_8
);
801 case BRW_OPCODE_BREAK
:
803 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
805 case BRW_OPCODE_CONTINUE
:
806 /* FINISHME: We need to write the loop instruction support still. */
811 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
814 case BRW_OPCODE_WHILE
:
819 generate_vs_instruction(inst
, dst
, src
);
823 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
824 brw_dump_compile(p
, stdout
,
825 last_native_insn_offset
, p
->next_insn_offset
);
828 last_native_insn_offset
= p
->next_insn_offset
;
831 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
837 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
838 * emit issues, it doesn't get the jump distances into the output,
839 * which is often something we want to debug. So this is here in
840 * case you're doing that.
842 if (0 && unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
843 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
847 } /* namespace brw */