src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX + 1];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45       }
  46    }
  47
  48    /* VertexID is stored by the VF as the last vertex element, but we
  49     * don't represent it with a flag in inputs_read, so we call it
  50     * VERT_ATTRIB_MAX.
  51     */
  52    if (prog_data->uses_vertexid) {
  53       attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
  54       nr_attributes++;
  55    }
  56
  57    foreach_list(node, &this->instructions) {
  58       vec4_instruction *inst = (vec4_instruction *)node;
  59
  60       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  61       if (inst->dst.file == ATTR) {
  62          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  63
  64          struct brw_reg reg = brw_vec8_grf(grf, 0);
  65          reg.dw1.bits.writemask = inst->dst.writemask;
  66
  67          inst->dst.file = HW_REG;
  68          inst->dst.fixed_hw_reg = reg;
  69       }
  70
  71       for (int i = 0; i < 3; i++) {
  72          if (inst->src[i].file != ATTR)
  73             continue;
  74
  75          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  76
  77          struct brw_reg reg = brw_vec8_grf(grf, 0);
  78          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  79          reg.type = inst->src[i].type;
  80          if (inst->src[i].abs)
  81             reg = brw_abs(reg);
  82          if (inst->src[i].negate)
  83             reg = negate(reg);
  84
  85          inst->src[i].file = HW_REG;
  86          inst->src[i].fixed_hw_reg = reg;
  87       }
  88    }
  89
  90    /* The BSpec says we always have to read at least one thing from
  91     * the VF, and it appears that the hardware wedges otherwise.
  92     */
  93    if (nr_attributes == 0)
  94       nr_attributes = 1;
  95
  96    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  97
  98    return payload_reg + nr_attributes;
  99 }
 100
 101 int
 102 vec4_visitor::setup_uniforms(int reg)
 103 {
 104    /* The pre-gen6 VS requires that some push constants get loaded no
 105     * matter what, or the GPU would hang.
 106     */
 107    if (intel->gen < 6 && this->uniforms == 0) {
 108       this->uniform_vector_size[this->uniforms] = 1;
 109
 110       for (unsigned int i = 0; i < 4; i++) {
 111          unsigned int slot = this->uniforms * 4 + i;
 112          static float zero = 0.0;
 113          c->prog_data.param[slot] = &zero;
 114       }
 115
 116       this->uniforms++;
 117       reg++;
 118    } else {
 119       reg += ALIGN(uniforms, 2) / 2;
 120    }
 121
 122    c->prog_data.nr_params = this->uniforms * 4;
 123
 124    c->prog_data.curb_read_length = reg - 1;
 125    c->prog_data.uses_new_param_layout = true;
 126
 127    return reg;
 128 }
 129
 130 void
 131 vec4_visitor::setup_payload(void)
 132 {
 133    int reg = 0;
 134
 135    /* The payload always contains important data in g0, which contains
 136     * the URB handles that are passed on to the URB write at the end
 137     * of the thread.  So, we always start push constants at g1.
 138     */
 139    reg++;
 140
 141    reg = setup_uniforms(reg);
 142
 143    reg = setup_attributes(reg);
 144
 145    this->first_non_payload_grf = reg;
 146 }
 147
 148 struct brw_reg
 149 vec4_instruction::get_dst(void)
 150 {
 151    struct brw_reg brw_reg;
 152
 153    switch (dst.file) {
 154    case GRF:
 155       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 156       brw_reg = retype(brw_reg, dst.type);
 157       brw_reg.dw1.bits.writemask = dst.writemask;
 158       break;
 159
 160    case MRF:
 161       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 162       brw_reg = retype(brw_reg, dst.type);
 163       brw_reg.dw1.bits.writemask = dst.writemask;
 164       break;
 165
 166    case HW_REG:
 167       brw_reg = dst.fixed_hw_reg;
 168       break;
 169
 170    case BAD_FILE:
 171       brw_reg = brw_null_reg();
 172       break;
 173
 174    default:
 175       assert(!"not reached");
 176       brw_reg = brw_null_reg();
 177       break;
 178    }
 179    return brw_reg;
 180 }
 181
 182 struct brw_reg
 183 vec4_instruction::get_src(int i)
 184 {
 185    struct brw_reg brw_reg;
 186
 187    switch (src[i].file) {
 188    case GRF:
 189       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 190       brw_reg = retype(brw_reg, src[i].type);
 191       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 192       if (src[i].abs)
 193          brw_reg = brw_abs(brw_reg);
 194       if (src[i].negate)
 195          brw_reg = negate(brw_reg);
 196       break;
 197
 198    case IMM:
 199       switch (src[i].type) {
 200       case BRW_REGISTER_TYPE_F:
 201          brw_reg = brw_imm_f(src[i].imm.f);
 202          break;
 203       case BRW_REGISTER_TYPE_D:
 204          brw_reg = brw_imm_d(src[i].imm.i);
 205          break;
 206       case BRW_REGISTER_TYPE_UD:
 207          brw_reg = brw_imm_ud(src[i].imm.u);
 208          break;
 209       default:
 210          assert(!"not reached");
 211          brw_reg = brw_null_reg();
 212          break;
 213       }
 214       break;
 215
 216    case UNIFORM:
 217       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 218                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 219                        0, 4, 1);
 220       brw_reg = retype(brw_reg, src[i].type);
 221       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 222       if (src[i].abs)
 223          brw_reg = brw_abs(brw_reg);
 224       if (src[i].negate)
 225          brw_reg = negate(brw_reg);
 226
 227       /* This should have been moved to pull constants. */
 228       assert(!src[i].reladdr);
 229       break;
 230
 231    case HW_REG:
 232       brw_reg = src[i].fixed_hw_reg;
 233       break;
 234
 235    case BAD_FILE:
 236       /* Probably unused. */
 237       brw_reg = brw_null_reg();
 238       break;
 239    case ATTR:
 240    default:
 241       assert(!"not reached");
 242       brw_reg = brw_null_reg();
 243       break;
 244    }
 245
 246    return brw_reg;
 247 }
 248
 249 void
 250 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 251                                   struct brw_reg dst,
 252                                   struct brw_reg src)
 253 {
 254    brw_math(p,
 255             dst,
 256             brw_math_function(inst->opcode),
 257             BRW_MATH_SATURATE_NONE,
 258             inst->base_mrf,
 259             src,
 260             BRW_MATH_DATA_VECTOR,
 261             BRW_MATH_PRECISION_FULL);
 262 }
 263
 264 static void
 265 check_gen6_math_src_arg(struct brw_reg src)
 266 {
 267    /* Source swizzles are ignored. */
 268    assert(!src.abs);
 269    assert(!src.negate);
 270    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 271 }
 272
 273 void
 274 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 275                                   struct brw_reg dst,
 276                                   struct brw_reg src)
 277 {
 278    /* Can't do writemask because math can't be align16. */
 279    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 280    check_gen6_math_src_arg(src);
 281
 282    brw_set_access_mode(p, BRW_ALIGN_1);
 283    brw_math(p,
 284             dst,
 285             brw_math_function(inst->opcode),
 286             BRW_MATH_SATURATE_NONE,
 287             inst->base_mrf,
 288             src,
 289             BRW_MATH_DATA_SCALAR,
 290             BRW_MATH_PRECISION_FULL);
 291    brw_set_access_mode(p, BRW_ALIGN_16);
 292 }
 293
 294 void
 295 vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
 296                                   struct brw_reg dst,
 297                                   struct brw_reg src0,
 298                                   struct brw_reg src1)
 299 {
 300    brw_math2(p,
 301              dst,
 302              brw_math_function(inst->opcode),
 303              src0, src1);
 304 }
 305
 306 void
 307 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 308                                   struct brw_reg dst,
 309                                   struct brw_reg src0,
 310                                   struct brw_reg src1)
 311 {
 312    /* Can't do writemask because math can't be align16. */
 313    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 314    /* Source swizzles are ignored. */
 315    check_gen6_math_src_arg(src0);
 316    check_gen6_math_src_arg(src1);
 317
 318    brw_set_access_mode(p, BRW_ALIGN_1);
 319    brw_math2(p,
 320              dst,
 321              brw_math_function(inst->opcode),
 322              src0, src1);
 323    brw_set_access_mode(p, BRW_ALIGN_16);
 324 }
 325
 326 void
 327 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 328                                   struct brw_reg dst,
 329                                   struct brw_reg src0,
 330                                   struct brw_reg src1)
 331 {
 332    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 333     * "Message Payload":
 334     *
 335     * "Operand0[7].  For the INT DIV functions, this operand is the
 336     *  denominator."
 337     *  ...
 338     * "Operand1[7].  For the INT DIV functions, this operand is the
 339     *  numerator."
 340     */
 341    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 342    struct brw_reg &op0 = is_int_div ? src1 : src0;
 343    struct brw_reg &op1 = is_int_div ? src0 : src1;
 344
 345    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 346
 347    brw_math(p,
 348             dst,
 349             brw_math_function(inst->opcode),
 350             BRW_MATH_SATURATE_NONE,
 351             inst->base_mrf,
 352             op0,
 353             BRW_MATH_DATA_VECTOR,
 354             BRW_MATH_PRECISION_FULL);
 355 }
 356
 357 void
 358 vec4_visitor::generate_tex(vec4_instruction *inst,
 359                            struct brw_reg dst,
 360                            struct brw_reg src)
 361 {
 362    int msg_type = -1;
 363
 364    if (intel->gen >= 5) {
 365       switch (inst->opcode) {
 366       case SHADER_OPCODE_TEX:
 367       case SHADER_OPCODE_TXL:
 368          if (inst->shadow_compare) {
 369             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
 370          } else {
 371             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
 372          }
 373          break;
 374       case SHADER_OPCODE_TXD:
 375          /* There is no sample_d_c message; comparisons are done manually. */
 376          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
 377          break;
 378       case SHADER_OPCODE_TXF:
 379          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 380          break;
 381       case SHADER_OPCODE_TXS:
 382          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 383          break;
 384       default:
 385          assert(!"should not get here: invalid VS texture opcode");
 386          break;
 387       }
 388    } else {
 389       switch (inst->opcode) {
 390       case SHADER_OPCODE_TEX:
 391       case SHADER_OPCODE_TXL:
 392          if (inst->shadow_compare) {
 393             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
 394             assert(inst->mlen == 3);
 395          } else {
 396             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
 397             assert(inst->mlen == 2);
 398          }
 399          break;
 400       case SHADER_OPCODE_TXD:
 401          /* There is no sample_d_c message; comparisons are done manually. */
 402          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
 403          assert(inst->mlen == 4);
 404          break;
 405       case SHADER_OPCODE_TXF:
 406          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
 407          assert(inst->mlen == 2);
 408          break;
 409       case SHADER_OPCODE_TXS:
 410          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
 411          assert(inst->mlen == 2);
 412          break;
 413       default:
 414          assert(!"should not get here: invalid VS texture opcode");
 415          break;
 416       }
 417    }
 418
 419    assert(msg_type != -1);
 420
 421    if (inst->header_present) {
 422       /* Set up an implied move from g0 to the MRF. */
 423       src = brw_vec8_grf(0, 0);
 424    }
 425
 426    uint32_t return_format;
 427
 428    switch (dst.type) {
 429    case BRW_REGISTER_TYPE_D:
 430       return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
 431       break;
 432    case BRW_REGISTER_TYPE_UD:
 433       return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
 434       break;
 435    default:
 436       return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
 437       break;
 438    }
 439
 440    brw_SAMPLE(p,
 441               dst,
 442               inst->base_mrf,
 443               src,
 444               SURF_INDEX_TEXTURE(inst->sampler),
 445               inst->sampler,
 446               WRITEMASK_XYZW,
 447               msg_type,
 448               1, /* response length */
 449               inst->mlen,
 450               inst->header_present,
 451               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 452               return_format);
 453 }
 454
 455 void
 456 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 457 {
 458    brw_urb_WRITE(p,
 459                  brw_null_reg(), /* dest */
 460                  inst->base_mrf, /* starting mrf reg nr */
 461                  brw_vec8_grf(0, 0), /* src */
 462                  false,         /* allocate */
 463                  true,          /* used */
 464                  inst->mlen,
 465                  0,             /* response len */
 466                  inst->eot,     /* eot */
 467                  inst->eot,     /* writes complete */
 468                  inst->offset,  /* urb destination offset */
 469                  BRW_URB_SWIZZLE_INTERLEAVE);
 470 }
 471
 472 void
 473 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 474                                                 struct brw_reg index)
 475 {
 476    int second_vertex_offset;
 477
 478    if (intel->gen >= 6)
 479       second_vertex_offset = 1;
 480    else
 481       second_vertex_offset = 16;
 482
 483    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 484
 485    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 486     * M1.4 are used, and the rest are ignored.
 487     */
 488    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 489    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 490    struct brw_reg index_0 = suboffset(vec1(index), 0);
 491    struct brw_reg index_4 = suboffset(vec1(index), 4);
 492
 493    brw_push_insn_state(p);
 494    brw_set_mask_control(p, BRW_MASK_DISABLE);
 495    brw_set_access_mode(p, BRW_ALIGN_1);
 496
 497    brw_MOV(p, m1_0, index_0);
 498
 499    brw_set_predicate_inverse(p, true);
 500    if (index.file == BRW_IMMEDIATE_VALUE) {
 501       index_4.dw1.ud += second_vertex_offset;
 502       brw_MOV(p, m1_4, index_4);
 503    } else {
 504       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 505    }
 506
 507    brw_pop_insn_state(p);
 508 }
 509
 510 void
 511 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 512                                     struct brw_reg dst,
 513                                     struct brw_reg index)
 514 {
 515    struct brw_reg header = brw_vec8_grf(0, 0);
 516
 517    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 518
 519    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 520                                      index);
 521
 522    uint32_t msg_type;
 523
 524    if (intel->gen >= 6)
 525       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 526    else if (intel->gen == 5 || intel->is_g4x)
 527       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 528    else
 529       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 530
 531    /* Each of the 8 channel enables is considered for whether each
 532     * dword is written.
 533     */
 534    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 535    brw_set_dest(p, send, dst);
 536    brw_set_src0(p, send, header);
 537    if (intel->gen < 6)
 538       send->header.destreg__conditionalmod = inst->base_mrf;
 539    brw_set_dp_read_message(p, send,
 540                            255, /* binding table index: stateless access */
 541                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 542                            msg_type,
 543                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 544                            2, /* mlen */
 545                            1 /* rlen */);
 546 }
 547
 548 void
 549 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 550                                      struct brw_reg dst,
 551                                      struct brw_reg src,
 552                                      struct brw_reg index)
 553 {
 554    struct brw_reg header = brw_vec8_grf(0, 0);
 555    bool write_commit;
 556
 557    /* If the instruction is predicated, we'll predicate the send, not
 558     * the header setup.
 559     */
 560    brw_set_predicate_control(p, false);
 561
 562    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 563
 564    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 565                                      index);
 566
 567    brw_MOV(p,
 568            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 569            retype(src, BRW_REGISTER_TYPE_D));
 570
 571    uint32_t msg_type;
 572
 573    if (intel->gen >= 7)
 574       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 575    else if (intel->gen == 6)
 576       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 577    else
 578       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 579
 580    brw_set_predicate_control(p, inst->predicate);
 581
 582    /* Pre-gen6, we have to specify write commits to ensure ordering
 583     * between reads and writes within a thread.  Afterwards, that's
 584     * guaranteed and write commits only matter for inter-thread
 585     * synchronization.
 586     */
 587    if (intel->gen >= 6) {
 588       write_commit = false;
 589    } else {
 590       /* The visitor set up our destination register to be g0.  This
 591        * means that when the next read comes along, we will end up
 592        * reading from g0 and causing a block on the write commit.  For
 593        * write-after-read, we are relying on the value of the previous
 594        * read being used (and thus blocking on completion) before our
 595        * write is executed.  This means we have to be careful in
 596        * instruction scheduling to not violate this assumption.
 597        */
 598       write_commit = true;
 599    }
 600
 601    /* Each of the 8 channel enables is considered for whether each
 602     * dword is written.
 603     */
 604    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 605    brw_set_dest(p, send, dst);
 606    brw_set_src0(p, send, header);
 607    if (intel->gen < 6)
 608       send->header.destreg__conditionalmod = inst->base_mrf;
 609    brw_set_dp_write_message(p, send,
 610                             255, /* binding table index: stateless access */
 611                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 612                             msg_type,
 613                             3, /* mlen */
 614                             true, /* header present */
 615                             false, /* not a render target write */
 616                             write_commit, /* rlen */
 617                             false, /* eot */
 618                             write_commit);
 619 }
 620
 621 void
 622 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 623                                           struct brw_reg dst,
 624                                           struct brw_reg index)
 625 {
 626    struct brw_reg header = brw_vec8_grf(0, 0);
 627
 628    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 629
 630    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 631            index);
 632
 633    uint32_t msg_type;
 634
 635    if (intel->gen >= 6)
 636       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 637    else if (intel->gen == 5 || intel->is_g4x)
 638       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 639    else
 640       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 641
 642    /* Each of the 8 channel enables is considered for whether each
 643     * dword is written.
 644     */
 645    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 646    brw_set_dest(p, send, dst);
 647    brw_set_src0(p, send, header);
 648    if (intel->gen < 6)
 649       send->header.destreg__conditionalmod = inst->base_mrf;
 650    brw_set_dp_read_message(p, send,
 651                            SURF_INDEX_VERT_CONST_BUFFER,
 652                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 653                            msg_type,
 654                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 655                            2, /* mlen */
 656                            1 /* rlen */);
 657 }
 658
 659 void
 660 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 661                                       struct brw_reg dst,
 662                                       struct brw_reg *src)
 663 {
 664    vec4_instruction *inst = (vec4_instruction *)instruction;
 665
 666    switch (inst->opcode) {
 667    case SHADER_OPCODE_RCP:
 668    case SHADER_OPCODE_RSQ:
 669    case SHADER_OPCODE_SQRT:
 670    case SHADER_OPCODE_EXP2:
 671    case SHADER_OPCODE_LOG2:
 672    case SHADER_OPCODE_SIN:
 673    case SHADER_OPCODE_COS:
 674       if (intel->gen == 6) {
 675          generate_math1_gen6(inst, dst, src[0]);
 676       } else {
 677          /* Also works for Gen7. */
 678          generate_math1_gen4(inst, dst, src[0]);
 679       }
 680       break;
 681
 682    case SHADER_OPCODE_POW:
 683    case SHADER_OPCODE_INT_QUOTIENT:
 684    case SHADER_OPCODE_INT_REMAINDER:
 685       if (intel->gen >= 7) {
 686          generate_math2_gen7(inst, dst, src[0], src[1]);
 687       } else if (intel->gen == 6) {
 688          generate_math2_gen6(inst, dst, src[0], src[1]);
 689       } else {
 690          generate_math2_gen4(inst, dst, src[0], src[1]);
 691       }
 692       break;
 693
 694    case SHADER_OPCODE_TEX:
 695    case SHADER_OPCODE_TXD:
 696    case SHADER_OPCODE_TXF:
 697    case SHADER_OPCODE_TXL:
 698    case SHADER_OPCODE_TXS:
 699       generate_tex(inst, dst, src[0]);
 700       break;
 701
 702    case VS_OPCODE_URB_WRITE:
 703       generate_urb_write(inst);
 704       break;
 705
 706    case VS_OPCODE_SCRATCH_READ:
 707       generate_scratch_read(inst, dst, src[0]);
 708       break;
 709
 710    case VS_OPCODE_SCRATCH_WRITE:
 711       generate_scratch_write(inst, dst, src[0], src[1]);
 712       break;
 713
 714    case VS_OPCODE_PULL_CONSTANT_LOAD:
 715       generate_pull_constant_load(inst, dst, src[0]);
 716       break;
 717
 718    default:
 719       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 720          fail("unsupported opcode in `%s' in VS\n",
 721               brw_opcodes[inst->opcode].name);
 722       } else {
 723          fail("Unsupported opcode %d in VS", inst->opcode);
 724       }
 725    }
 726 }
 727
 728 bool
 729 vec4_visitor::run()
 730 {
 731    if (c->key.userclip_active && !c->key.uses_clip_distance)
 732       setup_uniform_clipplane_values();
 733
 734    /* Generate VS IR for main().  (the visitor only descends into
 735     * functions called "main").
 736     */
 737    visit_instructions(shader->ir);
 738
 739    emit_urb_writes();
 740
 741    /* Before any optimization, push array accesses out to scratch
 742     * space where we need them to be.  This pass may allocate new
 743     * virtual GRFs, so we want to do it early.  It also makes sure
 744     * that we have reladdr computations available for CSE, since we'll
 745     * often do repeated subexpressions for those.
 746     */
 747    move_grf_array_access_to_scratch();
 748    move_uniform_array_access_to_pull_constants();
 749    pack_uniform_registers();
 750    move_push_constants_to_pull_constants();
 751
 752    bool progress;
 753    do {
 754       progress = false;
 755       progress = dead_code_eliminate() || progress;
 756       progress = opt_copy_propagation() || progress;
 757       progress = opt_algebraic() || progress;
 758       progress = opt_compute_to_mrf() || progress;
 759    } while (progress);
 760
 761
 762    if (failed)
 763       return false;
 764
 765    setup_payload();
 766    reg_allocate();
 767
 768    if (failed)
 769       return false;
 770
 771    brw_set_access_mode(p, BRW_ALIGN_16);
 772
 773    generate_code();
 774
 775    return !failed;
 776 }
 777
 778 void
 779 vec4_visitor::generate_code()
 780 {
 781    int last_native_inst = 0;
 782    const char *last_annotation_string = NULL;
 783    ir_instruction *last_annotation_ir = NULL;
 784
 785    int loop_stack_array_size = 16;
 786    int loop_stack_depth = 0;
 787    brw_instruction **loop_stack =
 788       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 789    int *if_depth_in_loop =
 790       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 791
 792
 793    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 794       printf("Native code for vertex shader %d:\n", prog->Name);
 795    }
 796
 797    foreach_list(node, &this->instructions) {
 798       vec4_instruction *inst = (vec4_instruction *)node;
 799       struct brw_reg src[3], dst;
 800
 801       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 802          if (last_annotation_ir != inst->ir) {
 803             last_annotation_ir = inst->ir;
 804             if (last_annotation_ir) {
 805                printf("   ");
 806                last_annotation_ir->print();
 807                printf("\n");
 808             }
 809          }
 810          if (last_annotation_string != inst->annotation) {
 811             last_annotation_string = inst->annotation;
 812             if (last_annotation_string)
 813                printf("   %s\n", last_annotation_string);
 814          }
 815       }
 816
 817       for (unsigned int i = 0; i < 3; i++) {
 818          src[i] = inst->get_src(i);
 819       }
 820       dst = inst->get_dst();
 821
 822       brw_set_conditionalmod(p, inst->conditional_mod);
 823       brw_set_predicate_control(p, inst->predicate);
 824       brw_set_predicate_inverse(p, inst->predicate_inverse);
 825       brw_set_saturate(p, inst->saturate);
 826
 827       switch (inst->opcode) {
 828       case BRW_OPCODE_MOV:
 829          brw_MOV(p, dst, src[0]);
 830          break;
 831       case BRW_OPCODE_ADD:
 832          brw_ADD(p, dst, src[0], src[1]);
 833          break;
 834       case BRW_OPCODE_MUL:
 835          brw_MUL(p, dst, src[0], src[1]);
 836          break;
 837       case BRW_OPCODE_MACH:
 838          brw_set_acc_write_control(p, 1);
 839          brw_MACH(p, dst, src[0], src[1]);
 840          brw_set_acc_write_control(p, 0);
 841          break;
 842
 843       case BRW_OPCODE_FRC:
 844          brw_FRC(p, dst, src[0]);
 845          break;
 846       case BRW_OPCODE_RNDD:
 847          brw_RNDD(p, dst, src[0]);
 848          break;
 849       case BRW_OPCODE_RNDE:
 850          brw_RNDE(p, dst, src[0]);
 851          break;
 852       case BRW_OPCODE_RNDZ:
 853          brw_RNDZ(p, dst, src[0]);
 854          break;
 855
 856       case BRW_OPCODE_AND:
 857          brw_AND(p, dst, src[0], src[1]);
 858          break;
 859       case BRW_OPCODE_OR:
 860          brw_OR(p, dst, src[0], src[1]);
 861          break;
 862       case BRW_OPCODE_XOR:
 863          brw_XOR(p, dst, src[0], src[1]);
 864          break;
 865       case BRW_OPCODE_NOT:
 866          brw_NOT(p, dst, src[0]);
 867          break;
 868       case BRW_OPCODE_ASR:
 869          brw_ASR(p, dst, src[0], src[1]);
 870          break;
 871       case BRW_OPCODE_SHR:
 872          brw_SHR(p, dst, src[0], src[1]);
 873          break;
 874       case BRW_OPCODE_SHL:
 875          brw_SHL(p, dst, src[0], src[1]);
 876          break;
 877
 878       case BRW_OPCODE_CMP:
 879          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 880          break;
 881       case BRW_OPCODE_SEL:
 882          brw_SEL(p, dst, src[0], src[1]);
 883          break;
 884
 885       case BRW_OPCODE_DP4:
 886          brw_DP4(p, dst, src[0], src[1]);
 887          break;
 888
 889       case BRW_OPCODE_DP3:
 890          brw_DP3(p, dst, src[0], src[1]);
 891          break;
 892
 893       case BRW_OPCODE_DP2:
 894          brw_DP2(p, dst, src[0], src[1]);
 895          break;
 896
 897       case BRW_OPCODE_IF:
 898          if (inst->src[0].file != BAD_FILE) {
 899             /* The instruction has an embedded compare (only allowed on gen6) */
 900             assert(intel->gen == 6);
 901             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 902          } else {
 903             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 904             brw_inst->header.predicate_control = inst->predicate;
 905          }
 906          if_depth_in_loop[loop_stack_depth]++;
 907          break;
 908
 909       case BRW_OPCODE_ELSE:
 910          brw_ELSE(p);
 911          break;
 912       case BRW_OPCODE_ENDIF:
 913          brw_ENDIF(p);
 914          if_depth_in_loop[loop_stack_depth]--;
 915          break;
 916
 917       case BRW_OPCODE_DO:
 918          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 919          if (loop_stack_array_size <= loop_stack_depth) {
 920             loop_stack_array_size *= 2;
 921             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 922                                   loop_stack_array_size);
 923             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 924                                         loop_stack_array_size);
 925          }
 926          if_depth_in_loop[loop_stack_depth] = 0;
 927          break;
 928
 929       case BRW_OPCODE_BREAK:
 930          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 931          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 932          break;
 933       case BRW_OPCODE_CONTINUE:
 934          /* FINISHME: We need to write the loop instruction support still. */
 935          if (intel->gen >= 6)
 936             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 937          else
 938             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 939          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 940          break;
 941
 942       case BRW_OPCODE_WHILE: {
 943          struct brw_instruction *inst0, *inst1;
 944          GLuint br = 1;
 945
 946          if (intel->gen >= 5)
 947             br = 2;
 948
 949          assert(loop_stack_depth > 0);
 950          loop_stack_depth--;
 951          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 952          if (intel->gen < 6) {
 953             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 954             while (inst0 > loop_stack[loop_stack_depth]) {
 955                inst0--;
 956                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 957                    inst0->bits3.if_else.jump_count == 0) {
 958                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 959             }
 960                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 961                         inst0->bits3.if_else.jump_count == 0) {
 962                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 963                }
 964             }
 965          }
 966       }
 967          break;
 968
 969       default:
 970          generate_vs_instruction(inst, dst, src);
 971          break;
 972       }
 973
 974       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 975          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 976             if (0) {
 977                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 978                       ((uint32_t *)&p->store[i])[3],
 979                       ((uint32_t *)&p->store[i])[2],
 980                       ((uint32_t *)&p->store[i])[1],
 981                       ((uint32_t *)&p->store[i])[0]);
 982             }
 983             brw_disasm(stdout, &p->store[i], intel->gen);
 984          }
 985       }
 986
 987       last_native_inst = p->nr_insn;
 988    }
 989
 990    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 991       printf("\n");
 992    }
 993
 994    ralloc_free(loop_stack);
 995    ralloc_free(if_depth_in_loop);
 996
 997    brw_set_uip_jip(p);
 998
 999    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1000     * emit issues, it doesn't get the jump distances into the output,
1001     * which is often something we want to debug.  So this is here in
1002     * case you're doing that.
1003     */
1004    if (0) {
1005       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1006          for (unsigned int i = 0; i < p->nr_insn; i++) {
1007             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
1008                    ((uint32_t *)&p->store[i])[3],
1009                    ((uint32_t *)&p->store[i])[2],
1010                    ((uint32_t *)&p->store[i])[1],
1011                    ((uint32_t *)&p->store[i])[0]);
1012             brw_disasm(stdout, &p->store[i], intel->gen);
1013          }
1014       }
1015    }
1016 }
1017
1018 extern "C" {
1019
1020 bool
1021 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
1022 {
1023    if (!prog)
1024       return false;
1025
1026    struct brw_shader *shader =
1027      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
1028    if (!shader)
1029       return false;
1030
1031    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1032       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
1033       _mesa_print_ir(shader->ir, NULL);
1034       printf("\n\n");
1035    }
1036
1037    vec4_visitor v(c, prog, shader);
1038    if (!v.run()) {
1039       prog->LinkStatus = false;
1040       ralloc_strcat(&prog->InfoLog, v.fail_msg);
1041       return false;
1042    }
1043
1044    return true;
1045 }
1046
1047 } /* extern "C" */
1048
1049 } /* namespace brw */