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i915: Remove most of the code under gen >= 4 checks.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct gl_shader_program *shader_prog,
137 struct gl_program *prog,
138 void *mem_ctx,
139 bool debug_flag)
140 : brw(brw), shader_prog(shader_prog), prog(prog), mem_ctx(mem_ctx),
141 debug_flag(debug_flag)
142 {
143 intel = &brw->intel;
144
145 shader = shader_prog ? shader_prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
146
147 p = rzalloc(mem_ctx, struct brw_compile);
148 brw_init_compile(brw, p, mem_ctx);
149 }
150
151 vec4_generator::~vec4_generator()
152 {
153 }
154
155 void
156 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
157 struct brw_reg dst,
158 struct brw_reg src)
159 {
160 brw_math(p,
161 dst,
162 brw_math_function(inst->opcode),
163 inst->base_mrf,
164 src,
165 BRW_MATH_DATA_VECTOR,
166 BRW_MATH_PRECISION_FULL);
167 }
168
169 static void
170 check_gen6_math_src_arg(struct brw_reg src)
171 {
172 /* Source swizzles are ignored. */
173 assert(!src.abs);
174 assert(!src.negate);
175 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
176 }
177
178 void
179 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
180 struct brw_reg dst,
181 struct brw_reg src)
182 {
183 /* Can't do writemask because math can't be align16. */
184 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
185 check_gen6_math_src_arg(src);
186
187 brw_set_access_mode(p, BRW_ALIGN_1);
188 brw_math(p,
189 dst,
190 brw_math_function(inst->opcode),
191 inst->base_mrf,
192 src,
193 BRW_MATH_DATA_SCALAR,
194 BRW_MATH_PRECISION_FULL);
195 brw_set_access_mode(p, BRW_ALIGN_16);
196 }
197
198 void
199 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
200 struct brw_reg dst,
201 struct brw_reg src0,
202 struct brw_reg src1)
203 {
204 brw_math2(p,
205 dst,
206 brw_math_function(inst->opcode),
207 src0, src1);
208 }
209
210 void
211 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
212 struct brw_reg dst,
213 struct brw_reg src0,
214 struct brw_reg src1)
215 {
216 /* Can't do writemask because math can't be align16. */
217 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
218 /* Source swizzles are ignored. */
219 check_gen6_math_src_arg(src0);
220 check_gen6_math_src_arg(src1);
221
222 brw_set_access_mode(p, BRW_ALIGN_1);
223 brw_math2(p,
224 dst,
225 brw_math_function(inst->opcode),
226 src0, src1);
227 brw_set_access_mode(p, BRW_ALIGN_16);
228 }
229
230 void
231 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
232 struct brw_reg dst,
233 struct brw_reg src0,
234 struct brw_reg src1)
235 {
236 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
237 * "Message Payload":
238 *
239 * "Operand0[7]. For the INT DIV functions, this operand is the
240 * denominator."
241 * ...
242 * "Operand1[7]. For the INT DIV functions, this operand is the
243 * numerator."
244 */
245 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
246 struct brw_reg &op0 = is_int_div ? src1 : src0;
247 struct brw_reg &op1 = is_int_div ? src0 : src1;
248
249 brw_push_insn_state(p);
250 brw_set_saturate(p, false);
251 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
252 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
253 brw_pop_insn_state(p);
254
255 brw_math(p,
256 dst,
257 brw_math_function(inst->opcode),
258 inst->base_mrf,
259 op0,
260 BRW_MATH_DATA_VECTOR,
261 BRW_MATH_PRECISION_FULL);
262 }
263
264 void
265 vec4_generator::generate_tex(vec4_instruction *inst,
266 struct brw_reg dst,
267 struct brw_reg src)
268 {
269 int msg_type = -1;
270
271 if (intel->gen >= 5) {
272 switch (inst->opcode) {
273 case SHADER_OPCODE_TEX:
274 case SHADER_OPCODE_TXL:
275 if (inst->shadow_compare) {
276 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
277 } else {
278 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
279 }
280 break;
281 case SHADER_OPCODE_TXD:
282 if (inst->shadow_compare) {
283 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
284 assert(intel->is_haswell);
285 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
286 } else {
287 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
288 }
289 break;
290 case SHADER_OPCODE_TXF:
291 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
292 break;
293 case SHADER_OPCODE_TXF_MS:
294 if (intel->gen >= 7)
295 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
296 else
297 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
298 break;
299 case SHADER_OPCODE_TXS:
300 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
301 break;
302 default:
303 assert(!"should not get here: invalid VS texture opcode");
304 break;
305 }
306 } else {
307 switch (inst->opcode) {
308 case SHADER_OPCODE_TEX:
309 case SHADER_OPCODE_TXL:
310 if (inst->shadow_compare) {
311 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
312 assert(inst->mlen == 3);
313 } else {
314 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
315 assert(inst->mlen == 2);
316 }
317 break;
318 case SHADER_OPCODE_TXD:
319 /* There is no sample_d_c message; comparisons are done manually. */
320 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
321 assert(inst->mlen == 4);
322 break;
323 case SHADER_OPCODE_TXF:
324 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
325 assert(inst->mlen == 2);
326 break;
327 case SHADER_OPCODE_TXS:
328 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
329 assert(inst->mlen == 2);
330 break;
331 default:
332 assert(!"should not get here: invalid VS texture opcode");
333 break;
334 }
335 }
336
337 assert(msg_type != -1);
338
339 /* Load the message header if present. If there's a texture offset, we need
340 * to set it up explicitly and load the offset bitfield. Otherwise, we can
341 * use an implied move from g0 to the first message register.
342 */
343 if (inst->texture_offset) {
344 /* Explicitly set up the message header by copying g0 to the MRF. */
345 brw_push_insn_state(p);
346 brw_set_mask_control(p, BRW_MASK_DISABLE);
347 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
348 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
349
350 /* Then set the offset bits in DWord 2. */
351 brw_set_access_mode(p, BRW_ALIGN_1);
352 brw_MOV(p,
353 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
354 BRW_REGISTER_TYPE_UD),
355 brw_imm_uw(inst->texture_offset));
356 brw_pop_insn_state(p);
357 } else if (inst->header_present) {
358 /* Set up an implied move from g0 to the MRF. */
359 src = brw_vec8_grf(0, 0);
360 }
361
362 uint32_t return_format;
363
364 switch (dst.type) {
365 case BRW_REGISTER_TYPE_D:
366 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
367 break;
368 case BRW_REGISTER_TYPE_UD:
369 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
370 break;
371 default:
372 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
373 break;
374 }
375
376 brw_SAMPLE(p,
377 dst,
378 inst->base_mrf,
379 src,
380 SURF_INDEX_VS_TEXTURE(inst->sampler),
381 inst->sampler,
382 msg_type,
383 1, /* response length */
384 inst->mlen,
385 inst->header_present,
386 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
387 return_format);
388 }
389
390 void
391 vec4_generator::generate_urb_write(vec4_instruction *inst)
392 {
393 brw_urb_WRITE(p,
394 brw_null_reg(), /* dest */
395 inst->base_mrf, /* starting mrf reg nr */
396 brw_vec8_grf(0, 0), /* src */
397 false, /* allocate */
398 true, /* used */
399 inst->mlen,
400 0, /* response len */
401 inst->eot, /* eot */
402 inst->eot, /* writes complete */
403 inst->offset, /* urb destination offset */
404 BRW_URB_SWIZZLE_INTERLEAVE);
405 }
406
407 void
408 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
409 struct brw_reg index)
410 {
411 int second_vertex_offset;
412
413 if (intel->gen >= 6)
414 second_vertex_offset = 1;
415 else
416 second_vertex_offset = 16;
417
418 m1 = retype(m1, BRW_REGISTER_TYPE_D);
419
420 /* Set up M1 (message payload). Only the block offsets in M1.0 and
421 * M1.4 are used, and the rest are ignored.
422 */
423 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
424 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
425 struct brw_reg index_0 = suboffset(vec1(index), 0);
426 struct brw_reg index_4 = suboffset(vec1(index), 4);
427
428 brw_push_insn_state(p);
429 brw_set_mask_control(p, BRW_MASK_DISABLE);
430 brw_set_access_mode(p, BRW_ALIGN_1);
431
432 brw_MOV(p, m1_0, index_0);
433
434 if (index.file == BRW_IMMEDIATE_VALUE) {
435 index_4.dw1.ud += second_vertex_offset;
436 brw_MOV(p, m1_4, index_4);
437 } else {
438 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
439 }
440
441 brw_pop_insn_state(p);
442 }
443
444 void
445 vec4_generator::generate_scratch_read(vec4_instruction *inst,
446 struct brw_reg dst,
447 struct brw_reg index)
448 {
449 struct brw_reg header = brw_vec8_grf(0, 0);
450
451 gen6_resolve_implied_move(p, &header, inst->base_mrf);
452
453 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
454 index);
455
456 uint32_t msg_type;
457
458 if (intel->gen >= 6)
459 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
460 else if (intel->gen == 5 || intel->is_g4x)
461 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
462 else
463 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
464
465 /* Each of the 8 channel enables is considered for whether each
466 * dword is written.
467 */
468 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
469 brw_set_dest(p, send, dst);
470 brw_set_src0(p, send, header);
471 if (intel->gen < 6)
472 send->header.destreg__conditionalmod = inst->base_mrf;
473 brw_set_dp_read_message(p, send,
474 255, /* binding table index: stateless access */
475 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
476 msg_type,
477 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
478 2, /* mlen */
479 true, /* header_present */
480 1 /* rlen */);
481 }
482
483 void
484 vec4_generator::generate_scratch_write(vec4_instruction *inst,
485 struct brw_reg dst,
486 struct brw_reg src,
487 struct brw_reg index)
488 {
489 struct brw_reg header = brw_vec8_grf(0, 0);
490 bool write_commit;
491
492 /* If the instruction is predicated, we'll predicate the send, not
493 * the header setup.
494 */
495 brw_set_predicate_control(p, false);
496
497 gen6_resolve_implied_move(p, &header, inst->base_mrf);
498
499 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
500 index);
501
502 brw_MOV(p,
503 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
504 retype(src, BRW_REGISTER_TYPE_D));
505
506 uint32_t msg_type;
507
508 if (intel->gen >= 7)
509 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
510 else if (intel->gen == 6)
511 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
512 else
513 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
514
515 brw_set_predicate_control(p, inst->predicate);
516
517 /* Pre-gen6, we have to specify write commits to ensure ordering
518 * between reads and writes within a thread. Afterwards, that's
519 * guaranteed and write commits only matter for inter-thread
520 * synchronization.
521 */
522 if (intel->gen >= 6) {
523 write_commit = false;
524 } else {
525 /* The visitor set up our destination register to be g0. This
526 * means that when the next read comes along, we will end up
527 * reading from g0 and causing a block on the write commit. For
528 * write-after-read, we are relying on the value of the previous
529 * read being used (and thus blocking on completion) before our
530 * write is executed. This means we have to be careful in
531 * instruction scheduling to not violate this assumption.
532 */
533 write_commit = true;
534 }
535
536 /* Each of the 8 channel enables is considered for whether each
537 * dword is written.
538 */
539 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
540 brw_set_dest(p, send, dst);
541 brw_set_src0(p, send, header);
542 if (intel->gen < 6)
543 send->header.destreg__conditionalmod = inst->base_mrf;
544 brw_set_dp_write_message(p, send,
545 255, /* binding table index: stateless access */
546 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
547 msg_type,
548 3, /* mlen */
549 true, /* header present */
550 false, /* not a render target write */
551 write_commit, /* rlen */
552 false, /* eot */
553 write_commit);
554 }
555
556 void
557 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
558 struct brw_reg dst,
559 struct brw_reg index,
560 struct brw_reg offset)
561 {
562 assert(intel->gen <= 7);
563 assert(index.file == BRW_IMMEDIATE_VALUE &&
564 index.type == BRW_REGISTER_TYPE_UD);
565 uint32_t surf_index = index.dw1.ud;
566
567 struct brw_reg header = brw_vec8_grf(0, 0);
568
569 gen6_resolve_implied_move(p, &header, inst->base_mrf);
570
571 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
572 offset);
573
574 uint32_t msg_type;
575
576 if (intel->gen >= 6)
577 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
578 else if (intel->gen == 5 || intel->is_g4x)
579 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
580 else
581 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
582
583 /* Each of the 8 channel enables is considered for whether each
584 * dword is written.
585 */
586 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
587 brw_set_dest(p, send, dst);
588 brw_set_src0(p, send, header);
589 if (intel->gen < 6)
590 send->header.destreg__conditionalmod = inst->base_mrf;
591 brw_set_dp_read_message(p, send,
592 surf_index,
593 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
594 msg_type,
595 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
596 2, /* mlen */
597 true, /* header_present */
598 1 /* rlen */);
599 }
600
601 void
602 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
603 struct brw_reg dst,
604 struct brw_reg surf_index,
605 struct brw_reg offset)
606 {
607 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
608 surf_index.type == BRW_REGISTER_TYPE_UD);
609
610 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
611 brw_set_dest(p, insn, dst);
612 brw_set_src0(p, insn, offset);
613 brw_set_sampler_message(p, insn,
614 surf_index.dw1.ud,
615 0, /* LD message ignores sampler unit */
616 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
617 1, /* rlen */
618 1, /* mlen */
619 false, /* no header */
620 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
621 0);
622 }
623
624 /**
625 * Generate assembly for a Vec4 IR instruction.
626 *
627 * \param instruction The Vec4 IR instruction to generate code for.
628 * \param dst The destination register.
629 * \param src An array of up to three source registers.
630 */
631 void
632 vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
633 struct brw_reg dst,
634 struct brw_reg *src)
635 {
636 vec4_instruction *inst = (vec4_instruction *) instruction;
637
638 switch (inst->opcode) {
639 case BRW_OPCODE_MOV:
640 brw_MOV(p, dst, src[0]);
641 break;
642 case BRW_OPCODE_ADD:
643 brw_ADD(p, dst, src[0], src[1]);
644 break;
645 case BRW_OPCODE_MUL:
646 brw_MUL(p, dst, src[0], src[1]);
647 break;
648 case BRW_OPCODE_MACH:
649 brw_set_acc_write_control(p, 1);
650 brw_MACH(p, dst, src[0], src[1]);
651 brw_set_acc_write_control(p, 0);
652 break;
653
654 case BRW_OPCODE_MAD:
655 brw_MAD(p, dst, src[0], src[1], src[2]);
656 break;
657
658 case BRW_OPCODE_FRC:
659 brw_FRC(p, dst, src[0]);
660 break;
661 case BRW_OPCODE_RNDD:
662 brw_RNDD(p, dst, src[0]);
663 break;
664 case BRW_OPCODE_RNDE:
665 brw_RNDE(p, dst, src[0]);
666 break;
667 case BRW_OPCODE_RNDZ:
668 brw_RNDZ(p, dst, src[0]);
669 break;
670
671 case BRW_OPCODE_AND:
672 brw_AND(p, dst, src[0], src[1]);
673 break;
674 case BRW_OPCODE_OR:
675 brw_OR(p, dst, src[0], src[1]);
676 break;
677 case BRW_OPCODE_XOR:
678 brw_XOR(p, dst, src[0], src[1]);
679 break;
680 case BRW_OPCODE_NOT:
681 brw_NOT(p, dst, src[0]);
682 break;
683 case BRW_OPCODE_ASR:
684 brw_ASR(p, dst, src[0], src[1]);
685 break;
686 case BRW_OPCODE_SHR:
687 brw_SHR(p, dst, src[0], src[1]);
688 break;
689 case BRW_OPCODE_SHL:
690 brw_SHL(p, dst, src[0], src[1]);
691 break;
692
693 case BRW_OPCODE_CMP:
694 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
695 break;
696 case BRW_OPCODE_SEL:
697 brw_SEL(p, dst, src[0], src[1]);
698 break;
699
700 case BRW_OPCODE_DPH:
701 brw_DPH(p, dst, src[0], src[1]);
702 break;
703
704 case BRW_OPCODE_DP4:
705 brw_DP4(p, dst, src[0], src[1]);
706 break;
707
708 case BRW_OPCODE_DP3:
709 brw_DP3(p, dst, src[0], src[1]);
710 break;
711
712 case BRW_OPCODE_DP2:
713 brw_DP2(p, dst, src[0], src[1]);
714 break;
715
716 case BRW_OPCODE_F32TO16:
717 brw_F32TO16(p, dst, src[0]);
718 break;
719
720 case BRW_OPCODE_F16TO32:
721 brw_F16TO32(p, dst, src[0]);
722 break;
723
724 case BRW_OPCODE_LRP:
725 brw_LRP(p, dst, src[0], src[1], src[2]);
726 break;
727
728 case BRW_OPCODE_BFREV:
729 /* BFREV only supports UD type for src and dst. */
730 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
731 retype(src[0], BRW_REGISTER_TYPE_UD));
732 break;
733 case BRW_OPCODE_FBH:
734 /* FBH only supports UD type for dst. */
735 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
736 break;
737 case BRW_OPCODE_FBL:
738 /* FBL only supports UD type for dst. */
739 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
740 break;
741 case BRW_OPCODE_CBIT:
742 /* CBIT only supports UD type for dst. */
743 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
744 break;
745
746 case BRW_OPCODE_BFE:
747 brw_BFE(p, dst, src[0], src[1], src[2]);
748 break;
749
750 case BRW_OPCODE_BFI1:
751 brw_BFI1(p, dst, src[0], src[1]);
752 break;
753 case BRW_OPCODE_BFI2:
754 brw_BFI2(p, dst, src[0], src[1], src[2]);
755 break;
756
757 case BRW_OPCODE_IF:
758 if (inst->src[0].file != BAD_FILE) {
759 /* The instruction has an embedded compare (only allowed on gen6) */
760 assert(intel->gen == 6);
761 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
762 } else {
763 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
764 brw_inst->header.predicate_control = inst->predicate;
765 }
766 break;
767
768 case BRW_OPCODE_ELSE:
769 brw_ELSE(p);
770 break;
771 case BRW_OPCODE_ENDIF:
772 brw_ENDIF(p);
773 break;
774
775 case BRW_OPCODE_DO:
776 brw_DO(p, BRW_EXECUTE_8);
777 break;
778
779 case BRW_OPCODE_BREAK:
780 brw_BREAK(p);
781 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
782 break;
783 case BRW_OPCODE_CONTINUE:
784 /* FINISHME: We need to write the loop instruction support still. */
785 if (intel->gen >= 6)
786 gen6_CONT(p);
787 else
788 brw_CONT(p);
789 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
790 break;
791
792 case BRW_OPCODE_WHILE:
793 brw_WHILE(p);
794 break;
795
796 case SHADER_OPCODE_RCP:
797 case SHADER_OPCODE_RSQ:
798 case SHADER_OPCODE_SQRT:
799 case SHADER_OPCODE_EXP2:
800 case SHADER_OPCODE_LOG2:
801 case SHADER_OPCODE_SIN:
802 case SHADER_OPCODE_COS:
803 if (intel->gen == 6) {
804 generate_math1_gen6(inst, dst, src[0]);
805 } else {
806 /* Also works for Gen7. */
807 generate_math1_gen4(inst, dst, src[0]);
808 }
809 break;
810
811 case SHADER_OPCODE_POW:
812 case SHADER_OPCODE_INT_QUOTIENT:
813 case SHADER_OPCODE_INT_REMAINDER:
814 if (intel->gen >= 7) {
815 generate_math2_gen7(inst, dst, src[0], src[1]);
816 } else if (intel->gen == 6) {
817 generate_math2_gen6(inst, dst, src[0], src[1]);
818 } else {
819 generate_math2_gen4(inst, dst, src[0], src[1]);
820 }
821 break;
822
823 case SHADER_OPCODE_TEX:
824 case SHADER_OPCODE_TXD:
825 case SHADER_OPCODE_TXF:
826 case SHADER_OPCODE_TXF_MS:
827 case SHADER_OPCODE_TXL:
828 case SHADER_OPCODE_TXS:
829 generate_tex(inst, dst, src[0]);
830 break;
831
832 case VS_OPCODE_URB_WRITE:
833 generate_urb_write(inst);
834 break;
835
836 case VS_OPCODE_SCRATCH_READ:
837 generate_scratch_read(inst, dst, src[0]);
838 break;
839
840 case VS_OPCODE_SCRATCH_WRITE:
841 generate_scratch_write(inst, dst, src[0], src[1]);
842 break;
843
844 case VS_OPCODE_PULL_CONSTANT_LOAD:
845 generate_pull_constant_load(inst, dst, src[0], src[1]);
846 break;
847
848 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
849 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
850 break;
851
852 case SHADER_OPCODE_SHADER_TIME_ADD:
853 brw_shader_time_add(p, src[0], SURF_INDEX_VS_SHADER_TIME);
854 break;
855
856 default:
857 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
858 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
859 opcode_descs[inst->opcode].name);
860 } else {
861 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
862 }
863 abort();
864 }
865 }
866
867 void
868 vec4_generator::generate_code(exec_list *instructions)
869 {
870 int last_native_insn_offset = 0;
871 const char *last_annotation_string = NULL;
872 const void *last_annotation_ir = NULL;
873
874 if (unlikely(debug_flag)) {
875 if (shader) {
876 printf("Native code for vertex shader %d:\n", shader_prog->Name);
877 } else {
878 printf("Native code for vertex program %d:\n", prog->Id);
879 }
880 }
881
882 foreach_list(node, instructions) {
883 vec4_instruction *inst = (vec4_instruction *)node;
884 struct brw_reg src[3], dst;
885
886 if (unlikely(debug_flag)) {
887 if (last_annotation_ir != inst->ir) {
888 last_annotation_ir = inst->ir;
889 if (last_annotation_ir) {
890 printf(" ");
891 if (shader) {
892 ((ir_instruction *) last_annotation_ir)->print();
893 } else {
894 const prog_instruction *vpi;
895 vpi = (const prog_instruction *) inst->ir;
896 printf("%d: ", (int)(vpi - prog->Instructions));
897 _mesa_fprint_instruction_opt(stdout, vpi, 0,
898 PROG_PRINT_DEBUG, NULL);
899 }
900 printf("\n");
901 }
902 }
903 if (last_annotation_string != inst->annotation) {
904 last_annotation_string = inst->annotation;
905 if (last_annotation_string)
906 printf(" %s\n", last_annotation_string);
907 }
908 }
909
910 for (unsigned int i = 0; i < 3; i++) {
911 src[i] = inst->get_src(i);
912 }
913 dst = inst->get_dst();
914
915 brw_set_conditionalmod(p, inst->conditional_mod);
916 brw_set_predicate_control(p, inst->predicate);
917 brw_set_predicate_inverse(p, inst->predicate_inverse);
918 brw_set_saturate(p, inst->saturate);
919 brw_set_mask_control(p, inst->force_writemask_all);
920
921 unsigned pre_emit_nr_insn = p->nr_insn;
922
923 generate_vec4_instruction(inst, dst, src);
924
925 if (inst->no_dd_clear || inst->no_dd_check) {
926 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
927 !"no_dd_check or no_dd_clear set for IR emitting more "
928 "than 1 instruction");
929
930 struct brw_instruction *last = &p->store[pre_emit_nr_insn];
931
932 if (inst->no_dd_clear)
933 last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
934 if (inst->no_dd_check)
935 last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
936 }
937
938 if (unlikely(debug_flag)) {
939 brw_dump_compile(p, stdout,
940 last_native_insn_offset, p->next_insn_offset);
941 }
942
943 last_native_insn_offset = p->next_insn_offset;
944 }
945
946 if (unlikely(debug_flag)) {
947 printf("\n");
948 }
949
950 brw_set_uip_jip(p);
951
952 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
953 * emit issues, it doesn't get the jump distances into the output,
954 * which is often something we want to debug. So this is here in
955 * case you're doing that.
956 */
957 if (0 && unlikely(debug_flag)) {
958 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
959 }
960 }
961
962 const unsigned *
963 vec4_generator::generate_assembly(exec_list *instructions,
964 unsigned *assembly_size)
965 {
966 brw_set_access_mode(p, BRW_ALIGN_16);
967 generate_code(instructions);
968 return brw_get_program(p, assembly_size);
969 }
970
971 } /* namespace brw */