1 /* Copyright © 2011 Intel Corporation
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
35 vec4_instruction::get_dst(void)
37 struct brw_reg brw_reg
;
41 brw_reg
= brw_vec8_grf(dst
.reg
+ dst
.reg_offset
, 0);
42 brw_reg
= retype(brw_reg
, dst
.type
);
43 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
47 brw_reg
= brw_message_reg(dst
.reg
+ dst
.reg_offset
);
48 brw_reg
= retype(brw_reg
, dst
.type
);
49 brw_reg
.dw1
.bits
.writemask
= dst
.writemask
;
53 brw_reg
= dst
.fixed_hw_reg
;
57 brw_reg
= brw_null_reg();
61 assert(!"not reached");
62 brw_reg
= brw_null_reg();
69 vec4_instruction::get_src(int i
)
71 struct brw_reg brw_reg
;
73 switch (src
[i
].file
) {
75 brw_reg
= brw_vec8_grf(src
[i
].reg
+ src
[i
].reg_offset
, 0);
76 brw_reg
= retype(brw_reg
, src
[i
].type
);
77 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
79 brw_reg
= brw_abs(brw_reg
);
81 brw_reg
= negate(brw_reg
);
85 switch (src
[i
].type
) {
86 case BRW_REGISTER_TYPE_F
:
87 brw_reg
= brw_imm_f(src
[i
].imm
.f
);
89 case BRW_REGISTER_TYPE_D
:
90 brw_reg
= brw_imm_d(src
[i
].imm
.i
);
92 case BRW_REGISTER_TYPE_UD
:
93 brw_reg
= brw_imm_ud(src
[i
].imm
.u
);
96 assert(!"not reached");
97 brw_reg
= brw_null_reg();
103 brw_reg
= stride(brw_vec4_grf(1 + (src
[i
].reg
+ src
[i
].reg_offset
) / 2,
104 ((src
[i
].reg
+ src
[i
].reg_offset
) % 2) * 4),
106 brw_reg
= retype(brw_reg
, src
[i
].type
);
107 brw_reg
.dw1
.bits
.swizzle
= src
[i
].swizzle
;
109 brw_reg
= brw_abs(brw_reg
);
111 brw_reg
= negate(brw_reg
);
113 /* This should have been moved to pull constants. */
114 assert(!src
[i
].reladdr
);
118 brw_reg
= src
[i
].fixed_hw_reg
;
122 /* Probably unused. */
123 brw_reg
= brw_null_reg();
127 assert(!"not reached");
128 brw_reg
= brw_null_reg();
135 vec4_generator::vec4_generator(struct brw_context
*brw
,
136 struct gl_shader_program
*shader_prog
,
137 struct gl_program
*prog
,
140 : brw(brw
), shader_prog(shader_prog
), prog(prog
), mem_ctx(mem_ctx
),
141 debug_flag(debug_flag
)
145 shader
= shader_prog
? shader_prog
->_LinkedShaders
[MESA_SHADER_VERTEX
] : NULL
;
147 p
= rzalloc(mem_ctx
, struct brw_compile
);
148 brw_init_compile(brw
, p
, mem_ctx
);
151 vec4_generator::~vec4_generator()
156 vec4_generator::generate_math1_gen4(vec4_instruction
*inst
,
162 brw_math_function(inst
->opcode
),
165 BRW_MATH_DATA_VECTOR
,
166 BRW_MATH_PRECISION_FULL
);
170 check_gen6_math_src_arg(struct brw_reg src
)
172 /* Source swizzles are ignored. */
175 assert(src
.dw1
.bits
.swizzle
== BRW_SWIZZLE_XYZW
);
179 vec4_generator::generate_math1_gen6(vec4_instruction
*inst
,
183 /* Can't do writemask because math can't be align16. */
184 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
185 check_gen6_math_src_arg(src
);
187 brw_set_access_mode(p
, BRW_ALIGN_1
);
190 brw_math_function(inst
->opcode
),
193 BRW_MATH_DATA_SCALAR
,
194 BRW_MATH_PRECISION_FULL
);
195 brw_set_access_mode(p
, BRW_ALIGN_16
);
199 vec4_generator::generate_math2_gen7(vec4_instruction
*inst
,
206 brw_math_function(inst
->opcode
),
211 vec4_generator::generate_math2_gen6(vec4_instruction
*inst
,
216 /* Can't do writemask because math can't be align16. */
217 assert(dst
.dw1
.bits
.writemask
== WRITEMASK_XYZW
);
218 /* Source swizzles are ignored. */
219 check_gen6_math_src_arg(src0
);
220 check_gen6_math_src_arg(src1
);
222 brw_set_access_mode(p
, BRW_ALIGN_1
);
225 brw_math_function(inst
->opcode
),
227 brw_set_access_mode(p
, BRW_ALIGN_16
);
231 vec4_generator::generate_math2_gen4(vec4_instruction
*inst
,
236 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
239 * "Operand0[7]. For the INT DIV functions, this operand is the
242 * "Operand1[7]. For the INT DIV functions, this operand is the
245 bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
246 struct brw_reg
&op0
= is_int_div
? src1
: src0
;
247 struct brw_reg
&op1
= is_int_div
? src0
: src1
;
249 brw_push_insn_state(p
);
250 brw_set_saturate(p
, false);
251 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
252 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), op1
.type
), op1
);
253 brw_pop_insn_state(p
);
257 brw_math_function(inst
->opcode
),
260 BRW_MATH_DATA_VECTOR
,
261 BRW_MATH_PRECISION_FULL
);
265 vec4_generator::generate_tex(vec4_instruction
*inst
,
271 if (intel
->gen
>= 5) {
272 switch (inst
->opcode
) {
273 case SHADER_OPCODE_TEX
:
274 case SHADER_OPCODE_TXL
:
275 if (inst
->shadow_compare
) {
276 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
278 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
281 case SHADER_OPCODE_TXD
:
282 if (inst
->shadow_compare
) {
283 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
284 assert(intel
->is_haswell
);
285 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
287 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
290 case SHADER_OPCODE_TXF
:
291 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
293 case SHADER_OPCODE_TXF_MS
:
295 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
297 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
299 case SHADER_OPCODE_TXS
:
300 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
303 assert(!"should not get here: invalid VS texture opcode");
307 switch (inst
->opcode
) {
308 case SHADER_OPCODE_TEX
:
309 case SHADER_OPCODE_TXL
:
310 if (inst
->shadow_compare
) {
311 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE
;
312 assert(inst
->mlen
== 3);
314 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD
;
315 assert(inst
->mlen
== 2);
318 case SHADER_OPCODE_TXD
:
319 /* There is no sample_d_c message; comparisons are done manually. */
320 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS
;
321 assert(inst
->mlen
== 4);
323 case SHADER_OPCODE_TXF
:
324 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_LD
;
325 assert(inst
->mlen
== 2);
327 case SHADER_OPCODE_TXS
:
328 msg_type
= BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO
;
329 assert(inst
->mlen
== 2);
332 assert(!"should not get here: invalid VS texture opcode");
337 assert(msg_type
!= -1);
339 /* Load the message header if present. If there's a texture offset, we need
340 * to set it up explicitly and load the offset bitfield. Otherwise, we can
341 * use an implied move from g0 to the first message register.
343 if (inst
->texture_offset
) {
344 /* Explicitly set up the message header by copying g0 to the MRF. */
345 brw_push_insn_state(p
);
346 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
347 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
), BRW_REGISTER_TYPE_UD
),
348 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
350 /* Then set the offset bits in DWord 2. */
351 brw_set_access_mode(p
, BRW_ALIGN_1
);
353 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, inst
->base_mrf
, 2),
354 BRW_REGISTER_TYPE_UD
),
355 brw_imm_uw(inst
->texture_offset
));
356 brw_pop_insn_state(p
);
357 } else if (inst
->header_present
) {
358 /* Set up an implied move from g0 to the MRF. */
359 src
= brw_vec8_grf(0, 0);
362 uint32_t return_format
;
365 case BRW_REGISTER_TYPE_D
:
366 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
368 case BRW_REGISTER_TYPE_UD
:
369 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
372 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
380 SURF_INDEX_VS_TEXTURE(inst
->sampler
),
383 1, /* response length */
385 inst
->header_present
,
386 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
391 vec4_generator::generate_urb_write(vec4_instruction
*inst
)
394 brw_null_reg(), /* dest */
395 inst
->base_mrf
, /* starting mrf reg nr */
396 brw_vec8_grf(0, 0), /* src */
397 false, /* allocate */
400 0, /* response len */
402 inst
->eot
, /* writes complete */
403 inst
->offset
, /* urb destination offset */
404 BRW_URB_SWIZZLE_INTERLEAVE
);
408 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1
,
409 struct brw_reg index
)
411 int second_vertex_offset
;
414 second_vertex_offset
= 1;
416 second_vertex_offset
= 16;
418 m1
= retype(m1
, BRW_REGISTER_TYPE_D
);
420 /* Set up M1 (message payload). Only the block offsets in M1.0 and
421 * M1.4 are used, and the rest are ignored.
423 struct brw_reg m1_0
= suboffset(vec1(m1
), 0);
424 struct brw_reg m1_4
= suboffset(vec1(m1
), 4);
425 struct brw_reg index_0
= suboffset(vec1(index
), 0);
426 struct brw_reg index_4
= suboffset(vec1(index
), 4);
428 brw_push_insn_state(p
);
429 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
430 brw_set_access_mode(p
, BRW_ALIGN_1
);
432 brw_MOV(p
, m1_0
, index_0
);
434 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
435 index_4
.dw1
.ud
+= second_vertex_offset
;
436 brw_MOV(p
, m1_4
, index_4
);
438 brw_ADD(p
, m1_4
, index_4
, brw_imm_d(second_vertex_offset
));
441 brw_pop_insn_state(p
);
445 vec4_generator::generate_scratch_read(vec4_instruction
*inst
,
447 struct brw_reg index
)
449 struct brw_reg header
= brw_vec8_grf(0, 0);
451 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
453 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
459 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
460 else if (intel
->gen
== 5 || intel
->is_g4x
)
461 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
463 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
465 /* Each of the 8 channel enables is considered for whether each
468 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
469 brw_set_dest(p
, send
, dst
);
470 brw_set_src0(p
, send
, header
);
472 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
473 brw_set_dp_read_message(p
, send
,
474 255, /* binding table index: stateless access */
475 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
477 BRW_DATAPORT_READ_TARGET_RENDER_CACHE
,
479 true, /* header_present */
484 vec4_generator::generate_scratch_write(vec4_instruction
*inst
,
487 struct brw_reg index
)
489 struct brw_reg header
= brw_vec8_grf(0, 0);
492 /* If the instruction is predicated, we'll predicate the send, not
495 brw_set_predicate_control(p
, false);
497 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
499 generate_oword_dual_block_offsets(brw_message_reg(inst
->base_mrf
+ 1),
503 retype(brw_message_reg(inst
->base_mrf
+ 2), BRW_REGISTER_TYPE_D
),
504 retype(src
, BRW_REGISTER_TYPE_D
));
509 msg_type
= GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
510 else if (intel
->gen
== 6)
511 msg_type
= GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
513 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
;
515 brw_set_predicate_control(p
, inst
->predicate
);
517 /* Pre-gen6, we have to specify write commits to ensure ordering
518 * between reads and writes within a thread. Afterwards, that's
519 * guaranteed and write commits only matter for inter-thread
522 if (intel
->gen
>= 6) {
523 write_commit
= false;
525 /* The visitor set up our destination register to be g0. This
526 * means that when the next read comes along, we will end up
527 * reading from g0 and causing a block on the write commit. For
528 * write-after-read, we are relying on the value of the previous
529 * read being used (and thus blocking on completion) before our
530 * write is executed. This means we have to be careful in
531 * instruction scheduling to not violate this assumption.
536 /* Each of the 8 channel enables is considered for whether each
539 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
540 brw_set_dest(p
, send
, dst
);
541 brw_set_src0(p
, send
, header
);
543 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
544 brw_set_dp_write_message(p
, send
,
545 255, /* binding table index: stateless access */
546 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
549 true, /* header present */
550 false, /* not a render target write */
551 write_commit
, /* rlen */
557 vec4_generator::generate_pull_constant_load(vec4_instruction
*inst
,
559 struct brw_reg index
,
560 struct brw_reg offset
)
562 assert(intel
->gen
<= 7);
563 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
564 index
.type
== BRW_REGISTER_TYPE_UD
);
565 uint32_t surf_index
= index
.dw1
.ud
;
567 struct brw_reg header
= brw_vec8_grf(0, 0);
569 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
571 brw_MOV(p
, retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_D
),
577 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
578 else if (intel
->gen
== 5 || intel
->is_g4x
)
579 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
581 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
583 /* Each of the 8 channel enables is considered for whether each
586 struct brw_instruction
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
587 brw_set_dest(p
, send
, dst
);
588 brw_set_src0(p
, send
, header
);
590 send
->header
.destreg__conditionalmod
= inst
->base_mrf
;
591 brw_set_dp_read_message(p
, send
,
593 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
595 BRW_DATAPORT_READ_TARGET_DATA_CACHE
,
597 true, /* header_present */
602 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction
*inst
,
604 struct brw_reg surf_index
,
605 struct brw_reg offset
)
607 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
&&
608 surf_index
.type
== BRW_REGISTER_TYPE_UD
);
610 brw_instruction
*insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
611 brw_set_dest(p
, insn
, dst
);
612 brw_set_src0(p
, insn
, offset
);
613 brw_set_sampler_message(p
, insn
,
615 0, /* LD message ignores sampler unit */
616 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
619 false, /* no header */
620 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
625 vec4_generator::generate_vec4_instruction(vec4_instruction
*instruction
,
629 vec4_instruction
*inst
= (vec4_instruction
*)instruction
;
631 switch (inst
->opcode
) {
632 case SHADER_OPCODE_RCP
:
633 case SHADER_OPCODE_RSQ
:
634 case SHADER_OPCODE_SQRT
:
635 case SHADER_OPCODE_EXP2
:
636 case SHADER_OPCODE_LOG2
:
637 case SHADER_OPCODE_SIN
:
638 case SHADER_OPCODE_COS
:
639 if (intel
->gen
== 6) {
640 generate_math1_gen6(inst
, dst
, src
[0]);
642 /* Also works for Gen7. */
643 generate_math1_gen4(inst
, dst
, src
[0]);
647 case SHADER_OPCODE_POW
:
648 case SHADER_OPCODE_INT_QUOTIENT
:
649 case SHADER_OPCODE_INT_REMAINDER
:
650 if (intel
->gen
>= 7) {
651 generate_math2_gen7(inst
, dst
, src
[0], src
[1]);
652 } else if (intel
->gen
== 6) {
653 generate_math2_gen6(inst
, dst
, src
[0], src
[1]);
655 generate_math2_gen4(inst
, dst
, src
[0], src
[1]);
659 case SHADER_OPCODE_TEX
:
660 case SHADER_OPCODE_TXD
:
661 case SHADER_OPCODE_TXF
:
662 case SHADER_OPCODE_TXF_MS
:
663 case SHADER_OPCODE_TXL
:
664 case SHADER_OPCODE_TXS
:
665 generate_tex(inst
, dst
, src
[0]);
668 case VS_OPCODE_URB_WRITE
:
669 generate_urb_write(inst
);
672 case VS_OPCODE_SCRATCH_READ
:
673 generate_scratch_read(inst
, dst
, src
[0]);
676 case VS_OPCODE_SCRATCH_WRITE
:
677 generate_scratch_write(inst
, dst
, src
[0], src
[1]);
680 case VS_OPCODE_PULL_CONSTANT_LOAD
:
681 generate_pull_constant_load(inst
, dst
, src
[0], src
[1]);
684 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
685 generate_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
688 case SHADER_OPCODE_SHADER_TIME_ADD
:
689 brw_shader_time_add(p
, src
[0], SURF_INDEX_VS_SHADER_TIME
);
693 if (inst
->opcode
< (int) ARRAY_SIZE(opcode_descs
)) {
694 _mesa_problem(ctx
, "Unsupported opcode in `%s' in VS\n",
695 opcode_descs
[inst
->opcode
].name
);
697 _mesa_problem(ctx
, "Unsupported opcode %d in VS", inst
->opcode
);
704 vec4_generator::generate_code(exec_list
*instructions
)
706 int last_native_insn_offset
= 0;
707 const char *last_annotation_string
= NULL
;
708 const void *last_annotation_ir
= NULL
;
710 if (unlikely(debug_flag
)) {
712 printf("Native code for vertex shader %d:\n", shader_prog
->Name
);
714 printf("Native code for vertex program %d:\n", prog
->Id
);
718 foreach_list(node
, instructions
) {
719 vec4_instruction
*inst
= (vec4_instruction
*)node
;
720 struct brw_reg src
[3], dst
;
722 if (unlikely(debug_flag
)) {
723 if (last_annotation_ir
!= inst
->ir
) {
724 last_annotation_ir
= inst
->ir
;
725 if (last_annotation_ir
) {
728 ((ir_instruction
*) last_annotation_ir
)->print();
730 const prog_instruction
*vpi
;
731 vpi
= (const prog_instruction
*) inst
->ir
;
732 printf("%d: ", (int)(vpi
- prog
->Instructions
));
733 _mesa_fprint_instruction_opt(stdout
, vpi
, 0,
734 PROG_PRINT_DEBUG
, NULL
);
739 if (last_annotation_string
!= inst
->annotation
) {
740 last_annotation_string
= inst
->annotation
;
741 if (last_annotation_string
)
742 printf(" %s\n", last_annotation_string
);
746 for (unsigned int i
= 0; i
< 3; i
++) {
747 src
[i
] = inst
->get_src(i
);
749 dst
= inst
->get_dst();
751 brw_set_conditionalmod(p
, inst
->conditional_mod
);
752 brw_set_predicate_control(p
, inst
->predicate
);
753 brw_set_predicate_inverse(p
, inst
->predicate_inverse
);
754 brw_set_saturate(p
, inst
->saturate
);
755 brw_set_mask_control(p
, inst
->force_writemask_all
);
757 unsigned pre_emit_nr_insn
= p
->nr_insn
;
759 switch (inst
->opcode
) {
761 brw_MOV(p
, dst
, src
[0]);
764 brw_ADD(p
, dst
, src
[0], src
[1]);
767 brw_MUL(p
, dst
, src
[0], src
[1]);
769 case BRW_OPCODE_MACH
:
770 brw_set_acc_write_control(p
, 1);
771 brw_MACH(p
, dst
, src
[0], src
[1]);
772 brw_set_acc_write_control(p
, 0);
776 brw_FRC(p
, dst
, src
[0]);
778 case BRW_OPCODE_RNDD
:
779 brw_RNDD(p
, dst
, src
[0]);
781 case BRW_OPCODE_RNDE
:
782 brw_RNDE(p
, dst
, src
[0]);
784 case BRW_OPCODE_RNDZ
:
785 brw_RNDZ(p
, dst
, src
[0]);
789 brw_AND(p
, dst
, src
[0], src
[1]);
792 brw_OR(p
, dst
, src
[0], src
[1]);
795 brw_XOR(p
, dst
, src
[0], src
[1]);
798 brw_NOT(p
, dst
, src
[0]);
801 brw_ASR(p
, dst
, src
[0], src
[1]);
804 brw_SHR(p
, dst
, src
[0], src
[1]);
807 brw_SHL(p
, dst
, src
[0], src
[1]);
811 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
814 brw_SEL(p
, dst
, src
[0], src
[1]);
818 brw_DPH(p
, dst
, src
[0], src
[1]);
822 brw_DP4(p
, dst
, src
[0], src
[1]);
826 brw_DP3(p
, dst
, src
[0], src
[1]);
830 brw_DP2(p
, dst
, src
[0], src
[1]);
833 case BRW_OPCODE_F32TO16
:
834 brw_F32TO16(p
, dst
, src
[0]);
837 case BRW_OPCODE_F16TO32
:
838 brw_F16TO32(p
, dst
, src
[0]);
842 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
846 if (inst
->src
[0].file
!= BAD_FILE
) {
847 /* The instruction has an embedded compare (only allowed on gen6) */
848 assert(intel
->gen
== 6);
849 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
851 struct brw_instruction
*brw_inst
= brw_IF(p
, BRW_EXECUTE_8
);
852 brw_inst
->header
.predicate_control
= inst
->predicate
;
856 case BRW_OPCODE_ELSE
:
859 case BRW_OPCODE_ENDIF
:
864 brw_DO(p
, BRW_EXECUTE_8
);
867 case BRW_OPCODE_BREAK
:
869 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
871 case BRW_OPCODE_CONTINUE
:
872 /* FINISHME: We need to write the loop instruction support still. */
877 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
880 case BRW_OPCODE_WHILE
:
885 generate_vec4_instruction(inst
, dst
, src
);
889 if (inst
->no_dd_clear
|| inst
->no_dd_check
) {
890 assert(p
->nr_insn
== pre_emit_nr_insn
+ 1 ||
891 !"no_dd_check or no_dd_clear set for IR emitting more "
892 "than 1 instruction");
894 struct brw_instruction
*last
= &p
->store
[pre_emit_nr_insn
];
896 if (inst
->no_dd_clear
)
897 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCLEARED
;
898 if (inst
->no_dd_check
)
899 last
->header
.dependency_control
|= BRW_DEPENDENCY_NOTCHECKED
;
902 if (unlikely(debug_flag
)) {
903 brw_dump_compile(p
, stdout
,
904 last_native_insn_offset
, p
->next_insn_offset
);
907 last_native_insn_offset
= p
->next_insn_offset
;
910 if (unlikely(debug_flag
)) {
916 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
917 * emit issues, it doesn't get the jump distances into the output,
918 * which is often something we want to debug. So this is here in
919 * case you're doing that.
921 if (0 && unlikely(debug_flag
)) {
922 brw_dump_compile(p
, stdout
, 0, p
->next_insn_offset
);
927 vec4_generator::generate_assembly(exec_list
*instructions
,
928 unsigned *assembly_size
)
930 brw_set_access_mode(p
, BRW_ALIGN_16
);
931 generate_code(instructions
);
932 return brw_get_program(p
, assembly_size
);
935 } /* namespace brw */