src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX + 1];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45       }
  46    }
  47
  48    /* VertexID is stored by the VF as the last vertex element, but we
  49     * don't represent it with a flag in inputs_read, so we call it
  50     * VERT_ATTRIB_MAX.
  51     */
  52    if (prog_data->uses_vertexid) {
  53       attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
  54       nr_attributes++;
  55    }
  56
  57    foreach_list(node, &this->instructions) {
  58       vec4_instruction *inst = (vec4_instruction *)node;
  59
  60       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  61       if (inst->dst.file == ATTR) {
  62          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  63
  64          struct brw_reg reg = brw_vec8_grf(grf, 0);
  65          reg.dw1.bits.writemask = inst->dst.writemask;
  66
  67          inst->dst.file = HW_REG;
  68          inst->dst.fixed_hw_reg = reg;
  69       }
  70
  71       for (int i = 0; i < 3; i++) {
  72          if (inst->src[i].file != ATTR)
  73             continue;
  74
  75          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  76
  77          struct brw_reg reg = brw_vec8_grf(grf, 0);
  78          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  79          reg.type = inst->src[i].type;
  80          if (inst->src[i].abs)
  81             reg = brw_abs(reg);
  82          if (inst->src[i].negate)
  83             reg = negate(reg);
  84
  85          inst->src[i].file = HW_REG;
  86          inst->src[i].fixed_hw_reg = reg;
  87       }
  88    }
  89
  90    /* The BSpec says we always have to read at least one thing from
  91     * the VF, and it appears that the hardware wedges otherwise.
  92     */
  93    if (nr_attributes == 0)
  94       nr_attributes = 1;
  95
  96    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  97
  98    return payload_reg + nr_attributes;
  99 }
 100
 101 int
 102 vec4_visitor::setup_uniforms(int reg)
 103 {
 104    /* The pre-gen6 VS requires that some push constants get loaded no
 105     * matter what, or the GPU would hang.
 106     */
 107    if (intel->gen < 6 && this->uniforms == 0) {
 108       this->uniform_vector_size[this->uniforms] = 1;
 109
 110       for (unsigned int i = 0; i < 4; i++) {
 111          unsigned int slot = this->uniforms * 4 + i;
 112          static float zero = 0.0;
 113          c->prog_data.param[slot] = &zero;
 114       }
 115
 116       this->uniforms++;
 117       reg++;
 118    } else {
 119       reg += ALIGN(uniforms, 2) / 2;
 120    }
 121
 122    c->prog_data.nr_params = this->uniforms * 4;
 123
 124    c->prog_data.curb_read_length = reg - 1;
 125    c->prog_data.uses_new_param_layout = true;
 126
 127    return reg;
 128 }
 129
 130 void
 131 vec4_visitor::setup_payload(void)
 132 {
 133    int reg = 0;
 134
 135    /* The payload always contains important data in g0, which contains
 136     * the URB handles that are passed on to the URB write at the end
 137     * of the thread.  So, we always start push constants at g1.
 138     */
 139    reg++;
 140
 141    reg = setup_uniforms(reg);
 142
 143    reg = setup_attributes(reg);
 144
 145    this->first_non_payload_grf = reg;
 146 }
 147
 148 struct brw_reg
 149 vec4_instruction::get_dst(void)
 150 {
 151    struct brw_reg brw_reg;
 152
 153    switch (dst.file) {
 154    case GRF:
 155       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 156       brw_reg = retype(brw_reg, dst.type);
 157       brw_reg.dw1.bits.writemask = dst.writemask;
 158       break;
 159
 160    case MRF:
 161       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 162       brw_reg = retype(brw_reg, dst.type);
 163       brw_reg.dw1.bits.writemask = dst.writemask;
 164       break;
 165
 166    case HW_REG:
 167       brw_reg = dst.fixed_hw_reg;
 168       break;
 169
 170    case BAD_FILE:
 171       brw_reg = brw_null_reg();
 172       break;
 173
 174    default:
 175       assert(!"not reached");
 176       brw_reg = brw_null_reg();
 177       break;
 178    }
 179    return brw_reg;
 180 }
 181
 182 struct brw_reg
 183 vec4_instruction::get_src(int i)
 184 {
 185    struct brw_reg brw_reg;
 186
 187    switch (src[i].file) {
 188    case GRF:
 189       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 190       brw_reg = retype(brw_reg, src[i].type);
 191       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 192       if (src[i].abs)
 193          brw_reg = brw_abs(brw_reg);
 194       if (src[i].negate)
 195          brw_reg = negate(brw_reg);
 196       break;
 197
 198    case IMM:
 199       switch (src[i].type) {
 200       case BRW_REGISTER_TYPE_F:
 201          brw_reg = brw_imm_f(src[i].imm.f);
 202          break;
 203       case BRW_REGISTER_TYPE_D:
 204          brw_reg = brw_imm_d(src[i].imm.i);
 205          break;
 206       case BRW_REGISTER_TYPE_UD:
 207          brw_reg = brw_imm_ud(src[i].imm.u);
 208          break;
 209       default:
 210          assert(!"not reached");
 211          brw_reg = brw_null_reg();
 212          break;
 213       }
 214       break;
 215
 216    case UNIFORM:
 217       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 218                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 219                        0, 4, 1);
 220       brw_reg = retype(brw_reg, src[i].type);
 221       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 222       if (src[i].abs)
 223          brw_reg = brw_abs(brw_reg);
 224       if (src[i].negate)
 225          brw_reg = negate(brw_reg);
 226
 227       /* This should have been moved to pull constants. */
 228       assert(!src[i].reladdr);
 229       break;
 230
 231    case HW_REG:
 232       brw_reg = src[i].fixed_hw_reg;
 233       break;
 234
 235    case BAD_FILE:
 236       /* Probably unused. */
 237       brw_reg = brw_null_reg();
 238       break;
 239    case ATTR:
 240    default:
 241       assert(!"not reached");
 242       brw_reg = brw_null_reg();
 243       break;
 244    }
 245
 246    return brw_reg;
 247 }
 248
 249 void
 250 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 251                                   struct brw_reg dst,
 252                                   struct brw_reg src)
 253 {
 254    brw_math(p,
 255             dst,
 256             brw_math_function(inst->opcode),
 257             BRW_MATH_SATURATE_NONE,
 258             inst->base_mrf,
 259             src,
 260             BRW_MATH_DATA_VECTOR,
 261             BRW_MATH_PRECISION_FULL);
 262 }
 263
 264 static void
 265 check_gen6_math_src_arg(struct brw_reg src)
 266 {
 267    /* Source swizzles are ignored. */
 268    assert(!src.abs);
 269    assert(!src.negate);
 270    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 271 }
 272
 273 void
 274 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 275                                   struct brw_reg dst,
 276                                   struct brw_reg src)
 277 {
 278    /* Can't do writemask because math can't be align16. */
 279    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 280    check_gen6_math_src_arg(src);
 281
 282    brw_set_access_mode(p, BRW_ALIGN_1);
 283    brw_math(p,
 284             dst,
 285             brw_math_function(inst->opcode),
 286             BRW_MATH_SATURATE_NONE,
 287             inst->base_mrf,
 288             src,
 289             BRW_MATH_DATA_SCALAR,
 290             BRW_MATH_PRECISION_FULL);
 291    brw_set_access_mode(p, BRW_ALIGN_16);
 292 }
 293
 294 void
 295 vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
 296                                   struct brw_reg dst,
 297                                   struct brw_reg src0,
 298                                   struct brw_reg src1)
 299 {
 300    brw_math2(p,
 301              dst,
 302              brw_math_function(inst->opcode),
 303              src0, src1);
 304 }
 305
 306 void
 307 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 308                                   struct brw_reg dst,
 309                                   struct brw_reg src0,
 310                                   struct brw_reg src1)
 311 {
 312    /* Can't do writemask because math can't be align16. */
 313    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 314    /* Source swizzles are ignored. */
 315    check_gen6_math_src_arg(src0);
 316    check_gen6_math_src_arg(src1);
 317
 318    brw_set_access_mode(p, BRW_ALIGN_1);
 319    brw_math2(p,
 320              dst,
 321              brw_math_function(inst->opcode),
 322              src0, src1);
 323    brw_set_access_mode(p, BRW_ALIGN_16);
 324 }
 325
 326 void
 327 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 328                                   struct brw_reg dst,
 329                                   struct brw_reg src0,
 330                                   struct brw_reg src1)
 331 {
 332    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 333     * "Message Payload":
 334     *
 335     * "Operand0[7].  For the INT DIV functions, this operand is the
 336     *  denominator."
 337     *  ...
 338     * "Operand1[7].  For the INT DIV functions, this operand is the
 339     *  numerator."
 340     */
 341    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 342    struct brw_reg &op0 = is_int_div ? src1 : src0;
 343    struct brw_reg &op1 = is_int_div ? src0 : src1;
 344
 345    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 346
 347    brw_math(p,
 348             dst,
 349             brw_math_function(inst->opcode),
 350             BRW_MATH_SATURATE_NONE,
 351             inst->base_mrf,
 352             op0,
 353             BRW_MATH_DATA_VECTOR,
 354             BRW_MATH_PRECISION_FULL);
 355 }
 356
 357 void
 358 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 359 {
 360    brw_urb_WRITE(p,
 361                  brw_null_reg(), /* dest */
 362                  inst->base_mrf, /* starting mrf reg nr */
 363                  brw_vec8_grf(0, 0), /* src */
 364                  false,         /* allocate */
 365                  true,          /* used */
 366                  inst->mlen,
 367                  0,             /* response len */
 368                  inst->eot,     /* eot */
 369                  inst->eot,     /* writes complete */
 370                  inst->offset,  /* urb destination offset */
 371                  BRW_URB_SWIZZLE_INTERLEAVE);
 372 }
 373
 374 void
 375 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 376                                                 struct brw_reg index)
 377 {
 378    int second_vertex_offset;
 379
 380    if (intel->gen >= 6)
 381       second_vertex_offset = 1;
 382    else
 383       second_vertex_offset = 16;
 384
 385    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 386
 387    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 388     * M1.4 are used, and the rest are ignored.
 389     */
 390    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 391    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 392    struct brw_reg index_0 = suboffset(vec1(index), 0);
 393    struct brw_reg index_4 = suboffset(vec1(index), 4);
 394
 395    brw_push_insn_state(p);
 396    brw_set_mask_control(p, BRW_MASK_DISABLE);
 397    brw_set_access_mode(p, BRW_ALIGN_1);
 398
 399    brw_MOV(p, m1_0, index_0);
 400
 401    brw_set_predicate_inverse(p, true);
 402    if (index.file == BRW_IMMEDIATE_VALUE) {
 403       index_4.dw1.ud += second_vertex_offset;
 404       brw_MOV(p, m1_4, index_4);
 405    } else {
 406       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 407    }
 408
 409    brw_pop_insn_state(p);
 410 }
 411
 412 void
 413 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 414                                     struct brw_reg dst,
 415                                     struct brw_reg index)
 416 {
 417    struct brw_reg header = brw_vec8_grf(0, 0);
 418
 419    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 420
 421    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 422                                      index);
 423
 424    uint32_t msg_type;
 425
 426    if (intel->gen >= 6)
 427       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 428    else if (intel->gen == 5 || intel->is_g4x)
 429       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 430    else
 431       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 432
 433    /* Each of the 8 channel enables is considered for whether each
 434     * dword is written.
 435     */
 436    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 437    brw_set_dest(p, send, dst);
 438    brw_set_src0(p, send, header);
 439    if (intel->gen < 6)
 440       send->header.destreg__conditionalmod = inst->base_mrf;
 441    brw_set_dp_read_message(p, send,
 442                            255, /* binding table index: stateless access */
 443                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 444                            msg_type,
 445                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 446                            2, /* mlen */
 447                            1 /* rlen */);
 448 }
 449
 450 void
 451 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 452                                      struct brw_reg dst,
 453                                      struct brw_reg src,
 454                                      struct brw_reg index)
 455 {
 456    struct brw_reg header = brw_vec8_grf(0, 0);
 457    bool write_commit;
 458
 459    /* If the instruction is predicated, we'll predicate the send, not
 460     * the header setup.
 461     */
 462    brw_set_predicate_control(p, false);
 463
 464    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 465
 466    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 467                                      index);
 468
 469    brw_MOV(p,
 470            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 471            retype(src, BRW_REGISTER_TYPE_D));
 472
 473    uint32_t msg_type;
 474
 475    if (intel->gen >= 7)
 476       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 477    else if (intel->gen == 6)
 478       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 479    else
 480       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 481
 482    brw_set_predicate_control(p, inst->predicate);
 483
 484    /* Pre-gen6, we have to specify write commits to ensure ordering
 485     * between reads and writes within a thread.  Afterwards, that's
 486     * guaranteed and write commits only matter for inter-thread
 487     * synchronization.
 488     */
 489    if (intel->gen >= 6) {
 490       write_commit = false;
 491    } else {
 492       /* The visitor set up our destination register to be g0.  This
 493        * means that when the next read comes along, we will end up
 494        * reading from g0 and causing a block on the write commit.  For
 495        * write-after-read, we are relying on the value of the previous
 496        * read being used (and thus blocking on completion) before our
 497        * write is executed.  This means we have to be careful in
 498        * instruction scheduling to not violate this assumption.
 499        */
 500       write_commit = true;
 501    }
 502
 503    /* Each of the 8 channel enables is considered for whether each
 504     * dword is written.
 505     */
 506    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 507    brw_set_dest(p, send, dst);
 508    brw_set_src0(p, send, header);
 509    if (intel->gen < 6)
 510       send->header.destreg__conditionalmod = inst->base_mrf;
 511    brw_set_dp_write_message(p, send,
 512                             255, /* binding table index: stateless access */
 513                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 514                             msg_type,
 515                             3, /* mlen */
 516                             true, /* header present */
 517                             false, /* not a render target write */
 518                             write_commit, /* rlen */
 519                             false, /* eot */
 520                             write_commit);
 521 }
 522
 523 void
 524 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 525                                           struct brw_reg dst,
 526                                           struct brw_reg index)
 527 {
 528    struct brw_reg header = brw_vec8_grf(0, 0);
 529
 530    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 531
 532    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 533            index);
 534
 535    uint32_t msg_type;
 536
 537    if (intel->gen >= 6)
 538       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 539    else if (intel->gen == 5 || intel->is_g4x)
 540       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 541    else
 542       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 543
 544    /* Each of the 8 channel enables is considered for whether each
 545     * dword is written.
 546     */
 547    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 548    brw_set_dest(p, send, dst);
 549    brw_set_src0(p, send, header);
 550    if (intel->gen < 6)
 551       send->header.destreg__conditionalmod = inst->base_mrf;
 552    brw_set_dp_read_message(p, send,
 553                            SURF_INDEX_VERT_CONST_BUFFER,
 554                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 555                            msg_type,
 556                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 557                            2, /* mlen */
 558                            1 /* rlen */);
 559 }
 560
 561 void
 562 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 563                                       struct brw_reg dst,
 564                                       struct brw_reg *src)
 565 {
 566    vec4_instruction *inst = (vec4_instruction *)instruction;
 567
 568    switch (inst->opcode) {
 569    case SHADER_OPCODE_RCP:
 570    case SHADER_OPCODE_RSQ:
 571    case SHADER_OPCODE_SQRT:
 572    case SHADER_OPCODE_EXP2:
 573    case SHADER_OPCODE_LOG2:
 574    case SHADER_OPCODE_SIN:
 575    case SHADER_OPCODE_COS:
 576       if (intel->gen == 6) {
 577          generate_math1_gen6(inst, dst, src[0]);
 578       } else {
 579          /* Also works for Gen7. */
 580          generate_math1_gen4(inst, dst, src[0]);
 581       }
 582       break;
 583
 584    case SHADER_OPCODE_POW:
 585    case SHADER_OPCODE_INT_QUOTIENT:
 586    case SHADER_OPCODE_INT_REMAINDER:
 587       if (intel->gen >= 7) {
 588          generate_math2_gen7(inst, dst, src[0], src[1]);
 589       } else if (intel->gen == 6) {
 590          generate_math2_gen6(inst, dst, src[0], src[1]);
 591       } else {
 592          generate_math2_gen4(inst, dst, src[0], src[1]);
 593       }
 594       break;
 595
 596    case VS_OPCODE_URB_WRITE:
 597       generate_urb_write(inst);
 598       break;
 599
 600    case VS_OPCODE_SCRATCH_READ:
 601       generate_scratch_read(inst, dst, src[0]);
 602       break;
 603
 604    case VS_OPCODE_SCRATCH_WRITE:
 605       generate_scratch_write(inst, dst, src[0], src[1]);
 606       break;
 607
 608    case VS_OPCODE_PULL_CONSTANT_LOAD:
 609       generate_pull_constant_load(inst, dst, src[0]);
 610       break;
 611
 612    default:
 613       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 614          fail("unsupported opcode in `%s' in VS\n",
 615               brw_opcodes[inst->opcode].name);
 616       } else {
 617          fail("Unsupported opcode %d in VS", inst->opcode);
 618       }
 619    }
 620 }
 621
 622 bool
 623 vec4_visitor::run()
 624 {
 625    if (c->key.userclip_active && !c->key.uses_clip_distance)
 626       setup_uniform_clipplane_values();
 627
 628    /* Generate VS IR for main().  (the visitor only descends into
 629     * functions called "main").
 630     */
 631    visit_instructions(shader->ir);
 632
 633    emit_urb_writes();
 634
 635    /* Before any optimization, push array accesses out to scratch
 636     * space where we need them to be.  This pass may allocate new
 637     * virtual GRFs, so we want to do it early.  It also makes sure
 638     * that we have reladdr computations available for CSE, since we'll
 639     * often do repeated subexpressions for those.
 640     */
 641    move_grf_array_access_to_scratch();
 642    move_uniform_array_access_to_pull_constants();
 643    pack_uniform_registers();
 644    move_push_constants_to_pull_constants();
 645
 646    bool progress;
 647    do {
 648       progress = false;
 649       progress = dead_code_eliminate() || progress;
 650       progress = opt_copy_propagation() || progress;
 651       progress = opt_algebraic() || progress;
 652       progress = opt_compute_to_mrf() || progress;
 653    } while (progress);
 654
 655
 656    if (failed)
 657       return false;
 658
 659    setup_payload();
 660    reg_allocate();
 661
 662    if (failed)
 663       return false;
 664
 665    brw_set_access_mode(p, BRW_ALIGN_16);
 666
 667    generate_code();
 668
 669    return !failed;
 670 }
 671
 672 void
 673 vec4_visitor::generate_code()
 674 {
 675    int last_native_inst = 0;
 676    const char *last_annotation_string = NULL;
 677    ir_instruction *last_annotation_ir = NULL;
 678
 679    int loop_stack_array_size = 16;
 680    int loop_stack_depth = 0;
 681    brw_instruction **loop_stack =
 682       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 683    int *if_depth_in_loop =
 684       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 685
 686
 687    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 688       printf("Native code for vertex shader %d:\n", prog->Name);
 689    }
 690
 691    foreach_list(node, &this->instructions) {
 692       vec4_instruction *inst = (vec4_instruction *)node;
 693       struct brw_reg src[3], dst;
 694
 695       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 696          if (last_annotation_ir != inst->ir) {
 697             last_annotation_ir = inst->ir;
 698             if (last_annotation_ir) {
 699                printf("   ");
 700                last_annotation_ir->print();
 701                printf("\n");
 702             }
 703          }
 704          if (last_annotation_string != inst->annotation) {
 705             last_annotation_string = inst->annotation;
 706             if (last_annotation_string)
 707                printf("   %s\n", last_annotation_string);
 708          }
 709       }
 710
 711       for (unsigned int i = 0; i < 3; i++) {
 712          src[i] = inst->get_src(i);
 713       }
 714       dst = inst->get_dst();
 715
 716       brw_set_conditionalmod(p, inst->conditional_mod);
 717       brw_set_predicate_control(p, inst->predicate);
 718       brw_set_predicate_inverse(p, inst->predicate_inverse);
 719       brw_set_saturate(p, inst->saturate);
 720
 721       switch (inst->opcode) {
 722       case BRW_OPCODE_MOV:
 723          brw_MOV(p, dst, src[0]);
 724          break;
 725       case BRW_OPCODE_ADD:
 726          brw_ADD(p, dst, src[0], src[1]);
 727          break;
 728       case BRW_OPCODE_MUL:
 729          brw_MUL(p, dst, src[0], src[1]);
 730          break;
 731       case BRW_OPCODE_MACH:
 732          brw_set_acc_write_control(p, 1);
 733          brw_MACH(p, dst, src[0], src[1]);
 734          brw_set_acc_write_control(p, 0);
 735          break;
 736
 737       case BRW_OPCODE_FRC:
 738          brw_FRC(p, dst, src[0]);
 739          break;
 740       case BRW_OPCODE_RNDD:
 741          brw_RNDD(p, dst, src[0]);
 742          break;
 743       case BRW_OPCODE_RNDE:
 744          brw_RNDE(p, dst, src[0]);
 745          break;
 746       case BRW_OPCODE_RNDZ:
 747          brw_RNDZ(p, dst, src[0]);
 748          break;
 749
 750       case BRW_OPCODE_AND:
 751          brw_AND(p, dst, src[0], src[1]);
 752          break;
 753       case BRW_OPCODE_OR:
 754          brw_OR(p, dst, src[0], src[1]);
 755          break;
 756       case BRW_OPCODE_XOR:
 757          brw_XOR(p, dst, src[0], src[1]);
 758          break;
 759       case BRW_OPCODE_NOT:
 760          brw_NOT(p, dst, src[0]);
 761          break;
 762       case BRW_OPCODE_ASR:
 763          brw_ASR(p, dst, src[0], src[1]);
 764          break;
 765       case BRW_OPCODE_SHR:
 766          brw_SHR(p, dst, src[0], src[1]);
 767          break;
 768       case BRW_OPCODE_SHL:
 769          brw_SHL(p, dst, src[0], src[1]);
 770          break;
 771
 772       case BRW_OPCODE_CMP:
 773          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 774          break;
 775       case BRW_OPCODE_SEL:
 776          brw_SEL(p, dst, src[0], src[1]);
 777          break;
 778
 779       case BRW_OPCODE_DP4:
 780          brw_DP4(p, dst, src[0], src[1]);
 781          break;
 782
 783       case BRW_OPCODE_DP3:
 784          brw_DP3(p, dst, src[0], src[1]);
 785          break;
 786
 787       case BRW_OPCODE_DP2:
 788          brw_DP2(p, dst, src[0], src[1]);
 789          break;
 790
 791       case BRW_OPCODE_IF:
 792          if (inst->src[0].file != BAD_FILE) {
 793             /* The instruction has an embedded compare (only allowed on gen6) */
 794             assert(intel->gen == 6);
 795             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 796          } else {
 797             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 798             brw_inst->header.predicate_control = inst->predicate;
 799          }
 800          if_depth_in_loop[loop_stack_depth]++;
 801          break;
 802
 803       case BRW_OPCODE_ELSE:
 804          brw_ELSE(p);
 805          break;
 806       case BRW_OPCODE_ENDIF:
 807          brw_ENDIF(p);
 808          if_depth_in_loop[loop_stack_depth]--;
 809          break;
 810
 811       case BRW_OPCODE_DO:
 812          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 813          if (loop_stack_array_size <= loop_stack_depth) {
 814             loop_stack_array_size *= 2;
 815             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 816                                   loop_stack_array_size);
 817             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 818                                         loop_stack_array_size);
 819          }
 820          if_depth_in_loop[loop_stack_depth] = 0;
 821          break;
 822
 823       case BRW_OPCODE_BREAK:
 824          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 825          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 826          break;
 827       case BRW_OPCODE_CONTINUE:
 828          /* FINISHME: We need to write the loop instruction support still. */
 829          if (intel->gen >= 6)
 830             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 831          else
 832             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 833          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 834          break;
 835
 836       case BRW_OPCODE_WHILE: {
 837          struct brw_instruction *inst0, *inst1;
 838          GLuint br = 1;
 839
 840          if (intel->gen >= 5)
 841             br = 2;
 842
 843          assert(loop_stack_depth > 0);
 844          loop_stack_depth--;
 845          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 846          if (intel->gen < 6) {
 847             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 848             while (inst0 > loop_stack[loop_stack_depth]) {
 849                inst0--;
 850                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 851                    inst0->bits3.if_else.jump_count == 0) {
 852                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 853             }
 854                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 855                         inst0->bits3.if_else.jump_count == 0) {
 856                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 857                }
 858             }
 859          }
 860       }
 861          break;
 862
 863       default:
 864          generate_vs_instruction(inst, dst, src);
 865          break;
 866       }
 867
 868       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 869          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 870             if (0) {
 871                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 872                       ((uint32_t *)&p->store[i])[3],
 873                       ((uint32_t *)&p->store[i])[2],
 874                       ((uint32_t *)&p->store[i])[1],
 875                       ((uint32_t *)&p->store[i])[0]);
 876             }
 877             brw_disasm(stdout, &p->store[i], intel->gen);
 878          }
 879       }
 880
 881       last_native_inst = p->nr_insn;
 882    }
 883
 884    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 885       printf("\n");
 886    }
 887
 888    ralloc_free(loop_stack);
 889    ralloc_free(if_depth_in_loop);
 890
 891    brw_set_uip_jip(p);
 892
 893    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 894     * emit issues, it doesn't get the jump distances into the output,
 895     * which is often something we want to debug.  So this is here in
 896     * case you're doing that.
 897     */
 898    if (0) {
 899       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 900          for (unsigned int i = 0; i < p->nr_insn; i++) {
 901             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 902                    ((uint32_t *)&p->store[i])[3],
 903                    ((uint32_t *)&p->store[i])[2],
 904                    ((uint32_t *)&p->store[i])[1],
 905                    ((uint32_t *)&p->store[i])[0]);
 906             brw_disasm(stdout, &p->store[i], intel->gen);
 907          }
 908       }
 909    }
 910 }
 911
 912 extern "C" {
 913
 914 bool
 915 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
 916 {
 917    if (!prog)
 918       return false;
 919
 920    struct brw_shader *shader =
 921      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
 922    if (!shader)
 923       return false;
 924
 925    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 926       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
 927       _mesa_print_ir(shader->ir, NULL);
 928       printf("\n\n");
 929    }
 930
 931    vec4_visitor v(c, prog, shader);
 932    if (!v.run()) {
 933       prog->LinkStatus = false;
 934       ralloc_strcat(&prog->InfoLog, v.fail_msg);
 935       return false;
 936    }
 937
 938    return true;
 939 }
 940
 941 } /* extern "C" */
 942
 943 } /* namespace brw */