src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45       }
  46    }
  47
  48    foreach_list(node, &this->instructions) {
  49       vec4_instruction *inst = (vec4_instruction *)node;
  50
  51       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  52       if (inst->dst.file == ATTR) {
  53          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  54
  55          struct brw_reg reg = brw_vec8_grf(grf, 0);
  56          reg.dw1.bits.writemask = inst->dst.writemask;
  57
  58          inst->dst.file = HW_REG;
  59          inst->dst.fixed_hw_reg = reg;
  60       }
  61
  62       for (int i = 0; i < 3; i++) {
  63          if (inst->src[i].file != ATTR)
  64             continue;
  65
  66          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  67
  68          struct brw_reg reg = brw_vec8_grf(grf, 0);
  69          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  70          reg.type = inst->src[i].type;
  71          if (inst->src[i].abs)
  72             reg = brw_abs(reg);
  73          if (inst->src[i].negate)
  74             reg = negate(reg);
  75
  76          inst->src[i].file = HW_REG;
  77          inst->src[i].fixed_hw_reg = reg;
  78       }
  79    }
  80
  81    /* The BSpec says we always have to read at least one thing from
  82     * the VF, and it appears that the hardware wedges otherwise.
  83     */
  84    if (nr_attributes == 0)
  85       nr_attributes = 1;
  86
  87    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  88
  89    return payload_reg + nr_attributes;
  90 }
  91
  92 int
  93 vec4_visitor::setup_uniforms(int reg)
  94 {
  95    /* The pre-gen6 VS requires that some push constants get loaded no
  96     * matter what, or the GPU would hang.
  97     */
  98    if (intel->gen < 6 && this->uniforms == 0) {
  99       this->uniform_vector_size[this->uniforms] = 1;
 100
 101       for (unsigned int i = 0; i < 4; i++) {
 102          unsigned int slot = this->uniforms * 4 + i;
 103          static float zero = 0.0;
 104          c->prog_data.param[slot] = &zero;
 105       }
 106
 107       this->uniforms++;
 108       reg++;
 109    } else {
 110       reg += ALIGN(uniforms, 2) / 2;
 111    }
 112
 113    c->prog_data.nr_params = this->uniforms * 4;
 114
 115    c->prog_data.curb_read_length = reg - 1;
 116    c->prog_data.uses_new_param_layout = true;
 117
 118    return reg;
 119 }
 120
 121 void
 122 vec4_visitor::setup_payload(void)
 123 {
 124    int reg = 0;
 125
 126    /* The payload always contains important data in g0, which contains
 127     * the URB handles that are passed on to the URB write at the end
 128     * of the thread.  So, we always start push constants at g1.
 129     */
 130    reg++;
 131
 132    reg = setup_uniforms(reg);
 133
 134    reg = setup_attributes(reg);
 135
 136    this->first_non_payload_grf = reg;
 137 }
 138
 139 struct brw_reg
 140 vec4_instruction::get_dst(void)
 141 {
 142    struct brw_reg brw_reg;
 143
 144    switch (dst.file) {
 145    case GRF:
 146       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 147       brw_reg = retype(brw_reg, dst.type);
 148       brw_reg.dw1.bits.writemask = dst.writemask;
 149       break;
 150
 151    case MRF:
 152       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 153       brw_reg = retype(brw_reg, dst.type);
 154       brw_reg.dw1.bits.writemask = dst.writemask;
 155       break;
 156
 157    case HW_REG:
 158       brw_reg = dst.fixed_hw_reg;
 159       break;
 160
 161    case BAD_FILE:
 162       brw_reg = brw_null_reg();
 163       break;
 164
 165    default:
 166       assert(!"not reached");
 167       brw_reg = brw_null_reg();
 168       break;
 169    }
 170    return brw_reg;
 171 }
 172
 173 struct brw_reg
 174 vec4_instruction::get_src(int i)
 175 {
 176    struct brw_reg brw_reg;
 177
 178    switch (src[i].file) {
 179    case GRF:
 180       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 181       brw_reg = retype(brw_reg, src[i].type);
 182       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 183       if (src[i].abs)
 184          brw_reg = brw_abs(brw_reg);
 185       if (src[i].negate)
 186          brw_reg = negate(brw_reg);
 187       break;
 188
 189    case IMM:
 190       switch (src[i].type) {
 191       case BRW_REGISTER_TYPE_F:
 192          brw_reg = brw_imm_f(src[i].imm.f);
 193          break;
 194       case BRW_REGISTER_TYPE_D:
 195          brw_reg = brw_imm_d(src[i].imm.i);
 196          break;
 197       case BRW_REGISTER_TYPE_UD:
 198          brw_reg = brw_imm_ud(src[i].imm.u);
 199          break;
 200       default:
 201          assert(!"not reached");
 202          brw_reg = brw_null_reg();
 203          break;
 204       }
 205       break;
 206
 207    case UNIFORM:
 208       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 209                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 210                        0, 4, 1);
 211       brw_reg = retype(brw_reg, src[i].type);
 212       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 213       if (src[i].abs)
 214          brw_reg = brw_abs(brw_reg);
 215       if (src[i].negate)
 216          brw_reg = negate(brw_reg);
 217
 218       /* This should have been moved to pull constants. */
 219       assert(!src[i].reladdr);
 220       break;
 221
 222    case HW_REG:
 223       brw_reg = src[i].fixed_hw_reg;
 224       break;
 225
 226    case BAD_FILE:
 227       /* Probably unused. */
 228       brw_reg = brw_null_reg();
 229       break;
 230    case ATTR:
 231    default:
 232       assert(!"not reached");
 233       brw_reg = brw_null_reg();
 234       break;
 235    }
 236
 237    return brw_reg;
 238 }
 239
 240 void
 241 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 242                                   struct brw_reg dst,
 243                                   struct brw_reg src)
 244 {
 245    brw_math(p,
 246             dst,
 247             brw_math_function(inst->opcode),
 248             BRW_MATH_SATURATE_NONE,
 249             inst->base_mrf,
 250             src,
 251             BRW_MATH_DATA_VECTOR,
 252             BRW_MATH_PRECISION_FULL);
 253 }
 254
 255 static void
 256 check_gen6_math_src_arg(struct brw_reg src)
 257 {
 258    /* Source swizzles are ignored. */
 259    assert(!src.abs);
 260    assert(!src.negate);
 261    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 262 }
 263
 264 void
 265 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 266                                   struct brw_reg dst,
 267                                   struct brw_reg src)
 268 {
 269    /* Can't do writemask because math can't be align16. */
 270    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 271    check_gen6_math_src_arg(src);
 272
 273    brw_set_access_mode(p, BRW_ALIGN_1);
 274    brw_math(p,
 275             dst,
 276             brw_math_function(inst->opcode),
 277             BRW_MATH_SATURATE_NONE,
 278             inst->base_mrf,
 279             src,
 280             BRW_MATH_DATA_SCALAR,
 281             BRW_MATH_PRECISION_FULL);
 282    brw_set_access_mode(p, BRW_ALIGN_16);
 283 }
 284
 285 void
 286 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 287                                   struct brw_reg dst,
 288                                   struct brw_reg src0,
 289                                   struct brw_reg src1)
 290 {
 291    /* Can't do writemask because math can't be align16. */
 292    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 293    /* Source swizzles are ignored. */
 294    check_gen6_math_src_arg(src0);
 295    check_gen6_math_src_arg(src1);
 296
 297    brw_set_access_mode(p, BRW_ALIGN_1);
 298    brw_math2(p,
 299              dst,
 300              brw_math_function(inst->opcode),
 301              src0, src1);
 302    brw_set_access_mode(p, BRW_ALIGN_16);
 303 }
 304
 305 void
 306 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 307                                   struct brw_reg dst,
 308                                   struct brw_reg src0,
 309                                   struct brw_reg src1)
 310 {
 311    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 312     * "Message Payload":
 313     *
 314     * "Operand0[7].  For the INT DIV functions, this operand is the
 315     *  denominator."
 316     *  ...
 317     * "Operand1[7].  For the INT DIV functions, this operand is the
 318     *  numerator."
 319     */
 320    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 321    struct brw_reg &op0 = is_int_div ? src1 : src0;
 322    struct brw_reg &op1 = is_int_div ? src0 : src1;
 323
 324    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 325
 326    brw_math(p,
 327             dst,
 328             brw_math_function(inst->opcode),
 329             BRW_MATH_SATURATE_NONE,
 330             inst->base_mrf,
 331             op0,
 332             BRW_MATH_DATA_VECTOR,
 333             BRW_MATH_PRECISION_FULL);
 334 }
 335
 336 void
 337 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 338 {
 339    brw_urb_WRITE(p,
 340                  brw_null_reg(), /* dest */
 341                  inst->base_mrf, /* starting mrf reg nr */
 342                  brw_vec8_grf(0, 0), /* src */
 343                  false,         /* allocate */
 344                  true,          /* used */
 345                  inst->mlen,
 346                  0,             /* response len */
 347                  inst->eot,     /* eot */
 348                  inst->eot,     /* writes complete */
 349                  inst->offset,  /* urb destination offset */
 350                  BRW_URB_SWIZZLE_INTERLEAVE);
 351 }
 352
 353 void
 354 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 355                                                 struct brw_reg index)
 356 {
 357    int second_vertex_offset;
 358
 359    if (intel->gen >= 6)
 360       second_vertex_offset = 1;
 361    else
 362       second_vertex_offset = 16;
 363
 364    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 365
 366    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 367     * M1.4 are used, and the rest are ignored.
 368     */
 369    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 370    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 371    struct brw_reg index_0 = suboffset(vec1(index), 0);
 372    struct brw_reg index_4 = suboffset(vec1(index), 4);
 373
 374    brw_push_insn_state(p);
 375    brw_set_mask_control(p, BRW_MASK_DISABLE);
 376    brw_set_access_mode(p, BRW_ALIGN_1);
 377
 378    brw_MOV(p, m1_0, index_0);
 379
 380    brw_set_predicate_inverse(p, true);
 381    if (index.file == BRW_IMMEDIATE_VALUE) {
 382       index_4.dw1.ud += second_vertex_offset;
 383       brw_MOV(p, m1_4, index_4);
 384    } else {
 385       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 386    }
 387
 388    brw_pop_insn_state(p);
 389 }
 390
 391 void
 392 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 393                                     struct brw_reg dst,
 394                                     struct brw_reg index)
 395 {
 396    struct brw_reg header = brw_vec8_grf(0, 0);
 397
 398    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 399
 400    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 401                                      index);
 402
 403    uint32_t msg_type;
 404
 405    if (intel->gen >= 6)
 406       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 407    else if (intel->gen == 5 || intel->is_g4x)
 408       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 409    else
 410       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 411
 412    /* Each of the 8 channel enables is considered for whether each
 413     * dword is written.
 414     */
 415    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 416    brw_set_dest(p, send, dst);
 417    brw_set_src0(p, send, header);
 418    if (intel->gen < 6)
 419       send->header.destreg__conditionalmod = inst->base_mrf;
 420    brw_set_dp_read_message(p, send,
 421                            255, /* binding table index: stateless access */
 422                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 423                            msg_type,
 424                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 425                            2, /* mlen */
 426                            1 /* rlen */);
 427 }
 428
 429 void
 430 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 431                                      struct brw_reg dst,
 432                                      struct brw_reg src,
 433                                      struct brw_reg index)
 434 {
 435    struct brw_reg header = brw_vec8_grf(0, 0);
 436    bool write_commit;
 437
 438    /* If the instruction is predicated, we'll predicate the send, not
 439     * the header setup.
 440     */
 441    brw_set_predicate_control(p, false);
 442
 443    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 444
 445    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 446                                      index);
 447
 448    brw_MOV(p,
 449            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 450            retype(src, BRW_REGISTER_TYPE_D));
 451
 452    uint32_t msg_type;
 453
 454    if (intel->gen >= 7)
 455       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 456    else if (intel->gen == 6)
 457       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 458    else
 459       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 460
 461    brw_set_predicate_control(p, inst->predicate);
 462
 463    /* Pre-gen6, we have to specify write commits to ensure ordering
 464     * between reads and writes within a thread.  Afterwards, that's
 465     * guaranteed and write commits only matter for inter-thread
 466     * synchronization.
 467     */
 468    if (intel->gen >= 6) {
 469       write_commit = false;
 470    } else {
 471       /* The visitor set up our destination register to be g0.  This
 472        * means that when the next read comes along, we will end up
 473        * reading from g0 and causing a block on the write commit.  For
 474        * write-after-read, we are relying on the value of the previous
 475        * read being used (and thus blocking on completion) before our
 476        * write is executed.  This means we have to be careful in
 477        * instruction scheduling to not violate this assumption.
 478        */
 479       write_commit = true;
 480    }
 481
 482    /* Each of the 8 channel enables is considered for whether each
 483     * dword is written.
 484     */
 485    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 486    brw_set_dest(p, send, dst);
 487    brw_set_src0(p, send, header);
 488    if (intel->gen < 6)
 489       send->header.destreg__conditionalmod = inst->base_mrf;
 490    brw_set_dp_write_message(p, send,
 491                             255, /* binding table index: stateless access */
 492                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 493                             msg_type,
 494                             3, /* mlen */
 495                             true, /* header present */
 496                             false, /* not a render target write */
 497                             write_commit, /* rlen */
 498                             false, /* eot */
 499                             write_commit);
 500 }
 501
 502 void
 503 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 504                                           struct brw_reg dst,
 505                                           struct brw_reg index)
 506 {
 507    struct brw_reg header = brw_vec8_grf(0, 0);
 508
 509    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 510
 511    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 512            index);
 513
 514    uint32_t msg_type;
 515
 516    if (intel->gen >= 6)
 517       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 518    else if (intel->gen == 5 || intel->is_g4x)
 519       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 520    else
 521       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 522
 523    /* Each of the 8 channel enables is considered for whether each
 524     * dword is written.
 525     */
 526    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 527    brw_set_dest(p, send, dst);
 528    brw_set_src0(p, send, header);
 529    if (intel->gen < 6)
 530       send->header.destreg__conditionalmod = inst->base_mrf;
 531    brw_set_dp_read_message(p, send,
 532                            SURF_INDEX_VERT_CONST_BUFFER,
 533                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 534                            msg_type,
 535                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 536                            2, /* mlen */
 537                            1 /* rlen */);
 538 }
 539
 540 void
 541 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 542                                       struct brw_reg dst,
 543                                       struct brw_reg *src)
 544 {
 545    vec4_instruction *inst = (vec4_instruction *)instruction;
 546
 547    switch (inst->opcode) {
 548    case SHADER_OPCODE_RCP:
 549    case SHADER_OPCODE_RSQ:
 550    case SHADER_OPCODE_SQRT:
 551    case SHADER_OPCODE_EXP2:
 552    case SHADER_OPCODE_LOG2:
 553    case SHADER_OPCODE_SIN:
 554    case SHADER_OPCODE_COS:
 555       if (intel->gen >= 6) {
 556          generate_math1_gen6(inst, dst, src[0]);
 557       } else {
 558          generate_math1_gen4(inst, dst, src[0]);
 559       }
 560       break;
 561
 562    case SHADER_OPCODE_POW:
 563    case SHADER_OPCODE_INT_QUOTIENT:
 564    case SHADER_OPCODE_INT_REMAINDER:
 565       if (intel->gen >= 6) {
 566          generate_math2_gen6(inst, dst, src[0], src[1]);
 567       } else {
 568          generate_math2_gen4(inst, dst, src[0], src[1]);
 569       }
 570       break;
 571
 572    case VS_OPCODE_URB_WRITE:
 573       generate_urb_write(inst);
 574       break;
 575
 576    case VS_OPCODE_SCRATCH_READ:
 577       generate_scratch_read(inst, dst, src[0]);
 578       break;
 579
 580    case VS_OPCODE_SCRATCH_WRITE:
 581       generate_scratch_write(inst, dst, src[0], src[1]);
 582       break;
 583
 584    case VS_OPCODE_PULL_CONSTANT_LOAD:
 585       generate_pull_constant_load(inst, dst, src[0]);
 586       break;
 587
 588    default:
 589       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 590          fail("unsupported opcode in `%s' in VS\n",
 591               brw_opcodes[inst->opcode].name);
 592       } else {
 593          fail("Unsupported opcode %d in VS", inst->opcode);
 594       }
 595    }
 596 }
 597
 598 bool
 599 vec4_visitor::run()
 600 {
 601    if (c->key.userclip_active && !c->key.uses_clip_distance)
 602       setup_uniform_clipplane_values();
 603
 604    /* Generate VS IR for main().  (the visitor only descends into
 605     * functions called "main").
 606     */
 607    visit_instructions(shader->ir);
 608
 609    emit_urb_writes();
 610
 611    /* Before any optimization, push array accesses out to scratch
 612     * space where we need them to be.  This pass may allocate new
 613     * virtual GRFs, so we want to do it early.  It also makes sure
 614     * that we have reladdr computations available for CSE, since we'll
 615     * often do repeated subexpressions for those.
 616     */
 617    move_grf_array_access_to_scratch();
 618    move_uniform_array_access_to_pull_constants();
 619    pack_uniform_registers();
 620    move_push_constants_to_pull_constants();
 621
 622    bool progress;
 623    do {
 624       progress = false;
 625       progress = dead_code_eliminate() || progress;
 626       progress = opt_copy_propagation() || progress;
 627       progress = opt_algebraic() || progress;
 628       progress = opt_compute_to_mrf() || progress;
 629    } while (progress);
 630
 631
 632    if (failed)
 633       return false;
 634
 635    setup_payload();
 636    reg_allocate();
 637
 638    if (failed)
 639       return false;
 640
 641    brw_set_access_mode(p, BRW_ALIGN_16);
 642
 643    generate_code();
 644
 645    return !failed;
 646 }
 647
 648 void
 649 vec4_visitor::generate_code()
 650 {
 651    int last_native_inst = 0;
 652    const char *last_annotation_string = NULL;
 653    ir_instruction *last_annotation_ir = NULL;
 654
 655    int loop_stack_array_size = 16;
 656    int loop_stack_depth = 0;
 657    brw_instruction **loop_stack =
 658       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 659    int *if_depth_in_loop =
 660       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 661
 662
 663    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 664       printf("Native code for vertex shader %d:\n", prog->Name);
 665    }
 666
 667    foreach_list(node, &this->instructions) {
 668       vec4_instruction *inst = (vec4_instruction *)node;
 669       struct brw_reg src[3], dst;
 670
 671       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 672          if (last_annotation_ir != inst->ir) {
 673             last_annotation_ir = inst->ir;
 674             if (last_annotation_ir) {
 675                printf("   ");
 676                last_annotation_ir->print();
 677                printf("\n");
 678             }
 679          }
 680          if (last_annotation_string != inst->annotation) {
 681             last_annotation_string = inst->annotation;
 682             if (last_annotation_string)
 683                printf("   %s\n", last_annotation_string);
 684          }
 685       }
 686
 687       for (unsigned int i = 0; i < 3; i++) {
 688          src[i] = inst->get_src(i);
 689       }
 690       dst = inst->get_dst();
 691
 692       brw_set_conditionalmod(p, inst->conditional_mod);
 693       brw_set_predicate_control(p, inst->predicate);
 694       brw_set_predicate_inverse(p, inst->predicate_inverse);
 695       brw_set_saturate(p, inst->saturate);
 696
 697       switch (inst->opcode) {
 698       case BRW_OPCODE_MOV:
 699          brw_MOV(p, dst, src[0]);
 700          break;
 701       case BRW_OPCODE_ADD:
 702          brw_ADD(p, dst, src[0], src[1]);
 703          break;
 704       case BRW_OPCODE_MUL:
 705          brw_MUL(p, dst, src[0], src[1]);
 706          break;
 707       case BRW_OPCODE_MACH:
 708          brw_set_acc_write_control(p, 1);
 709          brw_MACH(p, dst, src[0], src[1]);
 710          brw_set_acc_write_control(p, 0);
 711          break;
 712
 713       case BRW_OPCODE_FRC:
 714          brw_FRC(p, dst, src[0]);
 715          break;
 716       case BRW_OPCODE_RNDD:
 717          brw_RNDD(p, dst, src[0]);
 718          break;
 719       case BRW_OPCODE_RNDE:
 720          brw_RNDE(p, dst, src[0]);
 721          break;
 722       case BRW_OPCODE_RNDZ:
 723          brw_RNDZ(p, dst, src[0]);
 724          break;
 725
 726       case BRW_OPCODE_AND:
 727          brw_AND(p, dst, src[0], src[1]);
 728          break;
 729       case BRW_OPCODE_OR:
 730          brw_OR(p, dst, src[0], src[1]);
 731          break;
 732       case BRW_OPCODE_XOR:
 733          brw_XOR(p, dst, src[0], src[1]);
 734          break;
 735       case BRW_OPCODE_NOT:
 736          brw_NOT(p, dst, src[0]);
 737          break;
 738       case BRW_OPCODE_ASR:
 739          brw_ASR(p, dst, src[0], src[1]);
 740          break;
 741       case BRW_OPCODE_SHR:
 742          brw_SHR(p, dst, src[0], src[1]);
 743          break;
 744       case BRW_OPCODE_SHL:
 745          brw_SHL(p, dst, src[0], src[1]);
 746          break;
 747
 748       case BRW_OPCODE_CMP:
 749          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 750          break;
 751       case BRW_OPCODE_SEL:
 752          brw_SEL(p, dst, src[0], src[1]);
 753          break;
 754
 755       case BRW_OPCODE_DP4:
 756          brw_DP4(p, dst, src[0], src[1]);
 757          break;
 758
 759       case BRW_OPCODE_DP3:
 760          brw_DP3(p, dst, src[0], src[1]);
 761          break;
 762
 763       case BRW_OPCODE_DP2:
 764          brw_DP2(p, dst, src[0], src[1]);
 765          break;
 766
 767       case BRW_OPCODE_IF:
 768          if (inst->src[0].file != BAD_FILE) {
 769             /* The instruction has an embedded compare (only allowed on gen6) */
 770             assert(intel->gen == 6);
 771             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 772          } else {
 773             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 774             brw_inst->header.predicate_control = inst->predicate;
 775          }
 776          if_depth_in_loop[loop_stack_depth]++;
 777          break;
 778
 779       case BRW_OPCODE_ELSE:
 780          brw_ELSE(p);
 781          break;
 782       case BRW_OPCODE_ENDIF:
 783          brw_ENDIF(p);
 784          if_depth_in_loop[loop_stack_depth]--;
 785          break;
 786
 787       case BRW_OPCODE_DO:
 788          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 789          if (loop_stack_array_size <= loop_stack_depth) {
 790             loop_stack_array_size *= 2;
 791             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 792                                   loop_stack_array_size);
 793             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 794                                         loop_stack_array_size);
 795          }
 796          if_depth_in_loop[loop_stack_depth] = 0;
 797          break;
 798
 799       case BRW_OPCODE_BREAK:
 800          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 801          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 802          break;
 803       case BRW_OPCODE_CONTINUE:
 804          /* FINISHME: We need to write the loop instruction support still. */
 805          if (intel->gen >= 6)
 806             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 807          else
 808             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 809          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 810          break;
 811
 812       case BRW_OPCODE_WHILE: {
 813          struct brw_instruction *inst0, *inst1;
 814          GLuint br = 1;
 815
 816          if (intel->gen >= 5)
 817             br = 2;
 818
 819          assert(loop_stack_depth > 0);
 820          loop_stack_depth--;
 821          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 822          if (intel->gen < 6) {
 823             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 824             while (inst0 > loop_stack[loop_stack_depth]) {
 825                inst0--;
 826                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 827                    inst0->bits3.if_else.jump_count == 0) {
 828                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 829             }
 830                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 831                         inst0->bits3.if_else.jump_count == 0) {
 832                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 833                }
 834             }
 835          }
 836       }
 837          break;
 838
 839       default:
 840          generate_vs_instruction(inst, dst, src);
 841          break;
 842       }
 843
 844       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 845          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 846             if (0) {
 847                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 848                       ((uint32_t *)&p->store[i])[3],
 849                       ((uint32_t *)&p->store[i])[2],
 850                       ((uint32_t *)&p->store[i])[1],
 851                       ((uint32_t *)&p->store[i])[0]);
 852             }
 853             brw_disasm(stdout, &p->store[i], intel->gen);
 854          }
 855       }
 856
 857       last_native_inst = p->nr_insn;
 858    }
 859
 860    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 861       printf("\n");
 862    }
 863
 864    ralloc_free(loop_stack);
 865    ralloc_free(if_depth_in_loop);
 866
 867    brw_set_uip_jip(p);
 868
 869    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 870     * emit issues, it doesn't get the jump distances into the output,
 871     * which is often something we want to debug.  So this is here in
 872     * case you're doing that.
 873     */
 874    if (0) {
 875       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 876          for (unsigned int i = 0; i < p->nr_insn; i++) {
 877             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 878                    ((uint32_t *)&p->store[i])[3],
 879                    ((uint32_t *)&p->store[i])[2],
 880                    ((uint32_t *)&p->store[i])[1],
 881                    ((uint32_t *)&p->store[i])[0]);
 882             brw_disasm(stdout, &p->store[i], intel->gen);
 883          }
 884       }
 885    }
 886 }
 887
 888 extern "C" {
 889
 890 bool
 891 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
 892 {
 893    if (!prog)
 894       return false;
 895
 896    struct brw_shader *shader =
 897      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
 898    if (!shader)
 899       return false;
 900
 901    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 902       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
 903       _mesa_print_ir(shader->ir, NULL);
 904       printf("\n\n");
 905    }
 906
 907    vec4_visitor v(c, prog, shader);
 908    if (!v.run()) {
 909       prog->LinkStatus = false;
 910       ralloc_strcat(&prog->InfoLog, v.fail_msg);
 911       return false;
 912    }
 913
 914    return true;
 915 }
 916
 917 } /* extern "C" */
 918
 919 } /* namespace brw */