src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 };
  29
  30 using namespace brw;
  31
  32 namespace brw {
  33
  34 int
  35 vec4_visitor::setup_attributes(int payload_reg)
  36 {
  37    int nr_attributes;
  38    int attribute_map[VERT_ATTRIB_MAX];
  39
  40    nr_attributes = 0;
  41    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  42       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  43          attribute_map[i] = payload_reg + nr_attributes;
  44          nr_attributes++;
  45
  46          /* Do GL_FIXED rescaling for GLES2.0.  Our GL_FIXED
  47           * attributes come in as floating point conversions of the
  48           * integer values.
  49           */
  50          if (c->key.gl_fixed_input_size[i] != 0) {
  51             struct brw_reg reg = brw_vec8_grf(attribute_map[i], 0);
  52
  53             brw_MUL(p,
  54                     brw_writemask(reg, (1 << c->key.gl_fixed_input_size[i]) - 1),
  55                     reg, brw_imm_f(1.0 / 65536.0));
  56          }
  57       }
  58    }
  59
  60    foreach_list(node, &this->instructions) {
  61       vec4_instruction *inst = (vec4_instruction *)node;
  62
  63       for (int i = 0; i < 3; i++) {
  64          if (inst->src[i].file != ATTR)
  65             continue;
  66
  67          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  68
  69          struct brw_reg reg = brw_vec8_grf(grf, 0);
  70          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  71          if (inst->src[i].abs)
  72             reg = brw_abs(reg);
  73          if (inst->src[i].negate)
  74             reg = negate(reg);
  75
  76          inst->src[i].file = HW_REG;
  77          inst->src[i].fixed_hw_reg = reg;
  78       }
  79    }
  80
  81    /* The BSpec says we always have to read at least one thing from
  82     * the VF, and it appears that the hardware wedges otherwise.
  83     */
  84    if (nr_attributes == 0)
  85       nr_attributes = 1;
  86
  87    prog_data->urb_read_length = (nr_attributes + 1) / 2;
  88
  89    return payload_reg + nr_attributes;
  90 }
  91
  92 int
  93 vec4_visitor::setup_uniforms(int reg)
  94 {
  95    /* User clip planes from curbe:
  96     */
  97    if (c->key.nr_userclip) {
  98       if (intel->gen >= 6) {
  99          for (int i = 0; i < c->key.nr_userclip; i++) {
 100             c->userplane[i] = stride(brw_vec4_grf(reg + i / 2,
 101                                                   (i % 2) * 4), 0, 4, 1);
 102          }
 103          reg += ALIGN(c->key.nr_userclip, 2) / 2;
 104       } else {
 105          for (int i = 0; i < c->key.nr_userclip; i++) {
 106             c->userplane[i] = stride(brw_vec4_grf(reg + (6 + i) / 2,
 107                                                   (i % 2) * 4), 0, 4, 1);
 108          }
 109          reg += (ALIGN(6 + c->key.nr_userclip, 4) / 4) * 2;
 110       }
 111    }
 112
 113    /* The pre-gen6 VS requires that some push constants get loaded no
 114     * matter what, or the GPU would hang.
 115     */
 116    if (intel->gen < 6 && this->uniforms == 0) {
 117       this->uniform_vector_size[this->uniforms] = 1;
 118
 119       for (unsigned int i = 0; i < 4; i++) {
 120          unsigned int slot = this->uniforms * 4 + i;
 121
 122          c->prog_data.param[slot] = NULL;
 123       }
 124
 125       this->uniforms++;
 126       reg++;
 127    } else {
 128       reg += ALIGN(uniforms, 2) / 2;
 129    }
 130
 131    /* for now, we are not doing any elimination of unused slots, nor
 132     * are we packing our uniforms.
 133     */
 134    c->prog_data.nr_params = this->uniforms * 4;
 135
 136    c->prog_data.curb_read_length = reg - 1;
 137    c->prog_data.uses_new_param_layout = true;
 138
 139    return reg;
 140 }
 141
 142 void
 143 vec4_visitor::setup_payload(void)
 144 {
 145    int reg = 0;
 146
 147    /* The payload always contains important data in g0, which contains
 148     * the URB handles that are passed on to the URB write at the end
 149     * of the thread.  So, we always start push constants at g1.
 150     */
 151    reg++;
 152
 153    reg = setup_uniforms(reg);
 154
 155    reg = setup_attributes(reg);
 156
 157    this->first_non_payload_grf = reg;
 158 }
 159
 160 struct brw_reg
 161 vec4_instruction::get_dst(void)
 162 {
 163    struct brw_reg brw_reg;
 164
 165    switch (dst.file) {
 166    case GRF:
 167       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 168       brw_reg = retype(brw_reg, dst.type);
 169       brw_reg.dw1.bits.writemask = dst.writemask;
 170       break;
 171
 172    case HW_REG:
 173       brw_reg = dst.fixed_hw_reg;
 174       break;
 175
 176    case BAD_FILE:
 177       brw_reg = brw_null_reg();
 178       break;
 179
 180    default:
 181       assert(!"not reached");
 182       brw_reg = brw_null_reg();
 183       break;
 184    }
 185    return brw_reg;
 186 }
 187
 188 struct brw_reg
 189 vec4_instruction::get_src(int i)
 190 {
 191    struct brw_reg brw_reg;
 192
 193    switch (src[i].file) {
 194    case GRF:
 195       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 196       brw_reg = retype(brw_reg, src[i].type);
 197       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 198       if (src[i].abs)
 199          brw_reg = brw_abs(brw_reg);
 200       if (src[i].negate)
 201          brw_reg = negate(brw_reg);
 202       break;
 203
 204    case IMM:
 205       switch (src[i].type) {
 206       case BRW_REGISTER_TYPE_F:
 207          brw_reg = brw_imm_f(src[i].imm.f);
 208          break;
 209       case BRW_REGISTER_TYPE_D:
 210          brw_reg = brw_imm_d(src[i].imm.i);
 211          break;
 212       case BRW_REGISTER_TYPE_UD:
 213          brw_reg = brw_imm_ud(src[i].imm.u);
 214          break;
 215       default:
 216          assert(!"not reached");
 217          brw_reg = brw_null_reg();
 218          break;
 219       }
 220       break;
 221
 222    case UNIFORM:
 223       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 224                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 225                        0, 4, 1);
 226       brw_reg = retype(brw_reg, src[i].type);
 227       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 228       if (src[i].abs)
 229          brw_reg = brw_abs(brw_reg);
 230       if (src[i].negate)
 231          brw_reg = negate(brw_reg);
 232
 233       /* This should have been moved to pull constants. */
 234       assert(!src[i].reladdr);
 235       break;
 236
 237    case HW_REG:
 238       brw_reg = src[i].fixed_hw_reg;
 239       break;
 240
 241    case BAD_FILE:
 242       /* Probably unused. */
 243       brw_reg = brw_null_reg();
 244       break;
 245    case ATTR:
 246    default:
 247       assert(!"not reached");
 248       brw_reg = brw_null_reg();
 249       break;
 250    }
 251
 252    return brw_reg;
 253 }
 254
 255 void
 256 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 257                                   struct brw_reg dst,
 258                                   struct brw_reg src)
 259 {
 260    brw_math(p,
 261             dst,
 262             brw_math_function(inst->opcode),
 263             BRW_MATH_SATURATE_NONE,
 264             inst->base_mrf,
 265             src,
 266             BRW_MATH_DATA_SCALAR,
 267             BRW_MATH_PRECISION_FULL);
 268 }
 269
 270 static void
 271 check_gen6_math_src_arg(struct brw_reg src)
 272 {
 273    /* Source swizzles are ignored. */
 274    assert(!src.abs);
 275    assert(!src.negate);
 276    assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW);
 277 }
 278
 279 void
 280 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 281                                   struct brw_reg dst,
 282                                   struct brw_reg src)
 283 {
 284    /* Can't do writemask because math can't be align16. */
 285    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 286    check_gen6_math_src_arg(src);
 287
 288    brw_set_access_mode(p, BRW_ALIGN_1);
 289    brw_math(p,
 290             dst,
 291             brw_math_function(inst->opcode),
 292             BRW_MATH_SATURATE_NONE,
 293             inst->base_mrf,
 294             src,
 295             BRW_MATH_DATA_SCALAR,
 296             BRW_MATH_PRECISION_FULL);
 297    brw_set_access_mode(p, BRW_ALIGN_16);
 298 }
 299
 300 void
 301 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 302                                   struct brw_reg dst,
 303                                   struct brw_reg src0,
 304                                   struct brw_reg src1)
 305 {
 306    /* Can't do writemask because math can't be align16. */
 307    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 308    /* Source swizzles are ignored. */
 309    check_gen6_math_src_arg(src0);
 310    check_gen6_math_src_arg(src1);
 311
 312    brw_set_access_mode(p, BRW_ALIGN_1);
 313    brw_math2(p,
 314              dst,
 315              brw_math_function(inst->opcode),
 316              src0, src1);
 317    brw_set_access_mode(p, BRW_ALIGN_16);
 318 }
 319
 320 void
 321 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 322                                   struct brw_reg dst,
 323                                   struct brw_reg src0,
 324                                   struct brw_reg src1)
 325 {
 326    /* Can't do writemask because math can't be align16. */
 327    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 328
 329    brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src1);
 330
 331    brw_set_access_mode(p, BRW_ALIGN_1);
 332    brw_math(p,
 333             dst,
 334             brw_math_function(inst->opcode),
 335             BRW_MATH_SATURATE_NONE,
 336             inst->base_mrf,
 337             src0,
 338             BRW_MATH_DATA_VECTOR,
 339             BRW_MATH_PRECISION_FULL);
 340    brw_set_access_mode(p, BRW_ALIGN_16);
 341 }
 342
 343 void
 344 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 345 {
 346    brw_urb_WRITE(p,
 347                  brw_null_reg(), /* dest */
 348                  inst->base_mrf, /* starting mrf reg nr */
 349                  brw_vec8_grf(0, 0), /* src */
 350                  false,         /* allocate */
 351                  true,          /* used */
 352                  inst->mlen,
 353                  0,             /* response len */
 354                  inst->eot,     /* eot */
 355                  inst->eot,     /* writes complete */
 356                  inst->offset,  /* urb destination offset */
 357                  BRW_URB_SWIZZLE_INTERLEAVE);
 358 }
 359
 360 void
 361 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 362                                                 struct brw_reg index)
 363 {
 364    int second_vertex_offset;
 365
 366    if (intel->gen >= 6)
 367       second_vertex_offset = 1;
 368    else
 369       second_vertex_offset = 16;
 370
 371    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 372
 373    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 374     * M1.4 are used, and the rest are ignored.
 375     */
 376    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 377    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 378    struct brw_reg index_0 = suboffset(vec1(index), 0);
 379    struct brw_reg index_4 = suboffset(vec1(index), 4);
 380
 381    brw_push_insn_state(p);
 382    brw_set_mask_control(p, BRW_MASK_DISABLE);
 383    brw_set_access_mode(p, BRW_ALIGN_1);
 384
 385    brw_MOV(p, m1_0, index_0);
 386
 387    brw_set_predicate_inverse(p, true);
 388    if (index.file == BRW_IMMEDIATE_VALUE) {
 389       index_4.dw1.ud++;
 390       brw_MOV(p, m1_4, index_4);
 391    } else {
 392       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 393    }
 394
 395    brw_pop_insn_state(p);
 396 }
 397
 398 void
 399 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 400                                     struct brw_reg dst,
 401                                     struct brw_reg index)
 402 {
 403    if (intel->gen >= 6) {
 404       brw_push_insn_state(p);
 405       brw_set_mask_control(p, BRW_MASK_DISABLE);
 406       brw_MOV(p,
 407               retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
 408               retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
 409       brw_pop_insn_state(p);
 410    }
 411
 412    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 413                                      index);
 414
 415    uint32_t msg_type;
 416
 417    if (intel->gen >= 6)
 418       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 419    else if (intel->gen == 5 || intel->is_g4x)
 420       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 421    else
 422       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 423
 424    /* Each of the 8 channel enables is considered for whether each
 425     * dword is written.
 426     */
 427    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 428    brw_set_dest(p, send, dst);
 429    brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
 430    brw_set_dp_read_message(p, send,
 431                            255, /* binding table index: stateless access */
 432                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 433                            msg_type,
 434                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 435                            2, /* mlen */
 436                            1 /* rlen */);
 437 }
 438
 439 void
 440 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 441                                      struct brw_reg dst,
 442                                      struct brw_reg src,
 443                                      struct brw_reg index)
 444 {
 445    /* If the instruction is predicated, we'll predicate the send, not
 446     * the header setup.
 447     */
 448    brw_set_predicate_control(p, false);
 449
 450    if (intel->gen >= 6) {
 451       brw_push_insn_state(p);
 452       brw_set_mask_control(p, BRW_MASK_DISABLE);
 453       brw_MOV(p,
 454               retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_D),
 455               retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D));
 456       brw_pop_insn_state(p);
 457    }
 458
 459    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 460                                      index);
 461
 462    brw_MOV(p,
 463            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 464            retype(src, BRW_REGISTER_TYPE_D));
 465
 466    uint32_t msg_type;
 467
 468    if (intel->gen >= 6)
 469       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 470    else
 471       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 472
 473    brw_set_predicate_control(p, inst->predicate);
 474
 475    /* Each of the 8 channel enables is considered for whether each
 476     * dword is written.
 477     */
 478    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 479    brw_set_dest(p, send, dst);
 480    brw_set_src0(p, send, brw_message_reg(inst->base_mrf));
 481    brw_set_dp_write_message(p, send,
 482                             255, /* binding table index: stateless access */
 483                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 484                             msg_type,
 485                             3, /* mlen */
 486                             true, /* header present */
 487                             false, /* pixel scoreboard */
 488                             0, /* rlen */
 489                             false, /* eot */
 490                             false /* commit */);
 491 }
 492
 493 void
 494 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 495                                           struct brw_reg dst,
 496                                           struct brw_reg index)
 497 {
 498    struct brw_reg header = brw_vec8_grf(0, 0);
 499
 500    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 501
 502    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 503            index);
 504
 505    uint32_t msg_type;
 506
 507    if (intel->gen >= 6)
 508       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 509    else if (intel->gen == 5 || intel->is_g4x)
 510       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 511    else
 512       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 513
 514    /* Each of the 8 channel enables is considered for whether each
 515     * dword is written.
 516     */
 517    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 518    brw_set_dest(p, send, dst);
 519    brw_set_src0(p, send, header);
 520    brw_set_dp_read_message(p, send,
 521                            SURF_INDEX_VERT_CONST_BUFFER,
 522                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 523                            msg_type,
 524                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 525                            2, /* mlen */
 526                            1 /* rlen */);
 527 }
 528
 529 void
 530 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 531                                       struct brw_reg dst,
 532                                       struct brw_reg *src)
 533 {
 534    vec4_instruction *inst = (vec4_instruction *)instruction;
 535
 536    switch (inst->opcode) {
 537    case SHADER_OPCODE_RCP:
 538    case SHADER_OPCODE_RSQ:
 539    case SHADER_OPCODE_SQRT:
 540    case SHADER_OPCODE_EXP2:
 541    case SHADER_OPCODE_LOG2:
 542    case SHADER_OPCODE_SIN:
 543    case SHADER_OPCODE_COS:
 544       if (intel->gen >= 6) {
 545          generate_math1_gen6(inst, dst, src[0]);
 546       } else {
 547          generate_math1_gen4(inst, dst, src[0]);
 548       }
 549       break;
 550
 551    case SHADER_OPCODE_POW:
 552       if (intel->gen >= 6) {
 553          generate_math2_gen6(inst, dst, src[0], src[1]);
 554       } else {
 555          generate_math2_gen4(inst, dst, src[0], src[1]);
 556       }
 557       break;
 558
 559    case VS_OPCODE_URB_WRITE:
 560       generate_urb_write(inst);
 561       break;
 562
 563    case VS_OPCODE_SCRATCH_READ:
 564       generate_scratch_read(inst, dst, src[0]);
 565       break;
 566
 567    case VS_OPCODE_SCRATCH_WRITE:
 568       generate_scratch_write(inst, dst, src[0], src[1]);
 569       break;
 570
 571    case VS_OPCODE_PULL_CONSTANT_LOAD:
 572       generate_pull_constant_load(inst, dst, src[0]);
 573       break;
 574
 575    default:
 576       if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
 577          fail("unsupported opcode in `%s' in VS\n",
 578               brw_opcodes[inst->opcode].name);
 579       } else {
 580          fail("Unsupported opcode %d in VS", inst->opcode);
 581       }
 582    }
 583 }
 584
 585 bool
 586 vec4_visitor::run()
 587 {
 588    /* Generate VS IR for main().  (the visitor only descends into
 589     * functions called "main").
 590     */
 591    visit_instructions(shader->ir);
 592
 593    emit_urb_writes();
 594
 595    /* Before any optimization, push array accesses out to scratch
 596     * space where we need them to be.  This pass may allocate new
 597     * virtual GRFs, so we want to do it early.  It also makes sure
 598     * that we have reladdr computations available for CSE, since we'll
 599     * often do repeated subexpressions for those.
 600     */
 601    move_grf_array_access_to_scratch();
 602    move_uniform_array_access_to_pull_constants();
 603
 604    bool progress;
 605    do {
 606       progress = false;
 607       progress = dead_code_eliminate() || progress;
 608    } while (progress);
 609
 610    if (failed)
 611       return false;
 612
 613    setup_payload();
 614    reg_allocate();
 615
 616    if (failed)
 617       return false;
 618
 619    brw_set_access_mode(p, BRW_ALIGN_16);
 620
 621    generate_code();
 622
 623    return !failed;
 624 }
 625
 626 void
 627 vec4_visitor::generate_code()
 628 {
 629    int last_native_inst = p->nr_insn;
 630    const char *last_annotation_string = NULL;
 631    ir_instruction *last_annotation_ir = NULL;
 632
 633    int loop_stack_array_size = 16;
 634    int loop_stack_depth = 0;
 635    brw_instruction **loop_stack =
 636       rzalloc_array(this->mem_ctx, brw_instruction *, loop_stack_array_size);
 637    int *if_depth_in_loop =
 638       rzalloc_array(this->mem_ctx, int, loop_stack_array_size);
 639
 640
 641    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 642       printf("Native code for vertex shader %d:\n", prog->Name);
 643    }
 644
 645    foreach_list(node, &this->instructions) {
 646       vec4_instruction *inst = (vec4_instruction *)node;
 647       struct brw_reg src[3], dst;
 648
 649       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 650          if (last_annotation_ir != inst->ir) {
 651             last_annotation_ir = inst->ir;
 652             if (last_annotation_ir) {
 653                printf("   ");
 654                last_annotation_ir->print();
 655                printf("\n");
 656             }
 657          }
 658          if (last_annotation_string != inst->annotation) {
 659             last_annotation_string = inst->annotation;
 660             if (last_annotation_string)
 661                printf("   %s\n", last_annotation_string);
 662          }
 663       }
 664
 665       for (unsigned int i = 0; i < 3; i++) {
 666          src[i] = inst->get_src(i);
 667       }
 668       dst = inst->get_dst();
 669
 670       brw_set_conditionalmod(p, inst->conditional_mod);
 671       brw_set_predicate_control(p, inst->predicate);
 672       brw_set_predicate_inverse(p, inst->predicate_inverse);
 673       brw_set_saturate(p, inst->saturate);
 674
 675       switch (inst->opcode) {
 676       case BRW_OPCODE_MOV:
 677          brw_MOV(p, dst, src[0]);
 678          break;
 679       case BRW_OPCODE_ADD:
 680          brw_ADD(p, dst, src[0], src[1]);
 681          break;
 682       case BRW_OPCODE_MUL:
 683          brw_MUL(p, dst, src[0], src[1]);
 684          break;
 685       case BRW_OPCODE_MACH:
 686          brw_set_acc_write_control(p, 1);
 687          brw_MACH(p, dst, src[0], src[1]);
 688          brw_set_acc_write_control(p, 0);
 689          break;
 690
 691       case BRW_OPCODE_FRC:
 692          brw_FRC(p, dst, src[0]);
 693          break;
 694       case BRW_OPCODE_RNDD:
 695          brw_RNDD(p, dst, src[0]);
 696          break;
 697       case BRW_OPCODE_RNDE:
 698          brw_RNDE(p, dst, src[0]);
 699          break;
 700       case BRW_OPCODE_RNDZ:
 701          brw_RNDZ(p, dst, src[0]);
 702          break;
 703
 704       case BRW_OPCODE_AND:
 705          brw_AND(p, dst, src[0], src[1]);
 706          break;
 707       case BRW_OPCODE_OR:
 708          brw_OR(p, dst, src[0], src[1]);
 709          break;
 710       case BRW_OPCODE_XOR:
 711          brw_XOR(p, dst, src[0], src[1]);
 712          break;
 713       case BRW_OPCODE_NOT:
 714          brw_NOT(p, dst, src[0]);
 715          break;
 716       case BRW_OPCODE_ASR:
 717          brw_ASR(p, dst, src[0], src[1]);
 718          break;
 719       case BRW_OPCODE_SHR:
 720          brw_SHR(p, dst, src[0], src[1]);
 721          break;
 722       case BRW_OPCODE_SHL:
 723          brw_SHL(p, dst, src[0], src[1]);
 724          break;
 725
 726       case BRW_OPCODE_CMP:
 727          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 728          break;
 729       case BRW_OPCODE_SEL:
 730          brw_SEL(p, dst, src[0], src[1]);
 731          break;
 732
 733       case BRW_OPCODE_DP4:
 734          brw_DP4(p, dst, src[0], src[1]);
 735          break;
 736
 737       case BRW_OPCODE_DP3:
 738          brw_DP3(p, dst, src[0], src[1]);
 739          break;
 740
 741       case BRW_OPCODE_DP2:
 742          brw_DP2(p, dst, src[0], src[1]);
 743          break;
 744
 745       case BRW_OPCODE_IF:
 746          if (inst->src[0].file != BAD_FILE) {
 747             /* The instruction has an embedded compare (only allowed on gen6) */
 748             assert(intel->gen == 6);
 749             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 750          } else {
 751             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 752             brw_inst->header.predicate_control = inst->predicate;
 753          }
 754          if_depth_in_loop[loop_stack_depth]++;
 755          break;
 756
 757       case BRW_OPCODE_ELSE:
 758          brw_ELSE(p);
 759          break;
 760       case BRW_OPCODE_ENDIF:
 761          brw_ENDIF(p);
 762          if_depth_in_loop[loop_stack_depth]--;
 763          break;
 764
 765       case BRW_OPCODE_DO:
 766          loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
 767          if (loop_stack_array_size <= loop_stack_depth) {
 768             loop_stack_array_size *= 2;
 769             loop_stack = reralloc(this->mem_ctx, loop_stack, brw_instruction *,
 770                                   loop_stack_array_size);
 771             if_depth_in_loop = reralloc(this->mem_ctx, if_depth_in_loop, int,
 772                                         loop_stack_array_size);
 773          }
 774          if_depth_in_loop[loop_stack_depth] = 0;
 775          break;
 776
 777       case BRW_OPCODE_BREAK:
 778          brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
 779          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 780          break;
 781       case BRW_OPCODE_CONTINUE:
 782          /* FINISHME: We need to write the loop instruction support still. */
 783          if (intel->gen >= 6)
 784             gen6_CONT(p, loop_stack[loop_stack_depth - 1]);
 785          else
 786             brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
 787          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 788          break;
 789
 790       case BRW_OPCODE_WHILE: {
 791          struct brw_instruction *inst0, *inst1;
 792          GLuint br = 1;
 793
 794          if (intel->gen >= 5)
 795             br = 2;
 796
 797          assert(loop_stack_depth > 0);
 798          loop_stack_depth--;
 799          inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
 800          if (intel->gen < 6) {
 801             /* patch all the BREAK/CONT instructions from last BGNLOOP */
 802             while (inst0 > loop_stack[loop_stack_depth]) {
 803                inst0--;
 804                if (inst0->header.opcode == BRW_OPCODE_BREAK &&
 805                    inst0->bits3.if_else.jump_count == 0) {
 806                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
 807             }
 808                else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
 809                         inst0->bits3.if_else.jump_count == 0) {
 810                   inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
 811                }
 812             }
 813          }
 814       }
 815          break;
 816
 817       default:
 818          generate_vs_instruction(inst, dst, src);
 819          break;
 820       }
 821
 822       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 823          for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
 824             if (0) {
 825                printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 826                       ((uint32_t *)&p->store[i])[3],
 827                       ((uint32_t *)&p->store[i])[2],
 828                       ((uint32_t *)&p->store[i])[1],
 829                       ((uint32_t *)&p->store[i])[0]);
 830             }
 831             brw_disasm(stdout, &p->store[i], intel->gen);
 832          }
 833       }
 834
 835       last_native_inst = p->nr_insn;
 836    }
 837
 838    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 839       printf("\n");
 840    }
 841
 842    ralloc_free(loop_stack);
 843    ralloc_free(if_depth_in_loop);
 844
 845    brw_set_uip_jip(p);
 846
 847    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
 848     * emit issues, it doesn't get the jump distances into the output,
 849     * which is often something we want to debug.  So this is here in
 850     * case you're doing that.
 851     */
 852    if (0) {
 853       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 854          for (unsigned int i = 0; i < p->nr_insn; i++) {
 855             printf("0x%08x 0x%08x 0x%08x 0x%08x ",
 856                    ((uint32_t *)&p->store[i])[3],
 857                    ((uint32_t *)&p->store[i])[2],
 858                    ((uint32_t *)&p->store[i])[1],
 859                    ((uint32_t *)&p->store[i])[0]);
 860             brw_disasm(stdout, &p->store[i], intel->gen);
 861          }
 862       }
 863    }
 864 }
 865
 866 extern "C" {
 867
 868 bool
 869 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
 870 {
 871    if (!prog)
 872       return false;
 873
 874    struct brw_shader *shader =
 875      (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
 876    if (!shader)
 877       return false;
 878
 879    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 880       printf("GLSL IR for native vertex shader %d:\n", prog->Name);
 881       _mesa_print_ir(shader->ir, NULL);
 882       printf("\n\n");
 883    }
 884
 885    vec4_visitor v(c, prog, shader);
 886    if (!v.run()) {
 887       prog->LinkStatus = GL_FALSE;
 888       ralloc_strcat(&prog->InfoLog, v.fail_msg);
 889       return false;
 890    }
 891
 892    return true;
 893 }
 894
 895 } /* extern "C" */
 896
 897 } /* namespace brw */