src/mesa/drivers/dri/i965/brw_vec4_emit.cpp

   1 /* Copyright © 2011 Intel Corporation
   2  *
   3  * Permission is hereby granted, free of charge, to any person obtaining a
   4  * copy of this software and associated documentation files (the "Software"),
   5  * to deal in the Software without restriction, including without limitation
   6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   7  * and/or sell copies of the Software, and to permit persons to whom the
   8  * Software is furnished to do so, subject to the following conditions:
   9  *
  10  * The above copyright notice and this permission notice (including the next
  11  * paragraph) shall be included in all copies or substantial portions of the
  12  * Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  20  * IN THE SOFTWARE.
  21  */
  22
  23 #include "brw_vec4.h"
  24 #include "glsl/ir_print_visitor.h"
  25
  26 extern "C" {
  27 #include "brw_eu.h"
  28 #include "main/macros.h"
  29 #include "program/prog_print.h"
  30 #include "program/prog_parameter.h"
  31 };
  32
  33 using namespace brw;
  34
  35 namespace brw {
  36
  37 int
  38 vec4_visitor::setup_attributes(int payload_reg)
  39 {
  40    int nr_attributes;
  41    int attribute_map[VERT_ATTRIB_MAX + 1];
  42
  43    nr_attributes = 0;
  44    for (int i = 0; i < VERT_ATTRIB_MAX; i++) {
  45       if (prog_data->inputs_read & BITFIELD64_BIT(i)) {
  46          attribute_map[i] = payload_reg + nr_attributes;
  47          nr_attributes++;
  48       }
  49    }
  50
  51    /* VertexID is stored by the VF as the last vertex element, but we
  52     * don't represent it with a flag in inputs_read, so we call it
  53     * VERT_ATTRIB_MAX.
  54     */
  55    if (prog_data->uses_vertexid) {
  56       attribute_map[VERT_ATTRIB_MAX] = payload_reg + nr_attributes;
  57       nr_attributes++;
  58    }
  59
  60    foreach_list(node, &this->instructions) {
  61       vec4_instruction *inst = (vec4_instruction *)node;
  62
  63       /* We have to support ATTR as a destination for GL_FIXED fixup. */
  64       if (inst->dst.file == ATTR) {
  65          int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset];
  66
  67          struct brw_reg reg = brw_vec8_grf(grf, 0);
  68          reg.type = inst->dst.type;
  69          reg.dw1.bits.writemask = inst->dst.writemask;
  70
  71          inst->dst.file = HW_REG;
  72          inst->dst.fixed_hw_reg = reg;
  73       }
  74
  75       for (int i = 0; i < 3; i++) {
  76          if (inst->src[i].file != ATTR)
  77             continue;
  78
  79          int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset];
  80
  81          struct brw_reg reg = brw_vec8_grf(grf, 0);
  82          reg.dw1.bits.swizzle = inst->src[i].swizzle;
  83          reg.type = inst->src[i].type;
  84          if (inst->src[i].abs)
  85             reg = brw_abs(reg);
  86          if (inst->src[i].negate)
  87             reg = negate(reg);
  88
  89          inst->src[i].file = HW_REG;
  90          inst->src[i].fixed_hw_reg = reg;
  91       }
  92    }
  93
  94    /* The BSpec says we always have to read at least one thing from
  95     * the VF, and it appears that the hardware wedges otherwise.
  96     */
  97    if (nr_attributes == 0)
  98       nr_attributes = 1;
  99
 100    prog_data->urb_read_length = (nr_attributes + 1) / 2;
 101
 102    unsigned vue_entries = MAX2(nr_attributes, c->prog_data.vue_map.num_slots);
 103
 104    if (intel->gen == 6)
 105       c->prog_data.urb_entry_size = ALIGN(vue_entries, 8) / 8;
 106    else
 107       c->prog_data.urb_entry_size = ALIGN(vue_entries, 4) / 4;
 108
 109    return payload_reg + nr_attributes;
 110 }
 111
 112 int
 113 vec4_visitor::setup_uniforms(int reg)
 114 {
 115    /* The pre-gen6 VS requires that some push constants get loaded no
 116     * matter what, or the GPU would hang.
 117     */
 118    if (intel->gen < 6 && this->uniforms == 0) {
 119       this->uniform_vector_size[this->uniforms] = 1;
 120
 121       for (unsigned int i = 0; i < 4; i++) {
 122          unsigned int slot = this->uniforms * 4 + i;
 123          static float zero = 0.0;
 124          c->prog_data.param[slot] = &zero;
 125       }
 126
 127       this->uniforms++;
 128       reg++;
 129    } else {
 130       reg += ALIGN(uniforms, 2) / 2;
 131    }
 132
 133    c->prog_data.nr_params = this->uniforms * 4;
 134
 135    c->prog_data.curb_read_length = reg - 1;
 136
 137    return reg;
 138 }
 139
 140 void
 141 vec4_visitor::setup_payload(void)
 142 {
 143    int reg = 0;
 144
 145    /* The payload always contains important data in g0, which contains
 146     * the URB handles that are passed on to the URB write at the end
 147     * of the thread.  So, we always start push constants at g1.
 148     */
 149    reg++;
 150
 151    reg = setup_uniforms(reg);
 152
 153    reg = setup_attributes(reg);
 154
 155    this->first_non_payload_grf = reg;
 156 }
 157
 158 struct brw_reg
 159 vec4_instruction::get_dst(void)
 160 {
 161    struct brw_reg brw_reg;
 162
 163    switch (dst.file) {
 164    case GRF:
 165       brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
 166       brw_reg = retype(brw_reg, dst.type);
 167       brw_reg.dw1.bits.writemask = dst.writemask;
 168       break;
 169
 170    case MRF:
 171       brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
 172       brw_reg = retype(brw_reg, dst.type);
 173       brw_reg.dw1.bits.writemask = dst.writemask;
 174       break;
 175
 176    case HW_REG:
 177       brw_reg = dst.fixed_hw_reg;
 178       break;
 179
 180    case BAD_FILE:
 181       brw_reg = brw_null_reg();
 182       break;
 183
 184    default:
 185       assert(!"not reached");
 186       brw_reg = brw_null_reg();
 187       break;
 188    }
 189    return brw_reg;
 190 }
 191
 192 struct brw_reg
 193 vec4_instruction::get_src(int i)
 194 {
 195    struct brw_reg brw_reg;
 196
 197    switch (src[i].file) {
 198    case GRF:
 199       brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
 200       brw_reg = retype(brw_reg, src[i].type);
 201       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 202       if (src[i].abs)
 203          brw_reg = brw_abs(brw_reg);
 204       if (src[i].negate)
 205          brw_reg = negate(brw_reg);
 206       break;
 207
 208    case IMM:
 209       switch (src[i].type) {
 210       case BRW_REGISTER_TYPE_F:
 211          brw_reg = brw_imm_f(src[i].imm.f);
 212          break;
 213       case BRW_REGISTER_TYPE_D:
 214          brw_reg = brw_imm_d(src[i].imm.i);
 215          break;
 216       case BRW_REGISTER_TYPE_UD:
 217          brw_reg = brw_imm_ud(src[i].imm.u);
 218          break;
 219       default:
 220          assert(!"not reached");
 221          brw_reg = brw_null_reg();
 222          break;
 223       }
 224       break;
 225
 226    case UNIFORM:
 227       brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
 228                                     ((src[i].reg + src[i].reg_offset) % 2) * 4),
 229                        0, 4, 1);
 230       brw_reg = retype(brw_reg, src[i].type);
 231       brw_reg.dw1.bits.swizzle = src[i].swizzle;
 232       if (src[i].abs)
 233          brw_reg = brw_abs(brw_reg);
 234       if (src[i].negate)
 235          brw_reg = negate(brw_reg);
 236
 237       /* This should have been moved to pull constants. */
 238       assert(!src[i].reladdr);
 239       break;
 240
 241    case HW_REG:
 242       brw_reg = src[i].fixed_hw_reg;
 243       break;
 244
 245    case BAD_FILE:
 246       /* Probably unused. */
 247       brw_reg = brw_null_reg();
 248       break;
 249    case ATTR:
 250    default:
 251       assert(!"not reached");
 252       brw_reg = brw_null_reg();
 253       break;
 254    }
 255
 256    return brw_reg;
 257 }
 258
 259 void
 260 vec4_visitor::generate_math1_gen4(vec4_instruction *inst,
 261                                   struct brw_reg dst,
 262                                   struct brw_reg src)
 263 {
 264    brw_math(p,
 265             dst,
 266             brw_math_function(inst->opcode),
 267             inst->base_mrf,
 268             src,
 269             BRW_MATH_DATA_VECTOR,
 270             BRW_MATH_PRECISION_FULL);
 271 }
 272
 273 static void
 274 check_gen6_math_src_arg(struct brw_reg src)
 275 {
 276    /* Source swizzles are ignored. */
 277    assert(!src.abs);
 278    assert(!src.negate);
 279    assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
 280 }
 281
 282 void
 283 vec4_visitor::generate_math1_gen6(vec4_instruction *inst,
 284                                   struct brw_reg dst,
 285                                   struct brw_reg src)
 286 {
 287    /* Can't do writemask because math can't be align16. */
 288    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 289    check_gen6_math_src_arg(src);
 290
 291    brw_set_access_mode(p, BRW_ALIGN_1);
 292    brw_math(p,
 293             dst,
 294             brw_math_function(inst->opcode),
 295             inst->base_mrf,
 296             src,
 297             BRW_MATH_DATA_SCALAR,
 298             BRW_MATH_PRECISION_FULL);
 299    brw_set_access_mode(p, BRW_ALIGN_16);
 300 }
 301
 302 void
 303 vec4_visitor::generate_math2_gen7(vec4_instruction *inst,
 304                                   struct brw_reg dst,
 305                                   struct brw_reg src0,
 306                                   struct brw_reg src1)
 307 {
 308    brw_math2(p,
 309              dst,
 310              brw_math_function(inst->opcode),
 311              src0, src1);
 312 }
 313
 314 void
 315 vec4_visitor::generate_math2_gen6(vec4_instruction *inst,
 316                                   struct brw_reg dst,
 317                                   struct brw_reg src0,
 318                                   struct brw_reg src1)
 319 {
 320    /* Can't do writemask because math can't be align16. */
 321    assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
 322    /* Source swizzles are ignored. */
 323    check_gen6_math_src_arg(src0);
 324    check_gen6_math_src_arg(src1);
 325
 326    brw_set_access_mode(p, BRW_ALIGN_1);
 327    brw_math2(p,
 328              dst,
 329              brw_math_function(inst->opcode),
 330              src0, src1);
 331    brw_set_access_mode(p, BRW_ALIGN_16);
 332 }
 333
 334 void
 335 vec4_visitor::generate_math2_gen4(vec4_instruction *inst,
 336                                   struct brw_reg dst,
 337                                   struct brw_reg src0,
 338                                   struct brw_reg src1)
 339 {
 340    /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
 341     * "Message Payload":
 342     *
 343     * "Operand0[7].  For the INT DIV functions, this operand is the
 344     *  denominator."
 345     *  ...
 346     * "Operand1[7].  For the INT DIV functions, this operand is the
 347     *  numerator."
 348     */
 349    bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
 350    struct brw_reg &op0 = is_int_div ? src1 : src0;
 351    struct brw_reg &op1 = is_int_div ? src0 : src1;
 352
 353    brw_push_insn_state(p);
 354    brw_set_saturate(p, false);
 355    brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 356    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
 357    brw_pop_insn_state(p);
 358
 359    brw_math(p,
 360             dst,
 361             brw_math_function(inst->opcode),
 362             inst->base_mrf,
 363             op0,
 364             BRW_MATH_DATA_VECTOR,
 365             BRW_MATH_PRECISION_FULL);
 366 }
 367
 368 void
 369 vec4_visitor::generate_tex(vec4_instruction *inst,
 370                            struct brw_reg dst,
 371                            struct brw_reg src)
 372 {
 373    int msg_type = -1;
 374
 375    if (intel->gen >= 5) {
 376       switch (inst->opcode) {
 377       case SHADER_OPCODE_TEX:
 378       case SHADER_OPCODE_TXL:
 379          if (inst->shadow_compare) {
 380             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
 381          } else {
 382             msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
 383          }
 384          break;
 385       case SHADER_OPCODE_TXD:
 386          /* There is no sample_d_c message; comparisons are done manually. */
 387          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
 388          break;
 389       case SHADER_OPCODE_TXF:
 390          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
 391          break;
 392       case SHADER_OPCODE_TXS:
 393          msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
 394          break;
 395       default:
 396          assert(!"should not get here: invalid VS texture opcode");
 397          break;
 398       }
 399    } else {
 400       switch (inst->opcode) {
 401       case SHADER_OPCODE_TEX:
 402       case SHADER_OPCODE_TXL:
 403          if (inst->shadow_compare) {
 404             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
 405             assert(inst->mlen == 3);
 406          } else {
 407             msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
 408             assert(inst->mlen == 2);
 409          }
 410          break;
 411       case SHADER_OPCODE_TXD:
 412          /* There is no sample_d_c message; comparisons are done manually. */
 413          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
 414          assert(inst->mlen == 4);
 415          break;
 416       case SHADER_OPCODE_TXF:
 417          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
 418          assert(inst->mlen == 2);
 419          break;
 420       case SHADER_OPCODE_TXS:
 421          msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
 422          assert(inst->mlen == 2);
 423          break;
 424       default:
 425          assert(!"should not get here: invalid VS texture opcode");
 426          break;
 427       }
 428    }
 429
 430    assert(msg_type != -1);
 431
 432    /* Load the message header if present.  If there's a texture offset, we need
 433     * to set it up explicitly and load the offset bitfield.  Otherwise, we can
 434     * use an implied move from g0 to the first message register.
 435     */
 436    if (inst->texture_offset) {
 437       /* Explicitly set up the message header by copying g0 to the MRF. */
 438       brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
 439                  retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 440
 441       /* Then set the offset bits in DWord 2. */
 442       brw_set_access_mode(p, BRW_ALIGN_1);
 443       brw_MOV(p,
 444               retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
 445                      BRW_REGISTER_TYPE_UD),
 446               brw_imm_uw(inst->texture_offset));
 447       brw_set_access_mode(p, BRW_ALIGN_16);
 448    } else if (inst->header_present) {
 449       /* Set up an implied move from g0 to the MRF. */
 450       src = brw_vec8_grf(0, 0);
 451    }
 452
 453    uint32_t return_format;
 454
 455    switch (dst.type) {
 456    case BRW_REGISTER_TYPE_D:
 457       return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
 458       break;
 459    case BRW_REGISTER_TYPE_UD:
 460       return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
 461       break;
 462    default:
 463       return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
 464       break;
 465    }
 466
 467    brw_SAMPLE(p,
 468               dst,
 469               inst->base_mrf,
 470               src,
 471               SURF_INDEX_VS_TEXTURE(inst->sampler),
 472               inst->sampler,
 473               WRITEMASK_XYZW,
 474               msg_type,
 475               1, /* response length */
 476               inst->mlen,
 477               inst->header_present,
 478               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 479               return_format);
 480 }
 481
 482 void
 483 vec4_visitor::generate_urb_write(vec4_instruction *inst)
 484 {
 485    brw_urb_WRITE(p,
 486                  brw_null_reg(), /* dest */
 487                  inst->base_mrf, /* starting mrf reg nr */
 488                  brw_vec8_grf(0, 0), /* src */
 489                  false,         /* allocate */
 490                  true,          /* used */
 491                  inst->mlen,
 492                  0,             /* response len */
 493                  inst->eot,     /* eot */
 494                  inst->eot,     /* writes complete */
 495                  inst->offset,  /* urb destination offset */
 496                  BRW_URB_SWIZZLE_INTERLEAVE);
 497 }
 498
 499 void
 500 vec4_visitor::generate_oword_dual_block_offsets(struct brw_reg m1,
 501                                                 struct brw_reg index)
 502 {
 503    int second_vertex_offset;
 504
 505    if (intel->gen >= 6)
 506       second_vertex_offset = 1;
 507    else
 508       second_vertex_offset = 16;
 509
 510    m1 = retype(m1, BRW_REGISTER_TYPE_D);
 511
 512    /* Set up M1 (message payload).  Only the block offsets in M1.0 and
 513     * M1.4 are used, and the rest are ignored.
 514     */
 515    struct brw_reg m1_0 = suboffset(vec1(m1), 0);
 516    struct brw_reg m1_4 = suboffset(vec1(m1), 4);
 517    struct brw_reg index_0 = suboffset(vec1(index), 0);
 518    struct brw_reg index_4 = suboffset(vec1(index), 4);
 519
 520    brw_push_insn_state(p);
 521    brw_set_mask_control(p, BRW_MASK_DISABLE);
 522    brw_set_access_mode(p, BRW_ALIGN_1);
 523
 524    brw_MOV(p, m1_0, index_0);
 525
 526    if (index.file == BRW_IMMEDIATE_VALUE) {
 527       index_4.dw1.ud += second_vertex_offset;
 528       brw_MOV(p, m1_4, index_4);
 529    } else {
 530       brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
 531    }
 532
 533    brw_pop_insn_state(p);
 534 }
 535
 536 void
 537 vec4_visitor::generate_scratch_read(vec4_instruction *inst,
 538                                     struct brw_reg dst,
 539                                     struct brw_reg index)
 540 {
 541    struct brw_reg header = brw_vec8_grf(0, 0);
 542
 543    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 544
 545    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 546                                      index);
 547
 548    uint32_t msg_type;
 549
 550    if (intel->gen >= 6)
 551       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 552    else if (intel->gen == 5 || intel->is_g4x)
 553       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 554    else
 555       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 556
 557    /* Each of the 8 channel enables is considered for whether each
 558     * dword is written.
 559     */
 560    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 561    brw_set_dest(p, send, dst);
 562    brw_set_src0(p, send, header);
 563    if (intel->gen < 6)
 564       send->header.destreg__conditionalmod = inst->base_mrf;
 565    brw_set_dp_read_message(p, send,
 566                            255, /* binding table index: stateless access */
 567                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 568                            msg_type,
 569                            BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
 570                            2, /* mlen */
 571                            1 /* rlen */);
 572 }
 573
 574 void
 575 vec4_visitor::generate_scratch_write(vec4_instruction *inst,
 576                                      struct brw_reg dst,
 577                                      struct brw_reg src,
 578                                      struct brw_reg index)
 579 {
 580    struct brw_reg header = brw_vec8_grf(0, 0);
 581    bool write_commit;
 582
 583    /* If the instruction is predicated, we'll predicate the send, not
 584     * the header setup.
 585     */
 586    brw_set_predicate_control(p, false);
 587
 588    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 589
 590    generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
 591                                      index);
 592
 593    brw_MOV(p,
 594            retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
 595            retype(src, BRW_REGISTER_TYPE_D));
 596
 597    uint32_t msg_type;
 598
 599    if (intel->gen >= 7)
 600       msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 601    else if (intel->gen == 6)
 602       msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 603    else
 604       msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
 605
 606    brw_set_predicate_control(p, inst->predicate);
 607
 608    /* Pre-gen6, we have to specify write commits to ensure ordering
 609     * between reads and writes within a thread.  Afterwards, that's
 610     * guaranteed and write commits only matter for inter-thread
 611     * synchronization.
 612     */
 613    if (intel->gen >= 6) {
 614       write_commit = false;
 615    } else {
 616       /* The visitor set up our destination register to be g0.  This
 617        * means that when the next read comes along, we will end up
 618        * reading from g0 and causing a block on the write commit.  For
 619        * write-after-read, we are relying on the value of the previous
 620        * read being used (and thus blocking on completion) before our
 621        * write is executed.  This means we have to be careful in
 622        * instruction scheduling to not violate this assumption.
 623        */
 624       write_commit = true;
 625    }
 626
 627    /* Each of the 8 channel enables is considered for whether each
 628     * dword is written.
 629     */
 630    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 631    brw_set_dest(p, send, dst);
 632    brw_set_src0(p, send, header);
 633    if (intel->gen < 6)
 634       send->header.destreg__conditionalmod = inst->base_mrf;
 635    brw_set_dp_write_message(p, send,
 636                             255, /* binding table index: stateless access */
 637                             BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 638                             msg_type,
 639                             3, /* mlen */
 640                             true, /* header present */
 641                             false, /* not a render target write */
 642                             write_commit, /* rlen */
 643                             false, /* eot */
 644                             write_commit);
 645 }
 646
 647 void
 648 vec4_visitor::generate_pull_constant_load(vec4_instruction *inst,
 649                                           struct brw_reg dst,
 650                                           struct brw_reg index,
 651                                           struct brw_reg offset)
 652 {
 653    assert(index.file == BRW_IMMEDIATE_VALUE &&
 654           index.type == BRW_REGISTER_TYPE_UD);
 655    uint32_t surf_index = index.dw1.ud;
 656
 657    if (intel->gen == 7) {
 658       gen6_resolve_implied_move(p, &offset, inst->base_mrf);
 659       brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
 660       brw_set_dest(p, insn, dst);
 661       brw_set_src0(p, insn, offset);
 662       brw_set_sampler_message(p, insn,
 663                               surf_index,
 664                               0, /* LD message ignores sampler unit */
 665                               GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
 666                               1, /* rlen */
 667                               1, /* mlen */
 668                               false, /* no header */
 669                               BRW_SAMPLER_SIMD_MODE_SIMD4X2,
 670                               0);
 671       return;
 672    }
 673
 674    struct brw_reg header = brw_vec8_grf(0, 0);
 675
 676    gen6_resolve_implied_move(p, &header, inst->base_mrf);
 677
 678    brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
 679            offset);
 680
 681    uint32_t msg_type;
 682
 683    if (intel->gen >= 6)
 684       msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 685    else if (intel->gen == 5 || intel->is_g4x)
 686       msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 687    else
 688       msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
 689
 690    /* Each of the 8 channel enables is considered for whether each
 691     * dword is written.
 692     */
 693    struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
 694    brw_set_dest(p, send, dst);
 695    brw_set_src0(p, send, header);
 696    if (intel->gen < 6)
 697       send->header.destreg__conditionalmod = inst->base_mrf;
 698    brw_set_dp_read_message(p, send,
 699                            surf_index,
 700                            BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
 701                            msg_type,
 702                            BRW_DATAPORT_READ_TARGET_DATA_CACHE,
 703                            2, /* mlen */
 704                            1 /* rlen */);
 705 }
 706
 707 void
 708 vec4_visitor::generate_vs_instruction(vec4_instruction *instruction,
 709                                       struct brw_reg dst,
 710                                       struct brw_reg *src)
 711 {
 712    vec4_instruction *inst = (vec4_instruction *)instruction;
 713
 714    switch (inst->opcode) {
 715    case SHADER_OPCODE_RCP:
 716    case SHADER_OPCODE_RSQ:
 717    case SHADER_OPCODE_SQRT:
 718    case SHADER_OPCODE_EXP2:
 719    case SHADER_OPCODE_LOG2:
 720    case SHADER_OPCODE_SIN:
 721    case SHADER_OPCODE_COS:
 722       if (intel->gen == 6) {
 723          generate_math1_gen6(inst, dst, src[0]);
 724       } else {
 725          /* Also works for Gen7. */
 726          generate_math1_gen4(inst, dst, src[0]);
 727       }
 728       break;
 729
 730    case SHADER_OPCODE_POW:
 731    case SHADER_OPCODE_INT_QUOTIENT:
 732    case SHADER_OPCODE_INT_REMAINDER:
 733       if (intel->gen >= 7) {
 734          generate_math2_gen7(inst, dst, src[0], src[1]);
 735       } else if (intel->gen == 6) {
 736          generate_math2_gen6(inst, dst, src[0], src[1]);
 737       } else {
 738          generate_math2_gen4(inst, dst, src[0], src[1]);
 739       }
 740       break;
 741
 742    case SHADER_OPCODE_TEX:
 743    case SHADER_OPCODE_TXD:
 744    case SHADER_OPCODE_TXF:
 745    case SHADER_OPCODE_TXL:
 746    case SHADER_OPCODE_TXS:
 747       generate_tex(inst, dst, src[0]);
 748       break;
 749
 750    case VS_OPCODE_URB_WRITE:
 751       generate_urb_write(inst);
 752       break;
 753
 754    case VS_OPCODE_SCRATCH_READ:
 755       generate_scratch_read(inst, dst, src[0]);
 756       break;
 757
 758    case VS_OPCODE_SCRATCH_WRITE:
 759       generate_scratch_write(inst, dst, src[0], src[1]);
 760       break;
 761
 762    case VS_OPCODE_PULL_CONSTANT_LOAD:
 763       generate_pull_constant_load(inst, dst, src[0], src[1]);
 764       break;
 765
 766    default:
 767       if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
 768          fail("unsupported opcode in `%s' in VS\n",
 769               opcode_descs[inst->opcode].name);
 770       } else {
 771          fail("Unsupported opcode %d in VS", inst->opcode);
 772       }
 773    }
 774 }
 775
 776 bool
 777 vec4_visitor::run()
 778 {
 779    emit_attribute_fixups();
 780
 781    /* Generate VS IR for main().  (the visitor only descends into
 782     * functions called "main").
 783     */
 784    if (shader) {
 785       visit_instructions(shader->ir);
 786    } else {
 787       emit_vertex_program_code();
 788    }
 789
 790    if (c->key.userclip_active && !c->key.uses_clip_distance)
 791       setup_uniform_clipplane_values();
 792
 793    emit_urb_writes();
 794
 795    /* Before any optimization, push array accesses out to scratch
 796     * space where we need them to be.  This pass may allocate new
 797     * virtual GRFs, so we want to do it early.  It also makes sure
 798     * that we have reladdr computations available for CSE, since we'll
 799     * often do repeated subexpressions for those.
 800     */
 801    if (shader) {
 802       move_grf_array_access_to_scratch();
 803       move_uniform_array_access_to_pull_constants();
 804    } else {
 805       /* The ARB_vertex_program frontend emits pull constant loads directly
 806        * rather than using reladdr, so we don't need to walk through all the
 807        * instructions looking for things to move.  There isn't anything.
 808        *
 809        * We do still need to split things to vec4 size.
 810        */
 811       split_uniform_registers();
 812    }
 813    pack_uniform_registers();
 814    move_push_constants_to_pull_constants();
 815    split_virtual_grfs();
 816
 817    bool progress;
 818    do {
 819       progress = false;
 820       progress = dead_code_eliminate() || progress;
 821       progress = opt_copy_propagation() || progress;
 822       progress = opt_algebraic() || progress;
 823       progress = opt_compute_to_mrf() || progress;
 824    } while (progress);
 825
 826
 827    if (failed)
 828       return false;
 829
 830    setup_payload();
 831
 832    if (false) {
 833       /* Debug of register spilling: Go spill everything. */
 834       const int grf_count = virtual_grf_count;
 835       float spill_costs[virtual_grf_count];
 836       bool no_spill[virtual_grf_count];
 837       evaluate_spill_costs(spill_costs, no_spill);
 838       for (int i = 0; i < grf_count; i++) {
 839          if (no_spill[i])
 840             continue;
 841          spill_reg(i);
 842       }
 843    }
 844
 845    while (!reg_allocate()) {
 846       if (failed)
 847          break;
 848    }
 849
 850    if (failed)
 851       return false;
 852
 853    brw_set_access_mode(p, BRW_ALIGN_16);
 854
 855    generate_code();
 856
 857    return !failed;
 858 }
 859
 860 void
 861 vec4_visitor::generate_code()
 862 {
 863    int last_native_insn_offset = 0;
 864    const char *last_annotation_string = NULL;
 865    const void *last_annotation_ir = NULL;
 866
 867    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 868       if (shader) {
 869          printf("Native code for vertex shader %d:\n", prog->Name);
 870       } else {
 871          printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
 872       }
 873    }
 874
 875    foreach_list(node, &this->instructions) {
 876       vec4_instruction *inst = (vec4_instruction *)node;
 877       struct brw_reg src[3], dst;
 878
 879       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
 880          if (last_annotation_ir != inst->ir) {
 881             last_annotation_ir = inst->ir;
 882             if (last_annotation_ir) {
 883                printf("   ");
 884                if (shader) {
 885                   ((ir_instruction *) last_annotation_ir)->print();
 886                } else {
 887                   const prog_instruction *vpi;
 888                   vpi = (const prog_instruction *) inst->ir;
 889                   printf("%d: ", (int)(vpi - vp->Base.Instructions));
 890                   _mesa_fprint_instruction_opt(stdout, vpi, 0,
 891                                                PROG_PRINT_DEBUG, NULL);
 892                }
 893                printf("\n");
 894             }
 895          }
 896          if (last_annotation_string != inst->annotation) {
 897             last_annotation_string = inst->annotation;
 898             if (last_annotation_string)
 899                printf("   %s\n", last_annotation_string);
 900          }
 901       }
 902
 903       for (unsigned int i = 0; i < 3; i++) {
 904          src[i] = inst->get_src(i);
 905       }
 906       dst = inst->get_dst();
 907
 908       brw_set_conditionalmod(p, inst->conditional_mod);
 909       brw_set_predicate_control(p, inst->predicate);
 910       brw_set_predicate_inverse(p, inst->predicate_inverse);
 911       brw_set_saturate(p, inst->saturate);
 912
 913       switch (inst->opcode) {
 914       case BRW_OPCODE_MOV:
 915          brw_MOV(p, dst, src[0]);
 916          break;
 917       case BRW_OPCODE_ADD:
 918          brw_ADD(p, dst, src[0], src[1]);
 919          break;
 920       case BRW_OPCODE_MUL:
 921          brw_MUL(p, dst, src[0], src[1]);
 922          break;
 923       case BRW_OPCODE_MACH:
 924          brw_set_acc_write_control(p, 1);
 925          brw_MACH(p, dst, src[0], src[1]);
 926          brw_set_acc_write_control(p, 0);
 927          break;
 928
 929       case BRW_OPCODE_FRC:
 930          brw_FRC(p, dst, src[0]);
 931          break;
 932       case BRW_OPCODE_RNDD:
 933          brw_RNDD(p, dst, src[0]);
 934          break;
 935       case BRW_OPCODE_RNDE:
 936          brw_RNDE(p, dst, src[0]);
 937          break;
 938       case BRW_OPCODE_RNDZ:
 939          brw_RNDZ(p, dst, src[0]);
 940          break;
 941
 942       case BRW_OPCODE_AND:
 943          brw_AND(p, dst, src[0], src[1]);
 944          break;
 945       case BRW_OPCODE_OR:
 946          brw_OR(p, dst, src[0], src[1]);
 947          break;
 948       case BRW_OPCODE_XOR:
 949          brw_XOR(p, dst, src[0], src[1]);
 950          break;
 951       case BRW_OPCODE_NOT:
 952          brw_NOT(p, dst, src[0]);
 953          break;
 954       case BRW_OPCODE_ASR:
 955          brw_ASR(p, dst, src[0], src[1]);
 956          break;
 957       case BRW_OPCODE_SHR:
 958          brw_SHR(p, dst, src[0], src[1]);
 959          break;
 960       case BRW_OPCODE_SHL:
 961          brw_SHL(p, dst, src[0], src[1]);
 962          break;
 963
 964       case BRW_OPCODE_CMP:
 965          brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
 966          break;
 967       case BRW_OPCODE_SEL:
 968          brw_SEL(p, dst, src[0], src[1]);
 969          break;
 970
 971       case BRW_OPCODE_DPH:
 972          brw_DPH(p, dst, src[0], src[1]);
 973          break;
 974
 975       case BRW_OPCODE_DP4:
 976          brw_DP4(p, dst, src[0], src[1]);
 977          break;
 978
 979       case BRW_OPCODE_DP3:
 980          brw_DP3(p, dst, src[0], src[1]);
 981          break;
 982
 983       case BRW_OPCODE_DP2:
 984          brw_DP2(p, dst, src[0], src[1]);
 985          break;
 986
 987       case BRW_OPCODE_IF:
 988          if (inst->src[0].file != BAD_FILE) {
 989             /* The instruction has an embedded compare (only allowed on gen6) */
 990             assert(intel->gen == 6);
 991             gen6_IF(p, inst->conditional_mod, src[0], src[1]);
 992          } else {
 993             struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
 994             brw_inst->header.predicate_control = inst->predicate;
 995          }
 996          break;
 997
 998       case BRW_OPCODE_ELSE:
 999          brw_ELSE(p);
1000          break;
1001       case BRW_OPCODE_ENDIF:
1002          brw_ENDIF(p);
1003          break;
1004
1005       case BRW_OPCODE_DO:
1006          brw_DO(p, BRW_EXECUTE_8);
1007          break;
1008
1009       case BRW_OPCODE_BREAK:
1010          brw_BREAK(p);
1011          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1012          break;
1013       case BRW_OPCODE_CONTINUE:
1014          /* FINISHME: We need to write the loop instruction support still. */
1015          if (intel->gen >= 6)
1016             gen6_CONT(p);
1017          else
1018             brw_CONT(p);
1019          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1020          break;
1021
1022       case BRW_OPCODE_WHILE:
1023          brw_WHILE(p);
1024          break;
1025
1026       default:
1027          generate_vs_instruction(inst, dst, src);
1028          break;
1029       }
1030
1031       if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1032          brw_dump_compile(p, stdout,
1033                           last_native_insn_offset, p->next_insn_offset);
1034       }
1035
1036       last_native_insn_offset = p->next_insn_offset;
1037    }
1038
1039    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1040       printf("\n");
1041    }
1042
1043    brw_set_uip_jip(p);
1044
1045    /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
1046     * emit issues, it doesn't get the jump distances into the output,
1047     * which is often something we want to debug.  So this is here in
1048     * case you're doing that.
1049     */
1050    if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
1051       brw_dump_compile(p, stdout, 0, p->next_insn_offset);
1052    }
1053 }
1054
1055 extern "C" {
1056
1057 bool
1058 brw_vs_emit(struct gl_shader_program *prog, struct brw_vs_compile *c)
1059 {
1060    struct brw_context *brw = c->func.brw;
1061    struct intel_context *intel = &c->func.brw->intel;
1062    bool start_busy = false;
1063    float start_time = 0;
1064
1065    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
1066       start_busy = (intel->batch.last_bo &&
1067                     drm_intel_bo_busy(intel->batch.last_bo));
1068       start_time = get_time();
1069    }
1070
1071    struct brw_shader *shader = NULL;
1072    if (prog)
1073       shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_VERTEX];
1074
1075    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
1076       if (shader) {
1077          printf("GLSL IR for native vertex shader %d:\n", prog->Name);
1078          _mesa_print_ir(shader->ir, NULL);
1079          printf("\n\n");
1080       } else {
1081          printf("ARB_vertex_program %d for native vertex shader\n",
1082                 c->vp->program.Base.Id);
1083          _mesa_print_program(&c->vp->program.Base);
1084       }
1085    }
1086
1087    if (unlikely(INTEL_DEBUG & DEBUG_PERF) && shader) {
1088       if (shader->compiled_once) {
1089          brw_vs_debug_recompile(brw, prog, &c->key);
1090       }
1091       if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
1092          perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1093                     (get_time() - start_time) * 1000);
1094       }
1095       shader->compiled_once = true;
1096    }
1097
1098    vec4_visitor v(c, prog, shader);
1099    if (!v.run()) {
1100       prog->LinkStatus = false;
1101       ralloc_strcat(&prog->InfoLog, v.fail_msg);
1102       return false;
1103    }
1104
1105    return true;
1106 }
1107
1108 } /* extern "C" */
1109
1110 } /* namespace brw */