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i965: Remove writemask support from brw_SAMPLE().
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_emit.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24
25 extern "C" {
26 #include "brw_eu.h"
27 #include "main/macros.h"
28 #include "program/prog_print.h"
29 #include "program/prog_parameter.h"
30 };
31
32 namespace brw {
33
34 struct brw_reg
35 vec4_instruction::get_dst(void)
36 {
37 struct brw_reg brw_reg;
38
39 switch (dst.file) {
40 case GRF:
41 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
42 brw_reg = retype(brw_reg, dst.type);
43 brw_reg.dw1.bits.writemask = dst.writemask;
44 break;
45
46 case MRF:
47 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
48 brw_reg = retype(brw_reg, dst.type);
49 brw_reg.dw1.bits.writemask = dst.writemask;
50 break;
51
52 case HW_REG:
53 brw_reg = dst.fixed_hw_reg;
54 break;
55
56 case BAD_FILE:
57 brw_reg = brw_null_reg();
58 break;
59
60 default:
61 assert(!"not reached");
62 brw_reg = brw_null_reg();
63 break;
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].imm.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].imm.i);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].imm.u);
94 break;
95 default:
96 assert(!"not reached");
97 brw_reg = brw_null_reg();
98 break;
99 }
100 break;
101
102 case UNIFORM:
103 brw_reg = stride(brw_vec4_grf(1 + (src[i].reg + src[i].reg_offset) / 2,
104 ((src[i].reg + src[i].reg_offset) % 2) * 4),
105 0, 4, 1);
106 brw_reg = retype(brw_reg, src[i].type);
107 brw_reg.dw1.bits.swizzle = src[i].swizzle;
108 if (src[i].abs)
109 brw_reg = brw_abs(brw_reg);
110 if (src[i].negate)
111 brw_reg = negate(brw_reg);
112
113 /* This should have been moved to pull constants. */
114 assert(!src[i].reladdr);
115 break;
116
117 case HW_REG:
118 brw_reg = src[i].fixed_hw_reg;
119 break;
120
121 case BAD_FILE:
122 /* Probably unused. */
123 brw_reg = brw_null_reg();
124 break;
125 case ATTR:
126 default:
127 assert(!"not reached");
128 brw_reg = brw_null_reg();
129 break;
130 }
131
132 return brw_reg;
133 }
134
135 vec4_generator::vec4_generator(struct brw_context *brw,
136 struct brw_vs_compile *c,
137 struct gl_shader_program *prog,
138 void *mem_ctx)
139 : brw(brw), c(c), prog(prog), mem_ctx(mem_ctx)
140 {
141 intel = &brw->intel;
142 vp = &c->vp->program;
143
144 shader = prog ? prog->_LinkedShaders[MESA_SHADER_VERTEX] : NULL;
145
146 p = rzalloc(mem_ctx, struct brw_compile);
147 brw_init_compile(brw, p, mem_ctx);
148 }
149
150 vec4_generator::~vec4_generator()
151 {
152 }
153
154 void
155 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
156 struct brw_reg dst,
157 struct brw_reg src)
158 {
159 brw_math(p,
160 dst,
161 brw_math_function(inst->opcode),
162 inst->base_mrf,
163 src,
164 BRW_MATH_DATA_VECTOR,
165 BRW_MATH_PRECISION_FULL);
166 }
167
168 static void
169 check_gen6_math_src_arg(struct brw_reg src)
170 {
171 /* Source swizzles are ignored. */
172 assert(!src.abs);
173 assert(!src.negate);
174 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
175 }
176
177 void
178 vec4_generator::generate_math1_gen6(vec4_instruction *inst,
179 struct brw_reg dst,
180 struct brw_reg src)
181 {
182 /* Can't do writemask because math can't be align16. */
183 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
184 check_gen6_math_src_arg(src);
185
186 brw_set_access_mode(p, BRW_ALIGN_1);
187 brw_math(p,
188 dst,
189 brw_math_function(inst->opcode),
190 inst->base_mrf,
191 src,
192 BRW_MATH_DATA_SCALAR,
193 BRW_MATH_PRECISION_FULL);
194 brw_set_access_mode(p, BRW_ALIGN_16);
195 }
196
197 void
198 vec4_generator::generate_math2_gen7(vec4_instruction *inst,
199 struct brw_reg dst,
200 struct brw_reg src0,
201 struct brw_reg src1)
202 {
203 brw_math2(p,
204 dst,
205 brw_math_function(inst->opcode),
206 src0, src1);
207 }
208
209 void
210 vec4_generator::generate_math2_gen6(vec4_instruction *inst,
211 struct brw_reg dst,
212 struct brw_reg src0,
213 struct brw_reg src1)
214 {
215 /* Can't do writemask because math can't be align16. */
216 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
217 /* Source swizzles are ignored. */
218 check_gen6_math_src_arg(src0);
219 check_gen6_math_src_arg(src1);
220
221 brw_set_access_mode(p, BRW_ALIGN_1);
222 brw_math2(p,
223 dst,
224 brw_math_function(inst->opcode),
225 src0, src1);
226 brw_set_access_mode(p, BRW_ALIGN_16);
227 }
228
229 void
230 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
231 struct brw_reg dst,
232 struct brw_reg src0,
233 struct brw_reg src1)
234 {
235 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
236 * "Message Payload":
237 *
238 * "Operand0[7]. For the INT DIV functions, this operand is the
239 * denominator."
240 * ...
241 * "Operand1[7]. For the INT DIV functions, this operand is the
242 * numerator."
243 */
244 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
245 struct brw_reg &op0 = is_int_div ? src1 : src0;
246 struct brw_reg &op1 = is_int_div ? src0 : src1;
247
248 brw_push_insn_state(p);
249 brw_set_saturate(p, false);
250 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
251 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
252 brw_pop_insn_state(p);
253
254 brw_math(p,
255 dst,
256 brw_math_function(inst->opcode),
257 inst->base_mrf,
258 op0,
259 BRW_MATH_DATA_VECTOR,
260 BRW_MATH_PRECISION_FULL);
261 }
262
263 void
264 vec4_generator::generate_tex(vec4_instruction *inst,
265 struct brw_reg dst,
266 struct brw_reg src)
267 {
268 int msg_type = -1;
269
270 if (intel->gen >= 5) {
271 switch (inst->opcode) {
272 case SHADER_OPCODE_TEX:
273 case SHADER_OPCODE_TXL:
274 if (inst->shadow_compare) {
275 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
276 } else {
277 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
278 }
279 break;
280 case SHADER_OPCODE_TXD:
281 if (inst->shadow_compare) {
282 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
283 assert(intel->is_haswell);
284 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
285 } else {
286 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
287 }
288 break;
289 case SHADER_OPCODE_TXF:
290 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
291 break;
292 case SHADER_OPCODE_TXS:
293 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
294 break;
295 default:
296 assert(!"should not get here: invalid VS texture opcode");
297 break;
298 }
299 } else {
300 switch (inst->opcode) {
301 case SHADER_OPCODE_TEX:
302 case SHADER_OPCODE_TXL:
303 if (inst->shadow_compare) {
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
305 assert(inst->mlen == 3);
306 } else {
307 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
308 assert(inst->mlen == 2);
309 }
310 break;
311 case SHADER_OPCODE_TXD:
312 /* There is no sample_d_c message; comparisons are done manually. */
313 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
314 assert(inst->mlen == 4);
315 break;
316 case SHADER_OPCODE_TXF:
317 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
318 assert(inst->mlen == 2);
319 break;
320 case SHADER_OPCODE_TXS:
321 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
322 assert(inst->mlen == 2);
323 break;
324 default:
325 assert(!"should not get here: invalid VS texture opcode");
326 break;
327 }
328 }
329
330 assert(msg_type != -1);
331
332 /* Load the message header if present. If there's a texture offset, we need
333 * to set it up explicitly and load the offset bitfield. Otherwise, we can
334 * use an implied move from g0 to the first message register.
335 */
336 if (inst->texture_offset) {
337 /* Explicitly set up the message header by copying g0 to the MRF. */
338 brw_push_insn_state(p);
339 brw_set_mask_control(p, BRW_MASK_DISABLE);
340 brw_MOV(p, retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
341 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
342
343 /* Then set the offset bits in DWord 2. */
344 brw_set_access_mode(p, BRW_ALIGN_1);
345 brw_MOV(p,
346 retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, inst->base_mrf, 2),
347 BRW_REGISTER_TYPE_UD),
348 brw_imm_uw(inst->texture_offset));
349 brw_pop_insn_state(p);
350 } else if (inst->header_present) {
351 /* Set up an implied move from g0 to the MRF. */
352 src = brw_vec8_grf(0, 0);
353 }
354
355 uint32_t return_format;
356
357 switch (dst.type) {
358 case BRW_REGISTER_TYPE_D:
359 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
360 break;
361 case BRW_REGISTER_TYPE_UD:
362 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
363 break;
364 default:
365 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
366 break;
367 }
368
369 brw_SAMPLE(p,
370 dst,
371 inst->base_mrf,
372 src,
373 SURF_INDEX_VS_TEXTURE(inst->sampler),
374 inst->sampler,
375 msg_type,
376 1, /* response length */
377 inst->mlen,
378 inst->header_present,
379 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
380 return_format);
381 }
382
383 void
384 vec4_generator::generate_urb_write(vec4_instruction *inst)
385 {
386 brw_urb_WRITE(p,
387 brw_null_reg(), /* dest */
388 inst->base_mrf, /* starting mrf reg nr */
389 brw_vec8_grf(0, 0), /* src */
390 false, /* allocate */
391 true, /* used */
392 inst->mlen,
393 0, /* response len */
394 inst->eot, /* eot */
395 inst->eot, /* writes complete */
396 inst->offset, /* urb destination offset */
397 BRW_URB_SWIZZLE_INTERLEAVE);
398 }
399
400 void
401 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
402 struct brw_reg index)
403 {
404 int second_vertex_offset;
405
406 if (intel->gen >= 6)
407 second_vertex_offset = 1;
408 else
409 second_vertex_offset = 16;
410
411 m1 = retype(m1, BRW_REGISTER_TYPE_D);
412
413 /* Set up M1 (message payload). Only the block offsets in M1.0 and
414 * M1.4 are used, and the rest are ignored.
415 */
416 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
417 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
418 struct brw_reg index_0 = suboffset(vec1(index), 0);
419 struct brw_reg index_4 = suboffset(vec1(index), 4);
420
421 brw_push_insn_state(p);
422 brw_set_mask_control(p, BRW_MASK_DISABLE);
423 brw_set_access_mode(p, BRW_ALIGN_1);
424
425 brw_MOV(p, m1_0, index_0);
426
427 if (index.file == BRW_IMMEDIATE_VALUE) {
428 index_4.dw1.ud += second_vertex_offset;
429 brw_MOV(p, m1_4, index_4);
430 } else {
431 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
432 }
433
434 brw_pop_insn_state(p);
435 }
436
437 void
438 vec4_generator::generate_scratch_read(vec4_instruction *inst,
439 struct brw_reg dst,
440 struct brw_reg index)
441 {
442 struct brw_reg header = brw_vec8_grf(0, 0);
443
444 gen6_resolve_implied_move(p, &header, inst->base_mrf);
445
446 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
447 index);
448
449 uint32_t msg_type;
450
451 if (intel->gen >= 6)
452 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
453 else if (intel->gen == 5 || intel->is_g4x)
454 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
455 else
456 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
457
458 /* Each of the 8 channel enables is considered for whether each
459 * dword is written.
460 */
461 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
462 brw_set_dest(p, send, dst);
463 brw_set_src0(p, send, header);
464 if (intel->gen < 6)
465 send->header.destreg__conditionalmod = inst->base_mrf;
466 brw_set_dp_read_message(p, send,
467 255, /* binding table index: stateless access */
468 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
469 msg_type,
470 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
471 2, /* mlen */
472 true, /* header_present */
473 1 /* rlen */);
474 }
475
476 void
477 vec4_generator::generate_scratch_write(vec4_instruction *inst,
478 struct brw_reg dst,
479 struct brw_reg src,
480 struct brw_reg index)
481 {
482 struct brw_reg header = brw_vec8_grf(0, 0);
483 bool write_commit;
484
485 /* If the instruction is predicated, we'll predicate the send, not
486 * the header setup.
487 */
488 brw_set_predicate_control(p, false);
489
490 gen6_resolve_implied_move(p, &header, inst->base_mrf);
491
492 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
493 index);
494
495 brw_MOV(p,
496 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
497 retype(src, BRW_REGISTER_TYPE_D));
498
499 uint32_t msg_type;
500
501 if (intel->gen >= 7)
502 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
503 else if (intel->gen == 6)
504 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
505 else
506 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
507
508 brw_set_predicate_control(p, inst->predicate);
509
510 /* Pre-gen6, we have to specify write commits to ensure ordering
511 * between reads and writes within a thread. Afterwards, that's
512 * guaranteed and write commits only matter for inter-thread
513 * synchronization.
514 */
515 if (intel->gen >= 6) {
516 write_commit = false;
517 } else {
518 /* The visitor set up our destination register to be g0. This
519 * means that when the next read comes along, we will end up
520 * reading from g0 and causing a block on the write commit. For
521 * write-after-read, we are relying on the value of the previous
522 * read being used (and thus blocking on completion) before our
523 * write is executed. This means we have to be careful in
524 * instruction scheduling to not violate this assumption.
525 */
526 write_commit = true;
527 }
528
529 /* Each of the 8 channel enables is considered for whether each
530 * dword is written.
531 */
532 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
533 brw_set_dest(p, send, dst);
534 brw_set_src0(p, send, header);
535 if (intel->gen < 6)
536 send->header.destreg__conditionalmod = inst->base_mrf;
537 brw_set_dp_write_message(p, send,
538 255, /* binding table index: stateless access */
539 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
540 msg_type,
541 3, /* mlen */
542 true, /* header present */
543 false, /* not a render target write */
544 write_commit, /* rlen */
545 false, /* eot */
546 write_commit);
547 }
548
549 void
550 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
551 struct brw_reg dst,
552 struct brw_reg index,
553 struct brw_reg offset)
554 {
555 assert(index.file == BRW_IMMEDIATE_VALUE &&
556 index.type == BRW_REGISTER_TYPE_UD);
557 uint32_t surf_index = index.dw1.ud;
558
559 if (intel->gen == 7) {
560 gen6_resolve_implied_move(p, &offset, inst->base_mrf);
561 brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
562 brw_set_dest(p, insn, dst);
563 brw_set_src0(p, insn, offset);
564 brw_set_sampler_message(p, insn,
565 surf_index,
566 0, /* LD message ignores sampler unit */
567 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
568 1, /* rlen */
569 1, /* mlen */
570 false, /* no header */
571 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
572 0);
573 return;
574 }
575
576 struct brw_reg header = brw_vec8_grf(0, 0);
577
578 gen6_resolve_implied_move(p, &header, inst->base_mrf);
579
580 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
581 offset);
582
583 uint32_t msg_type;
584
585 if (intel->gen >= 6)
586 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
587 else if (intel->gen == 5 || intel->is_g4x)
588 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
589 else
590 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
591
592 /* Each of the 8 channel enables is considered for whether each
593 * dword is written.
594 */
595 struct brw_instruction *send = brw_next_insn(p, BRW_OPCODE_SEND);
596 brw_set_dest(p, send, dst);
597 brw_set_src0(p, send, header);
598 if (intel->gen < 6)
599 send->header.destreg__conditionalmod = inst->base_mrf;
600 brw_set_dp_read_message(p, send,
601 surf_index,
602 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
603 msg_type,
604 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
605 2, /* mlen */
606 true, /* header_present */
607 1 /* rlen */);
608 }
609
610 void
611 vec4_generator::generate_vs_instruction(vec4_instruction *instruction,
612 struct brw_reg dst,
613 struct brw_reg *src)
614 {
615 vec4_instruction *inst = (vec4_instruction *)instruction;
616
617 switch (inst->opcode) {
618 case SHADER_OPCODE_RCP:
619 case SHADER_OPCODE_RSQ:
620 case SHADER_OPCODE_SQRT:
621 case SHADER_OPCODE_EXP2:
622 case SHADER_OPCODE_LOG2:
623 case SHADER_OPCODE_SIN:
624 case SHADER_OPCODE_COS:
625 if (intel->gen == 6) {
626 generate_math1_gen6(inst, dst, src[0]);
627 } else {
628 /* Also works for Gen7. */
629 generate_math1_gen4(inst, dst, src[0]);
630 }
631 break;
632
633 case SHADER_OPCODE_POW:
634 case SHADER_OPCODE_INT_QUOTIENT:
635 case SHADER_OPCODE_INT_REMAINDER:
636 if (intel->gen >= 7) {
637 generate_math2_gen7(inst, dst, src[0], src[1]);
638 } else if (intel->gen == 6) {
639 generate_math2_gen6(inst, dst, src[0], src[1]);
640 } else {
641 generate_math2_gen4(inst, dst, src[0], src[1]);
642 }
643 break;
644
645 case SHADER_OPCODE_TEX:
646 case SHADER_OPCODE_TXD:
647 case SHADER_OPCODE_TXF:
648 case SHADER_OPCODE_TXL:
649 case SHADER_OPCODE_TXS:
650 generate_tex(inst, dst, src[0]);
651 break;
652
653 case VS_OPCODE_URB_WRITE:
654 generate_urb_write(inst);
655 break;
656
657 case VS_OPCODE_SCRATCH_READ:
658 generate_scratch_read(inst, dst, src[0]);
659 break;
660
661 case VS_OPCODE_SCRATCH_WRITE:
662 generate_scratch_write(inst, dst, src[0], src[1]);
663 break;
664
665 case VS_OPCODE_PULL_CONSTANT_LOAD:
666 generate_pull_constant_load(inst, dst, src[0], src[1]);
667 break;
668
669 case SHADER_OPCODE_SHADER_TIME_ADD:
670 brw_shader_time_add(p, inst->base_mrf, SURF_INDEX_VS_SHADER_TIME);
671 break;
672
673 default:
674 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
675 _mesa_problem(ctx, "Unsupported opcode in `%s' in VS\n",
676 opcode_descs[inst->opcode].name);
677 } else {
678 _mesa_problem(ctx, "Unsupported opcode %d in VS", inst->opcode);
679 }
680 abort();
681 }
682 }
683
684 void
685 vec4_generator::generate_code(exec_list *instructions)
686 {
687 int last_native_insn_offset = 0;
688 const char *last_annotation_string = NULL;
689 const void *last_annotation_ir = NULL;
690
691 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
692 if (shader) {
693 printf("Native code for vertex shader %d:\n", prog->Name);
694 } else {
695 printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
696 }
697 }
698
699 foreach_list(node, instructions) {
700 vec4_instruction *inst = (vec4_instruction *)node;
701 struct brw_reg src[3], dst;
702
703 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
704 if (last_annotation_ir != inst->ir) {
705 last_annotation_ir = inst->ir;
706 if (last_annotation_ir) {
707 printf(" ");
708 if (shader) {
709 ((ir_instruction *) last_annotation_ir)->print();
710 } else {
711 const prog_instruction *vpi;
712 vpi = (const prog_instruction *) inst->ir;
713 printf("%d: ", (int)(vpi - vp->Base.Instructions));
714 _mesa_fprint_instruction_opt(stdout, vpi, 0,
715 PROG_PRINT_DEBUG, NULL);
716 }
717 printf("\n");
718 }
719 }
720 if (last_annotation_string != inst->annotation) {
721 last_annotation_string = inst->annotation;
722 if (last_annotation_string)
723 printf(" %s\n", last_annotation_string);
724 }
725 }
726
727 for (unsigned int i = 0; i < 3; i++) {
728 src[i] = inst->get_src(i);
729 }
730 dst = inst->get_dst();
731
732 brw_set_conditionalmod(p, inst->conditional_mod);
733 brw_set_predicate_control(p, inst->predicate);
734 brw_set_predicate_inverse(p, inst->predicate_inverse);
735 brw_set_saturate(p, inst->saturate);
736 brw_set_mask_control(p, inst->force_writemask_all);
737
738 switch (inst->opcode) {
739 case BRW_OPCODE_MOV:
740 brw_MOV(p, dst, src[0]);
741 break;
742 case BRW_OPCODE_ADD:
743 brw_ADD(p, dst, src[0], src[1]);
744 break;
745 case BRW_OPCODE_MUL:
746 brw_MUL(p, dst, src[0], src[1]);
747 break;
748 case BRW_OPCODE_MACH:
749 brw_set_acc_write_control(p, 1);
750 brw_MACH(p, dst, src[0], src[1]);
751 brw_set_acc_write_control(p, 0);
752 break;
753
754 case BRW_OPCODE_FRC:
755 brw_FRC(p, dst, src[0]);
756 break;
757 case BRW_OPCODE_RNDD:
758 brw_RNDD(p, dst, src[0]);
759 break;
760 case BRW_OPCODE_RNDE:
761 brw_RNDE(p, dst, src[0]);
762 break;
763 case BRW_OPCODE_RNDZ:
764 brw_RNDZ(p, dst, src[0]);
765 break;
766
767 case BRW_OPCODE_AND:
768 brw_AND(p, dst, src[0], src[1]);
769 break;
770 case BRW_OPCODE_OR:
771 brw_OR(p, dst, src[0], src[1]);
772 break;
773 case BRW_OPCODE_XOR:
774 brw_XOR(p, dst, src[0], src[1]);
775 break;
776 case BRW_OPCODE_NOT:
777 brw_NOT(p, dst, src[0]);
778 break;
779 case BRW_OPCODE_ASR:
780 brw_ASR(p, dst, src[0], src[1]);
781 break;
782 case BRW_OPCODE_SHR:
783 brw_SHR(p, dst, src[0], src[1]);
784 break;
785 case BRW_OPCODE_SHL:
786 brw_SHL(p, dst, src[0], src[1]);
787 break;
788
789 case BRW_OPCODE_CMP:
790 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
791 break;
792 case BRW_OPCODE_SEL:
793 brw_SEL(p, dst, src[0], src[1]);
794 break;
795
796 case BRW_OPCODE_DPH:
797 brw_DPH(p, dst, src[0], src[1]);
798 break;
799
800 case BRW_OPCODE_DP4:
801 brw_DP4(p, dst, src[0], src[1]);
802 break;
803
804 case BRW_OPCODE_DP3:
805 brw_DP3(p, dst, src[0], src[1]);
806 break;
807
808 case BRW_OPCODE_DP2:
809 brw_DP2(p, dst, src[0], src[1]);
810 break;
811
812 case BRW_OPCODE_F32TO16:
813 brw_F32TO16(p, dst, src[0]);
814 break;
815
816 case BRW_OPCODE_F16TO32:
817 brw_F16TO32(p, dst, src[0]);
818 break;
819
820 case BRW_OPCODE_IF:
821 if (inst->src[0].file != BAD_FILE) {
822 /* The instruction has an embedded compare (only allowed on gen6) */
823 assert(intel->gen == 6);
824 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
825 } else {
826 struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
827 brw_inst->header.predicate_control = inst->predicate;
828 }
829 break;
830
831 case BRW_OPCODE_ELSE:
832 brw_ELSE(p);
833 break;
834 case BRW_OPCODE_ENDIF:
835 brw_ENDIF(p);
836 break;
837
838 case BRW_OPCODE_DO:
839 brw_DO(p, BRW_EXECUTE_8);
840 break;
841
842 case BRW_OPCODE_BREAK:
843 brw_BREAK(p);
844 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
845 break;
846 case BRW_OPCODE_CONTINUE:
847 /* FINISHME: We need to write the loop instruction support still. */
848 if (intel->gen >= 6)
849 gen6_CONT(p);
850 else
851 brw_CONT(p);
852 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
853 break;
854
855 case BRW_OPCODE_WHILE:
856 brw_WHILE(p);
857 break;
858
859 default:
860 generate_vs_instruction(inst, dst, src);
861 break;
862 }
863
864 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
865 brw_dump_compile(p, stdout,
866 last_native_insn_offset, p->next_insn_offset);
867 }
868
869 last_native_insn_offset = p->next_insn_offset;
870 }
871
872 if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
873 printf("\n");
874 }
875
876 brw_set_uip_jip(p);
877
878 /* OK, while the INTEL_DEBUG=vs above is very nice for debugging VS
879 * emit issues, it doesn't get the jump distances into the output,
880 * which is often something we want to debug. So this is here in
881 * case you're doing that.
882 */
883 if (0 && unlikely(INTEL_DEBUG & DEBUG_VS)) {
884 brw_dump_compile(p, stdout, 0, p->next_insn_offset);
885 }
886 }
887
888 const unsigned *
889 vec4_generator::generate_assembly(exec_list *instructions,
890 unsigned *assembly_size)
891 {
892 brw_set_access_mode(p, BRW_ALIGN_16);
893 generate_code(instructions);
894 return brw_get_program(p, assembly_size);
895 }
896
897 } /* namespace brw */